// Copyright 2023 The Pigweed Authors
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy of
// the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// Update: 01/25 - Added logic to detect mode_i state change and assert reset.
//////////////////////////////////////////////////////////////////////////////////


module rst_sync (
    input  clk_i,
    input  rst_i,
    input  mode_i,
    output rst_o
);

  reg rst_i_r0, rst_i_r1, rst_i_r2, mode_i_r0;
  assign rst_o = rst_i_r2;

  reg [2:0] rst_state;
  reg [3:0] count;

  always @(posedge clk_i) begin
    case (rst_state)
      0: begin
        rst_i_r0 <= 1;
        rst_state <= 1;
        count <= 0;
      end
      1: begin
        rst_i_r0 <= 1;
        count <= count + 1;
        if (count >= 4'd9) rst_state <= 2;
      end
      2: begin
        rst_i_r0 <= 0;
        count <= 0;
        rst_state <= (mode_i_r0 ^ mode_i) ? 0 : 2;
      end
      default: rst_state <= 0;
    endcase
  end

  always @(posedge clk_i) begin
    mode_i_r0 <= mode_i;
  end

  always @(posedge clk_i or posedge rst_i) begin
    if (rst_i) begin
      // rst_i_r0<=1;
      rst_i_r1 <= 1;
      rst_i_r2 <= 1;
    end else begin
      // rst_i_r0<=rst_i;
      rst_i_r1 <= rst_i_r0;
      rst_i_r2 <= rst_i_r1;
    end
  end

endmodule