)]}'
{
  "commit": "39a239a1507b6985dfd2a4cf7e1036bafea27522",
  "tree": "7ee6a1e7a746082e6e1f40f8ccaf5d1ee3cbe573",
  "parents": [
    "37a38b73ef26730a8932448fa4daa00428c20d6f"
  ],
  "author": {
    "name": "Umang Shah",
    "email": "umangshah@google.com",
    "time": "Wed Dec 20 23:41:37 2023 +0000"
  },
  "committer": {
    "name": "CQ Bot Account",
    "email": "pigweed-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "time": "Wed Dec 20 23:41:37 2023 +0000"
  },
  "message": "fpga: Add initial Verilog build\n\nAlso applied Verilog auto-formatting with:\n\n  verible-verilog-format --inplace fpga/*.v\n\nChange-Id: I3520775fbca49519d8e20d934a7503110a70ff3f\nReviewed-on: https://pigweed-review.googlesource.com/c/gonk/+/185470\nPigweed-Auto-Submit: Anthony DiGirolamo \u003ctonymd@google.com\u003e\nReviewed-by: Umang Shah \u003cumangshah@google.com\u003e\nCommit-Queue: Auto-Submit \u003cauto-submit@pigweed-service-accounts.iam.gserviceaccount.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6958491c301e860d0775aace3a704fdc7d41e8f2",
      "old_mode": 33188,
      "old_path": "fpga/BUILD.gn",
      "new_id": "721056719c276c1b03647658b8d62f71dd033906",
      "new_mode": 33188,
      "new_path": "fpga/BUILD.gn"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "81ce6179fa3026efe46df36099eb780baa1f8e2f",
      "new_mode": 33188,
      "new_path": "fpga/gonk/csa_ctl_top.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0196621d9c2598e96c26db2ce89cac9a834ad999",
      "new_mode": 33188,
      "new_path": "fpga/gonk/pll.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f2fe98d100d9934c7624c2020ee1c9ed4922413c",
      "new_mode": 33188,
      "new_path": "fpga/gonk/rst_sync.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6946427fad974151a79477a450f4f7f0f73f6b2e",
      "new_mode": 33188,
      "new_path": "fpga/gonk/sig_sync.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c3f37c25d81c04f522eb9701583e0f924c56b304",
      "new_mode": 33188,
      "new_path": "fpga/gonk/spi_m_core.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e1b03774645061abbbc7b7ea5ccf99971ae1e94e",
      "new_mode": 33188,
      "new_path": "fpga/gonk/spi_m_core_ctl.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "349f5a8deae072e299bc7d035458a49b97b23384",
      "new_mode": 33188,
      "new_path": "fpga/gonk/spi_s_core.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "40a43c35198a881b5bc43c51ad233984d1bdbb31",
      "new_mode": 33188,
      "new_path": "fpga/gonk/top.pcf"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e1773ec7aad22e0c730459b1049aabf0733bbaa7",
      "new_mode": 33188,
      "new_path": "fpga/gonk/top.v"
    }
  ]
}