tree 7ee6a1e7a746082e6e1f40f8ccaf5d1ee3cbe573
parent 37a38b73ef26730a8932448fa4daa00428c20d6f
author Umang Shah <umangshah@google.com> 1703115697 +0000
committer CQ Bot Account <pigweed-scoped@luci-project-accounts.iam.gserviceaccount.com> 1703115697 +0000

fpga: Add initial Verilog build

Also applied Verilog auto-formatting with:

  verible-verilog-format --inplace fpga/*.v

Change-Id: I3520775fbca49519d8e20d934a7503110a70ff3f
Reviewed-on: https://pigweed-review.googlesource.com/c/gonk/+/185470
Pigweed-Auto-Submit: Anthony DiGirolamo <tonymd@google.com>
Reviewed-by: Umang Shah <umangshah@google.com>
Commit-Queue: Auto-Submit <auto-submit@pigweed-service-accounts.iam.gserviceaccount.com>