lib/adc: Continuous read fixes
- Shorten delay to 1ms between each continuous read
- Use WaitForFpgaIOValid() between continous reads instead of
checking for a pulse.
- Update to latest verilog with fixed valid signal handling.
Change-Id: Ieca3a955803b06287245e90f5574b8abdd35ace6
Reviewed-on: https://pigweed-review.googlesource.com/c/gonk/+/189370
Reviewed-by: Umang Shah <umangshah@google.com>
Commit-Queue: Anthony DiGirolamo <tonymd@google.com>
diff --git a/applications/fpga_config/main.cc b/applications/fpga_config/main.cc
index fcb94b4..41829fe 100644
--- a/applications/fpga_config/main.cc
+++ b/applications/fpga_config/main.cc
@@ -111,7 +111,7 @@
}
}
- if (this_update > last_update + 1000) {
+ if (this_update > last_update + 1) {
PW_LOG_INFO("ADC update: %d", update_count);
pw::Status update_result = fpga_adc.UpdateContinuousMeasurements();
diff --git a/fpga/gonk/csa_ctl_top.v b/fpga/gonk/csa_ctl_top.v
index 81ce617..5d8609c 100644
--- a/fpga/gonk/csa_ctl_top.v
+++ b/fpga/gonk/csa_ctl_top.v
@@ -180,6 +180,7 @@
spi_m_core_ctl csa_1 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r1),
.en_i(en_r1),
.mode_i(mode_i),
@@ -200,6 +201,7 @@
spi_m_core_ctl csa_2 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r2),
.en_i(en_r2),
.mode_i(mode_i),
@@ -220,6 +222,7 @@
spi_m_core_ctl csa_3 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r3),
.en_i(en_r3),
.mode_i(mode_i),
@@ -240,6 +243,7 @@
spi_m_core_ctl csa_4 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r4),
.en_i(en_r4),
.mode_i(mode_i),
@@ -260,6 +264,7 @@
spi_m_core_ctl csa_5 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r5),
.en_i(en_r5),
.mode_i(mode_i),
@@ -281,6 +286,7 @@
spi_m_core_ctl csa_6 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r6),
.en_i(en_r6),
.mode_i(mode_i),
@@ -301,6 +307,7 @@
spi_m_core_ctl csa_7 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r7),
.en_i(en_r7),
.mode_i(mode_i),
@@ -321,6 +328,7 @@
spi_m_core_ctl csa_8 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r8),
.en_i(en_r8),
.mode_i(mode_i),
@@ -341,6 +349,7 @@
spi_m_core_ctl csa_9 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r9),
.en_i(en_r9),
.mode_i(mode_i),
@@ -361,6 +370,7 @@
spi_m_core_ctl csa_10 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r10),
.en_i(en_r10),
.mode_i(mode_i),
@@ -381,6 +391,7 @@
spi_m_core_ctl csa_11 (
.mclk_i(mclk_i),
.rst_i(rst_i_r),
+ .dn_clr_i(dn_clr_i),
.r_w_en_i(r_w_en_r11),
.en_i(en_r11),
.mode_i(mode_i),
@@ -406,7 +417,7 @@
end else begin
poll_dn_o <= poll_dn_r;
dn_o <= dn_r;
- en_r <= en_i; //(en_i & !mode_i) ;
+ en_r <= en_i; // (en_i & !mode_i) ;
end
end
@@ -545,11 +556,11 @@
reg poll_dn_latch_0_r, poll_dn_latch_1_r, poll_dn_latch_2_r, poll_dn_latch_3_r;
wire poll_dn_latch_0, poll_dn_latch_1, poll_dn_latch_2, poll_dn_latch_3, poll_dn_w;
- assign poll_dn_latch_0 = (poll_dn_latch_r7 | poll_dn_latch_r9 | poll_dn_latch_r10); // bank0
- assign poll_dn_latch_1 = (poll_dn_latch_r5 | poll_dn_latch_r8 | poll_dn_latch_r1);
- assign poll_dn_latch_2 = (poll_dn_latch_r4 | poll_dn_latch_r6 | poll_dn_latch_r3);
- assign poll_dn_latch_3 = (poll_dn_latch_r2 | poll_dn_latch_r11);
- assign poll_dn_w = (poll_dn_latch_0_r | poll_dn_latch_1_r | poll_dn_latch_2_r | poll_dn_latch_3_r);
+ assign poll_dn_latch_0 = (poll_dn_latch_r7 & poll_dn_latch_r9 & poll_dn_latch_r10); // bank0
+ assign poll_dn_latch_1 = (poll_dn_latch_r5 & poll_dn_latch_r8 & poll_dn_latch_r1);
+ assign poll_dn_latch_2 = (poll_dn_latch_r4 & poll_dn_latch_r6 & poll_dn_latch_r3);
+ assign poll_dn_latch_3 = (poll_dn_latch_r2 & poll_dn_latch_r11);
+ assign poll_dn_w = (poll_dn_latch_0_r & poll_dn_latch_1_r & poll_dn_latch_2_r & poll_dn_latch_3_r);
always @(posedge mclk_i) begin
if (rst_i_r) begin
diff --git a/fpga/gonk/rst_sync.v b/fpga/gonk/rst_sync.v
index f2fe98d..2b6f09f 100644
--- a/fpga/gonk/rst_sync.v
+++ b/fpga/gonk/rst_sync.v
@@ -15,17 +15,18 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
-//
+// Update: 01/25 - Added logic to detect mode_i state change and assert reset.
//////////////////////////////////////////////////////////////////////////////////
module rst_sync (
input clk_i,
input rst_i,
+ input mode_i,
output rst_o
);
- reg rst_i_r0, rst_i_r1, rst_i_r2;
+ reg rst_i_r0, rst_i_r1, rst_i_r2, mode_i_r0;
assign rst_o = rst_i_r2;
reg [2:0] rst_state;
@@ -46,11 +47,16 @@
2: begin
rst_i_r0 <= 0;
count <= 0;
+ rst_state <= (mode_i_r0 ^ mode_i) ? 0 : 2;
end
default: rst_state <= 0;
endcase
end
+ always @(posedge clk_i) begin
+ mode_i_r0 <= mode_i;
+ end
+
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
// rst_i_r0<=1;
diff --git a/fpga/gonk/sig_sync.v b/fpga/gonk/sig_sync.v
index 6946427..30066ae 100644
--- a/fpga/gonk/sig_sync.v
+++ b/fpga/gonk/sig_sync.v
@@ -30,16 +30,16 @@
assign sig_o = sig_i_r2;
always @(posedge clk_i) begin
- if (rst_i) begin
- sig_i_r0 <= 0;
- sig_i_r1 <= 0;
- sig_i_r2 <= 0;
- end else begin
- sig_i_r0 <= sig_i;
- sig_i_r1 <= sig_i_r0;
- sig_i_r2 <= sig_i_r1;
+ // if (rst_i) begin Commented out - to get rid of xor'ed pulses in rst_sync.v
+ // sig_i_r0 <= 0;
+ // sig_i_r1 <= 0;
+ // sig_i_r2 <= 0;
+ // end else begin
+ sig_i_r0 <= sig_i;
+ sig_i_r1 <= sig_i_r0;
+ sig_i_r2 <= sig_i_r1;
- end
+ // end
end
endmodule
diff --git a/fpga/gonk/spi_m_core_ctl.v b/fpga/gonk/spi_m_core_ctl.v
index e1b0377..ca761f4 100644
--- a/fpga/gonk/spi_m_core_ctl.v
+++ b/fpga/gonk/spi_m_core_ctl.v
@@ -26,6 +26,7 @@
input r_w_en_i,
input en_i,
input mode_i,
+ input dn_clr_i, // Added to sync ADC polling logic with spi_s_core.v
input [5:0] rwaddr_i,
input [15:0] wdata_i,
output reg dn_o,
@@ -137,7 +138,7 @@
if (mode_i) begin
case (poll_state)
S0: begin
- if (alert_n_r2) poll_state <= S0;
+ if (alert_n_r2 | dn_clr_i) poll_state <= S0;
else poll_state <= S1;
end
S1: begin
@@ -148,17 +149,20 @@
else poll_state <= S2;
end
S3: begin
- if (poll_addr_select[1]) // Change to "poll_addr_select<=2" if alert doesn't clear after reading the vbus and vshunt registers.
+ if (poll_addr_select>2) begin // Changed to ">2" to clear alert after reading the vbus and vshunt registers.
poll_state <= S4;
- else begin
- if (wait_ctr_r[2]) //(wait_ctr_r>=5) // Changed to one bit comparator.
+ end else begin
+ if (wait_ctr_r[2]) // (wait_ctr_r>=5) // Changed to one bit comparator.
poll_state <= S1;
else poll_state <= S3;
end
end
S4: begin
- if (alert_n_r2) poll_state <= S0;
- else poll_state <= S4;
+ if (dn_clr_i)
+ poll_state <= S0; // alert_n_r2 // Changed to pause countinous reads updates causing this module to go out of sync wrt to spi_s_core.v
+ else begin
+ poll_state <= S4;
+ end
end
default: poll_state <= S0;
endcase
@@ -189,13 +193,13 @@
wait_ctr_en_r <= 0;
end
S3: begin // min wait time b/w 2 transaction
- poll_dn_o <= 0;
+ poll_dn_o <= (poll_addr_select > 2) ? 1 : 0;
spi_poll_en_r <= 0;
wait_ctr_en_r <= 1;
end
S4: begin
spi_poll_en_r <= 0;
- poll_dn_o <= 1;
+ poll_dn_o <= 0;
wait_ctr_en_r <= 0;
end
endcase
diff --git a/fpga/gonk/spi_s_core.v b/fpga/gonk/spi_s_core.v
index 349f5a8..d8f1af0 100644
--- a/fpga/gonk/spi_s_core.v
+++ b/fpga/gonk/spi_s_core.v
@@ -94,7 +94,7 @@
reg [2:0] spi_s_state;
reg [5:0] rwaddr_latch_r, poll_dat_ctr_r;
reg [6:0] dat_in_ctr_r, data_count_max_r, dat_out_ctr;
- reg [15:0] rwaddr_r, wdata_r, wdata_latch_r;
+ reg [15:0] rwaddr_r, wdata_r, wdata_latch_r, poll_dat_bits_ctr_r;
reg [23:0] poll_dat_r;
reg [39:0] dat_in_r, dat_out_r, dat_in_r1;
@@ -105,8 +105,6 @@
assign poll_ctr_en_w = dat_out_ctr_clr_r & dat_out_ctr_clr;
assign data_valid_o = (dat_out_en_r | wr_dn_valid_r);
- wire [10:0] test;
- assign test = (data_count_max_r - 1) - dat_out_ctr;
always @(posedge mclk_i) begin
rst_i_r <= rst_i;
@@ -223,7 +221,7 @@
end
end
DN: begin
- spi_s_state <= IDLE; //(pos_edge)?IDLE:DN;
+ spi_s_state <= IDLE; // (pos_edge)?IDLE:DN;
end
default: spi_s_state <= IDLE;
endcase
@@ -245,14 +243,22 @@
end
always @(posedge mclk_i) begin
- if (rst_i_r) miso_o <= 1;
- else begin
+ if (rst_i_r) begin
+ miso_o <= 1;
+ end else begin
if (dat_out_en_r) begin
if (pos_edge) miso_o <= dat_out_r[((data_count_max_r-1)-dat_out_ctr)];
end else miso_o <= 1;
end
end
+ always @(posedge mclk_i) begin // Test only logic to verify total number of clock cycles. NC
+ if (rst_i_r | poll_dat_bits_ctr_r == 528) poll_dat_bits_ctr_r <= 0;
+ else begin
+ if (mode_i & neg_edge) poll_dat_bits_ctr_r <= poll_dat_bits_ctr_r + 1;
+ end
+ end
+
always @(posedge mclk_i) begin
if (rst_i_r | dat_out_ctr_clr) dat_out_ctr <= 0;
else begin
@@ -309,12 +315,18 @@
always @(posedge mclk_i) begin
if (rst_i_r) dat_out_dn_r <= 0;
- else
- dat_out_dn_r <= (((!mode_i) & dat_out_ctr_clr) | (mode_i & poll_dat_ctr_clr)); // pos_edge &
+ else dat_out_dn_r <= (((!mode_i) & dat_out_ctr_clr) | (mode_i & poll_dat_ctr_clr));
+ end
+
+ reg [2:0] dat_out_dn_latch_ctr; // Added to clear latch to fix continous read.
+
+ always @(posedge mclk_i) begin
+ if (rst_i_r) dat_out_dn_latch_ctr <= 0;
+ dat_out_dn_latch_ctr <= (dat_out_dn_latch) ? dat_out_dn_latch_ctr + 1 : 0;
end
always @(posedge mclk_i) begin
- if (rst_i_r | neg_edge) dat_out_dn_latch <= 0;
+ if (rst_i_r | neg_edge | dat_out_dn_latch_ctr == 7) dat_out_dn_latch <= 0;
else if (dat_out_dn_r) dat_out_dn_latch <= 1;
end
@@ -328,7 +340,7 @@
always @(posedge mclk_i) begin
if (rst_i_r) dn_clr_o <= 0;
else begin
- dn_clr_o <= ((!mode_i & dn_i) | (mode_i & poll_dn_i));
+ dn_clr_o <= ((!mode_i & dn_i) | (mode_i & dat_out_dn_latch));//Changed from poll_dn_i -(Added multi-cycle path) for clear pulse.
end
end
diff --git a/fpga/gonk/top.v b/fpga/gonk/top.v
index 48b369b..7e222ed 100644
--- a/fpga/gonk/top.v
+++ b/fpga/gonk/top.v
@@ -22,8 +22,8 @@
input op_mode_i,
output data_valid_o,
output led,
- input ice_prog_spi_io0,
- input ice_prog_spi_io1,
+ input ice_prog_spi_io0,
+ input ice_prog_spi_io1,
// spi secondary interface
input sl_sclk_i_0,
@@ -108,8 +108,8 @@
wire [23:0] vbus_7 ,vshunt_7,vbus_8 ,vshunt_8 ,vbus_9 ,vshunt_9 ,vbus_10 ,vshunt_10 ,vbus_11 ,vshunt_11;
wire [39:0] rdata_w;
- //assign ice_prog_spi_io0 = 1'bz; assigned as input. same as output hi-z.
- //assign ice_prog_spi_io1 = 1'bz;
+ // Assign ice_prog_spi_io0 = 1'bz; assigned as input. same as output hi-z.
+ // Assign ice_prog_spi_io1 = 1'bz;
pll pll_inst (
.clock_in (clk_i),
@@ -142,6 +142,31 @@
.poll_dn_i(poll_dn_w),
.dn_i(trf_dn_w),
.dn_clr_o(dn_clr),
+
+ // DEBUG: hard coded vbus and vshunt values
+ // .vbus_1(1),
+ // .vshunt_1(2),
+ // .vbus_2(3),
+ // .vshunt_2(4),
+ // .vbus_3(5),
+ // .vshunt_3(6),
+ // .vbus_4(7),
+ // .vshunt_4(8),
+ // .vbus_5(9),
+ // .vshunt_5(10),
+ // .vbus_6(11),
+ // .vshunt_6(12),
+ // .vbus_7(13),
+ // .vshunt_7(14),
+ // .vbus_8(15),
+ // .vshunt_8(16),
+ // .vbus_9(17),
+ // .vshunt_9(19),
+ // .vbus_10(20),
+ // .vshunt_10(21),
+ // .vbus_11(22),
+ // .vshunt_11(23)
+
.vbus_1(vbus_1),
.vshunt_1(vshunt_1),
.vbus_2(vbus_2),
@@ -165,35 +190,13 @@
.vbus_11(vbus_11),
.vshunt_11(vshunt_11)
);
- //
- // .vbus_1(1),// vbus_1),
- // .vshunt_1(2),
- // .vbus_2(3),
- // .vshunt_2(4),
- // .vbus_3(5),
- // .vshunt_3(6),
- // .vbus_4(7),
- // .vshunt_4(8),
- // .vbus_5(9),
- // .vshunt_5(10),
- // .vbus_6(11),
- // .vshunt_6(12),
- // .vbus_7(13),
- // .vshunt_7(14),
- // .vbus_8(15),
- // .vshunt_8(16),
- // .vbus_9(17),
- // .vshunt_9(19),
- // .vbus_10(20),
- // .vshunt_10(21),
- // .vbus_11(22),
- // .vshunt_11(23));
rst_sync rst_sync_inst (
- .clk_i(mclk),
- .rst_i(rst_i),
- .rst_o(rst_i_sync)
+ .clk_i (mclk),
+ .rst_i (rst_i),
+ .mode_i(mode_i_sync),
+ .rst_o (rst_i_sync)
);
sig_sync op_mode_sync (
@@ -217,7 +220,7 @@
//
.dn_clr_i(dn_clr), // Use to clear data-valid. Short to trf_dn_o of spi core.
.poll_dn_o(poll_dn_w),
- // .poll_dn(),// NC. Only for bringup
+ // .poll_dn - NC. Only for bringup
// spi
.miso_i_1(miso_i_1),
.alertl_i_1(alertl_i_1),
diff --git a/lib/adc/adc.cc b/lib/adc/adc.cc
index 96df067..441e1c4 100644
--- a/lib/adc/adc.cc
+++ b/lib/adc/adc.cc
@@ -307,7 +307,7 @@
StartSpiTransaction();
- Status wait_result = WaitForFpgaIOValidPulse();
+ Status wait_result = WaitForFpgaIOValid();
if (!wait_result.ok()) {
EndSpiTransaction();
return wait_result;
