commit | a2055834541f3582b4352d6775db2ab12d3109bb | [log] [tgz] |
---|---|---|
author | pigweed-roller <pigweed-roller@pigweed-service-accounts.iam.gserviceaccount.com> | Wed Jan 03 09:34:26 2024 +0000 |
committer | CQ Bot Account <pigweed-scoped@luci-project-accounts.iam.gserviceaccount.com> | Wed Jan 03 09:34:26 2024 +0000 |
tree | dfbca78dcc1e0f630f3e05f69c68008b737475c5 | |
parent | 42a0b2da47239013c0f9885c371441eeb51d3a95 [diff] |
[third_party/pigweed] Roll 5 commits cbe50f75e2ca9de pw_ide: Improve VSC extension UX c09ca7786d475d2 pw_env_setup: Prevent NPM output from interrupting a49938f32d4beff docs: Rework first-time setup 3e12ae03b72ab8e pw_tokenizer: Make Rust hashing function const d7d4dccfa5a43c9 docs: Add troubleshooting section to Bazel quickst https://pigweed.googlesource.com/pigweed/pigweed third_party/pigweed Rolled-Commits: 355d7079513c703..cbe50f75e2ca9de Roller-URL: https://ci.chromium.org/b/8759932747210141217 GitWatcher: ignore CQ-Do-Not-Cancel-Tryjobs: true Change-Id: I35ea0445c20d87ea62f66a0e5265eff1b57bf3b9 Reviewed-on: https://pigweed-review.googlesource.com/c/gonk/+/186710 Commit-Queue: Pigweed Roller <pigweed-roller@pigweed-service-accounts.iam.gserviceaccount.com> Bot-Commit: Pigweed Roller <pigweed-roller@pigweed-service-accounts.iam.gserviceaccount.com>
Clone the repo
git clone https://pigweed.googlesource.com/pigweed/gonk
Source bootstrap.sh
to download all compilers and tooling into the environment
directory:
. ./bootstrap.sh
This should init all git submodules for you.
From here on the Pigweed environment is activated. You can activate the environment in a new shell without re-running bootstrap by sourcing activate.sh
. ./activate.sh
Build for the host and device by running:
pw build
This is mostly a shortcut with nice output for running gn gen out/gn
and ninja -C out/gn
.
The build commands are defined in: //tools/gonk_tools/build_project.py
.
The Verilog build requires the following to be installed on Linux:
sudo apt install fpga-icestorm nextpnr-ice40 yosys
Run this to compile the Gonk Verilog:
pw build
The bitstream files will be written with the .bin
extenson under ./out/gn/obj/fpga/*/*.bin
along with log output files.
For example:
$ ls ./out/gn/obj/fpga/toplevel/ nextpnr-log.txt toplevel.asc toplevel.bin toplevel.json toplevel_timing_report.json toplevel_timing_report.txt yosys-log.txt
fpga_config
ExampleFlash the stm32f7 and launch the write_fpga.py
script on a bitstream file.
dfu-util
Unplug gonk from USB and replug with MODE button held down.
Run pw flash
on the MCU binary.
pw flash ./out/gn/arduino_size_optimized/obj/applications/fpga_config/fpga_config.bin
Write an FPGA bitstream with the write_fpga.py
script:
python ./tools/gonk_tools/write_fpga.py ./applications/fpga_config/fpga_blinky.bin
spi_flash_test
Exampledfu-util
Unplug gonk from USB and replug with MODE button held down.
Run pw flash
on the MCU binary.
pw flash ./out/gn/arduino_size_optimized/obj/applications/spi_flash_test/spi_flash_test.bin
Unplug Gonk from USB and replug to reset the hardware. SPI bus issues have been observed without this step.
Connect over serial.
python -m serial.tools.miniterm --raw /dev/ttyGonk 1000000
You should see output matching:
--- Miniterm on /dev/ttyGonk 1000000,8,N,1 --- --- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H --- INF Device id: 1f 84 1 INF Device id: 1f 84 1 INF Device id: 1f 84 1 INF Device id: 1f 84 1
./scripts/flash-with-blackmagic-probe.sh ./out/gn/arduino_size_optimized/obj/applications/spi_flash_test/bin/spi_flash_test.elf
Run the host app and connect to it via pw-system-console
:
./out/gn/host_device_simulator.speed_optimized/obj/applications/system_example/bin/system_example & \ pw-system-console --socket-addr default \ --proto-globs third_party/pigweed/pw_rpc/echo.proto ; \ killall system_example
Flashing
openocd -s $PW_PIGWEED_CIPD_INSTALL_DIR/share/openocd/scripts \ -f $GONK_ROOT/targets/stm32f769i_disc0_stm32cube/openocd_stm32f7xx.cfg \ -c "program out/gn/stm32f769i_disc0_stm32cube.size_optimized/obj/applications/system_example/bin/system_example.elf reset exit"
Checkout the desired commits in each of these submodules:
third_party/stm32cube_f7/cmsis_core third_party/stm32cube_f7/cmsis_device third_party/stm32cube_f7/hal_driver
Then run from Gonk root:
python -m pw_stm32cube_build gen_file_list third_party/stm32cube_f7
| Net | STM32 Pin | STM32 Function | Function | |--------+-----------+----------------+----------| | STATUS | PB13 | GPIO_Output | STAT LED |
Net | STM32 Pin | STM32 Function | Flash Pin |
---|---|---|---|
ICE_SPI_SS | PD2 | GPIO_Output | S# |
ICE_SPI_MISO | PB4 | SPI1_MISO | DQ1 |
ICE_SPI_MOSI | PB5 | SPI1_MOSI | DQ0 |
ICE_SPI_SCK | PB3 | SPI1_SCK | C |
FLASH_HOLD | PC11 | GPIO_Output | HOLD#/DQ3 |
FLASH_WP | PC12 | GPIO_Output | W#/VPP/DQ2 |
Net | Function | FPGA IO# | STM32 Pin | STM32 Function | Notes |
---|---|---|---|---|---|
FPGA_IO_SPARE_0_2 | rst_i | 135 | PA0 | GPIO_Output | Active high |
FPGA_IO_SPARE_0_0 | mode_i | 137 | PB11 | GPIO_Output | FPGA operation mode |
FPGA_IO_SPARE_0_1 | valid_o | 136 | PB10 | GPIO_Output | Data/Transfer Valid |
DSPI_SCK | sclk_i | 76 | PB2 | QUADSPI_CLK | |
DSPI_CS | cs_n | 75 | PB6 | QUADSPI_BK1_NCS | |
DSPI_IO1 | mosi_i | 74 | PC10 | QUADSPI_BK1_IO1 | |
DSPI_IO0 | miso_i | 73 | PC9 | QUADSPI_BK1_IO0 |