commit | c846a8ca79ce32505b71dcb412f31a0ad998d544 | [log] [tgz] |
---|---|---|
author | Anthony DiGirolamo <tonymd@google.com> | Thu Feb 08 01:38:59 2024 +0000 |
committer | CQ Bot Account <pigweed-scoped@luci-project-accounts.iam.gserviceaccount.com> | Thu Feb 08 01:38:59 2024 +0000 |
tree | e134310b2f5efe48f6b55d836d2ba8c6bd98fedf | |
parent | a13324547d0d03859a436f16a6b9989b9e515763 [diff] |
lib/adc: SelectContinuousReadAdcs - Adds Adc::SelectContinuousReadAdcs which allows setting which ADC channels are sampled in continuous read mode. - Fix missing static_cast in Adc::VoltageMeasurement() - Correct continuous read mode order to vshunt followed by vbus. Change-Id: I0590af949399b6d46fd930df7575bab9f2fa2222 Reviewed-on: https://pigweed-review.googlesource.com/c/gonk/+/189640 Commit-Queue: Anthony DiGirolamo <tonymd@google.com> Reviewed-by: Umang Shah <umangshah@google.com> Reviewed-by: Eric Holland <hollande@google.com>
Clone the repo
git clone https://pigweed.googlesource.com/pigweed/gonk
Source bootstrap.sh
to download all compilers and tooling into the environment
directory:
. ./bootstrap.sh
This should init all git submodules for you.
From here on the Pigweed environment is activated. You can activate the environment in a new shell without re-running bootstrap by sourcing activate.sh
. ./activate.sh
Build for the host and device by running:
pw build
This is mostly a shortcut with nice output for running gn gen out/gn
and ninja -C out/gn
.
The build commands are defined in: //tools/gonk_tools/build_project.py
.
The Verilog build requires the following to be installed on Linux:
sudo apt install fpga-icestorm nextpnr-ice40 yosys
Run this to compile the Gonk Verilog:
pw build
The bitstream files will be written with the .bin
extenson under ./out/gn/obj/fpga/*/*.bin
along with log output files.
For example:
$ ls ./out/gn/obj/fpga/toplevel/ nextpnr-log.txt toplevel.asc toplevel.bin toplevel.json toplevel_timing_report.json toplevel_timing_report.txt yosys-log.txt
fpga_config
ExampleFlash the stm32f7 and launch the write_fpga.py
script on a bitstream file.
dfu-util
Unplug gonk from USB and replug with MODE button held down.
Run pw flash
on the MCU binary.
pw flash ./out/gn/arduino_size_optimized/obj/applications/fpga_config/fpga_config.bin
Write an FPGA bitstream with the write_fpga.py
script:
python ./tools/gonk_tools/write_fpga.py ./applications/fpga_config/fpga_blinky.bin
spi_flash_test
Exampledfu-util
Unplug gonk from USB and replug with MODE button held down.
Run pw flash
on the MCU binary.
pw flash ./out/gn/arduino_size_optimized/obj/applications/spi_flash_test/spi_flash_test.bin
Unplug Gonk from USB and replug to reset the hardware. SPI bus issues have been observed without this step.
Connect over serial.
python -m serial.tools.miniterm --raw /dev/ttyGonk 1000000
You should see output matching:
--- Miniterm on /dev/ttyGonk 1000000,8,N,1 --- --- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H --- INF Device id: 1f 84 1 INF Device id: 1f 84 1 INF Device id: 1f 84 1 INF Device id: 1f 84 1
./scripts/flash-with-blackmagic-probe.sh ./out/gn/arduino_size_optimized/obj/applications/spi_flash_test/bin/spi_flash_test.elf
Run the host app and connect to it via pw-system-console
:
./out/gn/host_device_simulator.speed_optimized/obj/applications/system_example/bin/system_example & \ pw-system-console --socket-addr default \ --proto-globs third_party/pigweed/pw_rpc/echo.proto ; \ killall system_example
Flashing
openocd -s $PW_PIGWEED_CIPD_INSTALL_DIR/share/openocd/scripts \ -f $GONK_ROOT/targets/stm32f769i_disc0_stm32cube/openocd_stm32f7xx.cfg \ -c "program out/gn/stm32f769i_disc0_stm32cube.size_optimized/obj/applications/system_example/bin/system_example.elf reset exit"
Checkout the desired commits in each of these submodules:
third_party/stm32cube_f7/cmsis_core third_party/stm32cube_f7/cmsis_device third_party/stm32cube_f7/hal_driver
Then run from Gonk root:
python -m pw_stm32cube_build gen_file_list third_party/stm32cube_f7
Net | STM32 Pin | STM32 Function | Function |
---|---|---|---|
STATUS | PB13 | GPIO_Output | STAT LED |
Net | FPGA IO# | STM32 Pin | STM32 Function | Flash Pin |
---|---|---|---|---|
ICE_SPI_SS | 71 | PD2 | GPIO_Output | S# |
ICE_SPI_MISO | 68 | PB4 | SPI1_MISO | DQ1 |
ICE_SPI_MOSI | 67 | PB5 | SPI1_MOSI | DQ0 |
ICE_SPI_SCK | 70 | PB3 | SPI1_SCK | C |
FLASH_HOLD | 63 | PC11 | GPIO_Output | HOLD#/DQ3 |
FLASH_WP | 64 | PC12 | GPIO_Output | W#/VPP/DQ2 |
Net | Function | FPGA IO# | STM32 Pin | STM32 Function | Notes |
---|---|---|---|---|---|
FPGA_IO_SPARE_0_2 | rst_i | 135 | PA0 | GPIO_Output | Active high |
FPGA_IO_SPARE_0_0 | mode_i | 137 | PB11 | GPIO_Output | FPGA operation mode |
DSPI_CS | valid_o | 75 | PB6 | GPIO_Output | Data/Transfer Valid |
FPGA_IO_SPARE_1_1 | miso_i | 101 | PC2 | SPI1_MISO | |
FPGA_IO_SPARE_1_0 | mosi_i | 99 | PC3 | SPI1_MOSI | |
I2C_O_SDA | cs_n | 79 | PB9 | SPI1_NSS | |
FPGA_IO_SPARE_0_1 | sclk_i | 136 | PB10 | SPI1_SCK | |
FPGA_IO_SPARE_2_0 | 49 | PA7 | |||
FPGA_IO_SPARE_2_1 | 48 | PA6 | |||
FPGA_IO_SPARE_2_2 | 47 | PA5 | |||
FPGA_IO_SPARE_2_3 | 45 | PA4 |