// Copyright 2023 The Pigweed Authors
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy of
// the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////////
module top (
    input  clk_i,
    input  rst_i,
    input  op_mode_i,
    output data_valid_o,
    output led,
    input ice_prog_spi_io0,
    input ice_prog_spi_io1,

    // spi secondary interface
    input  sl_sclk_i_0,
    input  sl_mosi_i_0,
    input  sl_cs_i_0,
    output sl_miso_o_0,
    // spi interfaces
    //
    input  miso_i_1,
    input  alertl_i_1,
    output sclk_o_1,
    output mosi_o_1,
    output cs_o_1,
    //
    input  miso_i_2,
    input  alertl_i_2,
    output sclk_o_2,
    output mosi_o_2,
    output cs_o_2,
    //
    input  miso_i_3,
    input  alertl_i_3,
    output sclk_o_3,
    output mosi_o_3,
    output cs_o_3,
    //
    input  miso_i_4,
    input  alertl_i_4,
    output sclk_o_4,
    output mosi_o_4,
    output cs_o_4,
    //
    input  miso_i_5,
    input  alertl_i_5,
    output sclk_o_5,
    output mosi_o_5,
    output cs_o_5,
    //
    input  miso_i_6,
    input  alertl_i_6,
    output sclk_o_6,
    output mosi_o_6,
    output cs_o_6,
    //
    input  miso_i_7,
    input  alertl_i_7,
    output sclk_o_7,
    output mosi_o_7,
    output cs_o_7,
    //
    input  miso_i_8,
    input  alertl_i_8,
    output sclk_o_8,
    output mosi_o_8,
    output cs_o_8,
    //
    input  miso_i_9,
    input  alertl_i_9,
    output sclk_o_9,
    output mosi_o_9,
    output cs_o_9,
    //
    input  miso_i_10,
    input  alertl_i_10,
    output sclk_o_10,
    output mosi_o_10,
    output cs_o_10,
    //
    input  miso_i_11,
    input  alertl_i_11,
    output sclk_o_11,
    output mosi_o_11,
    output cs_o_11
);

  wire rst_i_sync, poll_dn_w, mclk, en_w, r_w_en_w, mode_i_sync, trf_dn_w, dn_clr;
  wire [ 5:0] rwaddr_w;
  wire [10:0] adc_select_w;
  wire [11:0] poll_dn_bus_w;
  wire [15:0] wdata_w;
  wire [23:0] vbus_1,vshunt_1,vbus_2,vshunt_2 ,vbus_3 ,vshunt_3 ,vbus_4 ,vshunt_4 ,vbus_5 ,vshunt_5 ,vbus_6 ,vshunt_6 ;
  wire [23:0] vbus_7 ,vshunt_7,vbus_8 ,vshunt_8 ,vbus_9 ,vshunt_9 ,vbus_10 ,vshunt_10 ,vbus_11 ,vshunt_11;
  wire [39:0] rdata_w;

  //assign ice_prog_spi_io0 = 1'bz; assigned as input. same as output hi-z.
  //assign ice_prog_spi_io1 = 1'bz;

  pll pll_inst (
      .clock_in (clk_i),
      .clock_out(mclk)
  );

  assign led = count[25];
  reg [25:0] count;
  initial count = 0;
  always @(posedge mclk) begin
    count <= count + 1;
  end

  spi_s_core spi_s_core_inst (
      .sclk_i(sl_sclk_i_0),
      .mosi_i(sl_mosi_i_0),
      .cs_i(sl_cs_i_0),
      .miso_o(sl_miso_o_0),
      //
      .mclk_i(mclk),
      .rst_i(rst_i_sync),
      .en_o(en_w),
      .rwaddr_o(rwaddr_w),
      .adc_sel_o(adc_select_w),
      .wdata_o(wdata_w),
      .r_w_en_o(r_w_en_w),
      .data_valid_o(data_valid_o),
      .mode_i(mode_i_sync),
      .rdata_i(rdata_w),
      .poll_dn_i(poll_dn_w),
      .dn_i(trf_dn_w),
      .dn_clr_o(dn_clr),
      .vbus_1(vbus_1),
      .vshunt_1(vshunt_1),
      .vbus_2(vbus_2),
      .vshunt_2(vshunt_2),
      .vbus_3(vbus_3),
      .vshunt_3(vshunt_3),
      .vbus_4(vbus_4),
      .vshunt_4(vshunt_4),
      .vbus_5(vbus_5),
      .vshunt_5(vshunt_5),
      .vbus_6(vbus_6),
      .vshunt_6(vshunt_6),
      .vbus_7(vbus_7),
      .vshunt_7(vshunt_7),
      .vbus_8(vbus_8),
      .vshunt_8(vshunt_8),
      .vbus_9(vbus_9),
      .vshunt_9(vshunt_9),
      .vbus_10(vbus_10),
      .vshunt_10(vshunt_10),
      .vbus_11(vbus_11),
      .vshunt_11(vshunt_11)
  );
  //
  // .vbus_1(1),// vbus_1),
  // .vshunt_1(2),
  // .vbus_2(3),
  // .vshunt_2(4),
  // .vbus_3(5),
  // .vshunt_3(6),
  // .vbus_4(7),
  // .vshunt_4(8),
  // .vbus_5(9),
  // .vshunt_5(10),
  // .vbus_6(11),
  // .vshunt_6(12),
  // .vbus_7(13),
  // .vshunt_7(14),
  // .vbus_8(15),
  // .vshunt_8(16),
  // .vbus_9(17),
  // .vshunt_9(19),
  // .vbus_10(20),
  // .vshunt_10(21),
  // .vbus_11(22),
  // .vshunt_11(23));


  rst_sync rst_sync_inst (
      .clk_i(mclk),
      .rst_i(rst_i),
      .rst_o(rst_i_sync)
  );

  sig_sync op_mode_sync (
      .clk_i(mclk),
      .rst_i(rst_i_sync),
      .sig_i(op_mode_i),
      .sig_o(mode_i_sync)
  );

  csa_ctl_top csa_ctl_top_inst (
      .mclk_i(mclk),
      .rst_i(rst_i_sync),
      .r_w_en_i(r_w_en_w),
      .en_i(en_w),
      .mode_i(mode_i_sync),
      .rwaddr_i(rwaddr_w),
      .adc_sel_i(adc_select_w),
      .wdata_i(wdata_w),
      .dn_o(trf_dn_w),
      .rdata_o(rdata_w),
      //
      .dn_clr_i(dn_clr),  // Use to clear data-valid. Short to trf_dn_o of spi core.
      .poll_dn_o(poll_dn_w),
      // .poll_dn(),// NC. Only for bringup
      // spi
      .miso_i_1(miso_i_1),
      .alertl_i_1(alertl_i_1),
      .sclk_o_1(sclk_o_1),
      .mosi_o_1(mosi_o_1),
      .cs_o_1(cs_o_1),
      .miso_i_2(miso_i_2),
      .alertl_i_2(alertl_i_2),
      .sclk_o_2(sclk_o_2),
      .mosi_o_2(mosi_o_2),
      .cs_o_2(cs_o_2),
      .miso_i_3(miso_i_3),
      .alertl_i_3(alertl_i_3),
      .sclk_o_3(sclk_o_3),
      .mosi_o_3(mosi_o_3),
      .cs_o_3(cs_o_3),
      .miso_i_4(miso_i_4),
      .alertl_i_4(alertl_i_4),
      .sclk_o_4(sclk_o_4),
      .mosi_o_4(mosi_o_4),
      .cs_o_4(cs_o_4),
      .miso_i_5(miso_i_5),
      .alertl_i_5(alertl_i_5),
      .sclk_o_5(sclk_o_5),
      .mosi_o_5(mosi_o_5),
      .cs_o_5(cs_o_5),
      .miso_i_6(miso_i_6),
      .alertl_i_6(alertl_i_6),
      .sclk_o_6(sclk_o_6),
      .mosi_o_6(mosi_o_6),
      .cs_o_6(cs_o_6),
      .miso_i_7(miso_i_7),
      .alertl_i_7(alertl_i_7),
      .sclk_o_7(sclk_o_7),
      .mosi_o_7(mosi_o_7),
      .cs_o_7(cs_o_7),
      .miso_i_8(miso_i_8),
      .alertl_i_8(alertl_i_8),
      .sclk_o_8(sclk_o_8),
      .mosi_o_8(mosi_o_8),
      .cs_o_8(cs_o_8),
      .miso_i_9(miso_i_9),
      .alertl_i_9(alertl_i_9),
      .sclk_o_9(sclk_o_9),
      .mosi_o_9(mosi_o_9),
      .cs_o_9(cs_o_9),
      .miso_i_10(miso_i_10),
      .alertl_i_10(alertl_i_10),
      .sclk_o_10(sclk_o_10),
      .mosi_o_10(mosi_o_10),
      .cs_o_10(cs_o_10),
      .miso_i_11(miso_i_11),
      .alertl_i_11(alertl_i_11),
      .sclk_o_11(sclk_o_11),
      .mosi_o_11(mosi_o_11),
      .cs_o_11(cs_o_11),
      //
      .vbus_1(vbus_1),
      .vshunt_1(vshunt_1),
      .vbus_2(vbus_2),
      .vshunt_2(vshunt_2),
      .vbus_3(vbus_3),
      .vshunt_3(vshunt_3),
      .vbus_4(vbus_4),
      .vshunt_4(vshunt_4),
      .vbus_5(vbus_5),
      .vshunt_5(vshunt_5),
      .vbus_6(vbus_6),
      .vshunt_6(vshunt_6),
      .vbus_7(vbus_7),
      .vshunt_7(vshunt_7),
      .vbus_8(vbus_8),
      .vshunt_8(vshunt_8),
      .vbus_9(vbus_9),
      .vshunt_9(vshunt_9),
      .vbus_10(vbus_10),
      .vshunt_10(vshunt_10),
      .vbus_11(vbus_11),
      .vshunt_11(vshunt_11)
  );

endmodule