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{
  "log": [
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      "author": {
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        "email": "jinfeiaden@gmail.com",
        "time": "Wed Sep 09 07:15:33 2026 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Sep 09 10:45:33 2026 +0530"
      },
      "message": "Add initial AURIX TC3xx GCC port (#33)\n\nSigned-off-by: ruka77S \u003cjinfeiaden@gmail.com\u003e"
    },
    {
      "commit": "fccbbce9bd7e227ee211b01fdbbcf133dc3a474a",
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      "parents": [
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      "author": {
        "name": "Ian Thompson",
        "email": "101299961+ianstcdns@users.noreply.github.com",
        "time": "Tue Aug 18 08:45:32 2026 -0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Tue Aug 18 08:45:32 2026 -0700"
      },
      "message": "Cadence/Xtensa: Enabling XT_USE_L2RAM overrides PRIVILEGED_DATA (#32)\n\n- Removed portMOVE_PRIVILEGED_DATA config option after updates to mpu_wrappers.h\n- Improvement suggested via FreeRTOS-Kernel PR #1433\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e"
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    {
      "commit": "a5b5d9b7f524f931dedb85a7b2992891dc6c2d07",
      "tree": "b3e4b1f240343935b8e9ff394f610e3e20debe43",
      "parents": [
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      "author": {
        "name": "Ian Thompson",
        "email": "101299961+ianstcdns@users.noreply.github.com",
        "time": "Thu Jun 18 15:32:35 2026 -0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Thu Jun 18 15:32:35 2026 -0700"
      },
      "message": "Xtensa Port v3.13 Updates (#31)\n\n* Cadence/Xtensa: NX bug-fixes for imprecise exception handling\n\n- Update NX init logic to check whether a software interrupt is\n  already registered before provisioning it for the scheduler.\n- Add new xt_get_interrupt_handler() API to enable above fix.\n- Fix exception dispatch assembly code to correctly provide the\n  exception stack frame to imprecise exception handlers (NX only).\n- Confirm functionality on windowed/call0 configs with and without\n  FreeRTOS MPU support.\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: SMP support for Xtensa FreeRTOS\n\n- Merge pull request #2 from IPG-TIP-Xtensa/dev-xtensa-smp\n- Cadence/Xtensa: Add an assertion for SMP init ordering.\n- Cadence/Xtensa: Require RJ.5 tools\n- Cadence/Xtensa: SMP fixes to enable multicore Palladium\n- Cadence/Xtensa: Update coproc handling for SMP\n- Cadence/Xtensa: Limit outstanding CacheOps coming from L2\n- Cadence/Xtensa: Update release notes for 3.10 release\n- Remove DRAM requirement\n- Call main() only for core 0\n- Replicate/consolidate per-core intr/coproc data\n- Separate initial stacks per-core\n- Additional fixes and clean-up\n- Update release notes for 3.11 release\n- FreeRTOS/SMP: CP save bug-fix\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: SMP: Increase core 0 startup stack size\n\n- Extra space required for main() to call printf()\n  without overflowing when argv[0] has a long path\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Enable context switch hooks for SMP builds\n\n- Enables xt_smp example to more accurately profile time\n  taken in single vs. multicore test.\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Add multcore clib support to SMP port\n\n- Add per-core xclib reentrancy struct instances\n- Redefine reentrant pointer to __getreent() function via\n  defining __DYNAMIC_REENT__ in xclib\n- Improve build infra to properly support overriding\n  CFLAGS in nightly tests\n- Bump port rev to 3.12\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Coprocessor handling fixes for SMP configs\n\n- Clear coproc owner thread when saving callee-saved state\n- Fix coproc init/release functions\n- Update readme and release notes\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Implement exclusive store locks for SMP\n\n- Removes dependency on XTOS locks\n- Clarify v3.12 release notes\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Clarify v3.12 SMP requirements\n\n- xclib is required for 3.12\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Patch xtsubsystem.h\n\n- Resolve a couple of errors in \u003cxtensa/xtsubsystem.h\u003e\n  when compiled with RJ.5 Xtensa toolchain and C++17.\n- Will no longer be necessary with RJ.6.\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Clear LCOUNT on ISR entry, new task creation\n\n- LCOUNT needs to be cleared during solicited context switch, ISR entry\n- Prevents incorrect zero-overhead execution\n- Extra conditional logic required for overlay save/restore\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Merge Xtensa v3.13 port into xtensa-dev\n\nNotes for Version 3.13\n----------------------\n- FreeRTOS SMP support for newlib (experimental).\n- FreeRTOS SMP context switching performance improvements.\n- FreeRTOS SMP config option \"XT_USE_L2RAM\" moves data into L2RAM\n  for context switching performance improvements.  Disabled by default.\n- FreeRTOS SMP config option \"XT_USE_DATARAM\" moves per-core data into\n  dataram for performance improvements.  Disabled by default.\n- Based on FreeRTOS-Kernel V11.2.0 release in 3/2025.\n- Numerous fixes and improvements.\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Correct SMP patch include\n\n- Subsystem patch only required for RJ.5 tool-chain;\n  do not apply for builds with earlier tools.\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Add support for idma-os library\n\n- Single-core multithreaded iDMA support\n- SMP iDMA support with pinned tasks\n- Example test and build infrastructure\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Fix race condition in idma-os module\n\n- NX configs were reallocating a channel before it was fully cleaned up\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n* Cadence/Xtensa: Update release notes and readme\n\n- Xtensa port v3.13 tested and working with FreeRTOS-Kernel version 11.3.0.\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\n\n---------\n\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e"
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        "email": "jinfeiaden@gmail.com",
        "time": "Fri Jun 12 19:45:26 2026 +0200"
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        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Fri Jun 12 10:45:26 2026 -0700"
      },
      "message": "add aurix tc4xx tricore-gcc port (#30)\n\n* Add initial tc4xx GCC port files\n\n* add the license file\n\n* Fix: an non-critical inline assembly syntax fix\n\n* add a readme to note about the triocore-gcc compiler\n\n* Fix TC4xx GCC CSA inline asm output constraint\n\n* Fix TC4xx GCC portmacro include path\n\n* Fix TC4xx GCC portmacro header guards\n\n* Document TC4xx GCC syscall trap integration\n\n* Updated the LICENSE copyright line\n\n* Document TC4xx GCC port integration options\n\n* Fix TC4xx GCC port function prototypes"
    },
    {
      "commit": "48534e1afa536a965a5db6e75ef1a1fa327ea32f",
      "tree": "766ae7b8e8e1555c27914022a2347bbd5d3925c0",
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        "email": "147012384+TrongNguyenR@users.noreply.github.com",
        "time": "Mon Nov 17 12:38:15 2025 +0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Nov 17 11:08:15 2025 +0530"
      },
      "message": "Supported new feature Interrupt Stack Management for U2x Port. (#28)\n\n* Add new port layer for CCRH U2x and GHS U2x\n\n* Updated U2x port to support U2Cx devices.\n\n* Due to internal constraint, we need to postpone the upstream. We will resume once it will be ready.\n\n* Update RH850 U2x resource references.\n\n* Due to internal constraint, we need to postpone the upstream. We will resume once it will be ready.\n\n* Update RH850 U2x resource references.\n\n* Updated U2x port to support U2Cx devices.\n\n* Due to internal constraint, we need to postpone the upstream. We will resume once it will be ready.\n\n* Update RH850 U2x resource references\n\n* Update RH850 U2x resource references\n\n* updated U2x FreeRTOS port to support Stack Interrupt Management.\n\n* updated U2x FreeRTOS port to support Stack Interrupt Management.\n\n* 1. Supported new feature Interrupt Stack Management.\n2. Improved the usage of FXU/FPU.\n3. Improved the content in README.md.\n\n---------\n\nCo-authored-by: Duc Dat Le \u003cduc.le.xm@renesas.com\u003e\nCo-authored-by: vung.tran.zg \u003cvung.tran.zg@renesas.com\u003e"
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    {
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        "email": "147012384+TrongNguyenR@users.noreply.github.com",
        "time": "Mon Sep 22 12:46:04 2025 +0700"
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      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Sep 22 11:16:04 2025 +0530"
      },
      "message": "Update RH850 U2x resource references (#26)\n\n* Add new port layer for CCRH U2x and GHS U2x\n\n* Updated U2x port to support U2Cx devices.\n\n* Due to internal constraint, we need to postpone the upstream. We will resume once it will be ready.\n\n* Update RH850 U2x resource references.\n\n* Due to internal constraint, we need to postpone the upstream. We will resume once it will be ready.\n\n* Update RH850 U2x resource references.\n\n* Updated U2x port to support U2Cx devices.\n\n* Due to internal constraint, we need to postpone the upstream. We will resume once it will be ready.\n\n* Update RH850 U2x resource references\n\n* Update RH850 U2x resource references\n\n---------\n\nCo-authored-by: Duc Dat Le \u003cduc.le.xm@renesas.com\u003e\nCo-authored-by: vung.tran.zg \u003cvung.tran.zg@renesas.com\u003e"
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    {
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      "parents": [
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      "author": {
        "name": "Trong Nguyen",
        "email": "147012384+TrongNguyenR@users.noreply.github.com",
        "time": "Wed Sep 17 12:34:41 2025 +0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Sep 17 11:04:41 2025 +0530"
      },
      "message": "Update port files for CCRH and GHS to support Renesas RH850 U2Cx devices. (#25)\n\n* Add new port layer for CCRH U2x and GHS U2x\n\n* Updated U2x port to support U2Cx devices.\n\n---------\n\nCo-authored-by: Duc Dat Le \u003cduc.le.xm@renesas.com\u003e\nCo-authored-by: vung.tran.zg \u003cvung.tran.zg@renesas.com\u003e"
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      "parents": [
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        "name": "Arnav Menon",
        "email": "63289642+arnavmenon@users.noreply.github.com",
        "time": "Wed Jul 02 12:18:54 2025 +0530"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Jul 02 12:18:54 2025 +0530"
      },
      "message": "Add C29x port for TI F29H85x device (#23)\n\n* Add C29x port for TI F29H85x device\n\n* Update macros \u0026 add error check in C29x port"
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    {
      "commit": "48407cc4498f83fd18d5c4cfc63df622979c54a5",
      "tree": "136823041360a4041095c21b28a27a6f91f63cb8",
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        "name": "Austin Foxley",
        "email": "59938516+afoxley@users.noreply.github.com",
        "time": "Mon Mar 31 08:26:37 2025 -0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Mar 31 20:56:37 2025 +0530"
      },
      "message": "xtensa: Implement xPortIsInsideInterrupt (#21)\n\nImplement support for this optional port API which provides a portable\nway to check if the current executing code is within an interrupt."
    },
    {
      "commit": "97a8f46383caa99a1d15b09b33a9db9c9641807b",
      "tree": "2270e6e84edfefc307fa6a9e1dd10879fb01d454",
      "parents": [
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        "name": "Anubhav Rawal",
        "email": "rawalexe@amazon.com",
        "time": "Tue Jan 07 21:45:11 2025 -0800"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Wed Jan 08 11:15:11 2025 +0530"
      },
      "message": "Add LICENSE file to the directory (#20)\n\n"
    },
    {
      "commit": "1afa57e5c56fd9e00d64333e3541d35b681accef",
      "tree": "a3536601852f6b501c0d1a303cbe884b435bb10a",
      "parents": [
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        "name": "Felix van Oost",
        "email": "felix.vanoost@live.com",
        "time": "Mon Dec 30 04:41:18 2024 -0500"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Dec 30 15:11:18 2024 +0530"
      },
      "message": "Pass core ID to port lock macros (#19)\n\nPass core ID to port task/ISR lock macros."
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    {
      "commit": "5576599177560751911ba4cc4d67ec8ddec7c0f7",
      "tree": "f277a0c40027400a459812067a2cf4c32f9c2040",
      "parents": [
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      "author": {
        "name": "Austin Foxley",
        "email": "59938516+afoxley@users.noreply.github.com",
        "time": "Mon Dec 02 22:04:21 2024 -0800"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Tue Dec 03 11:34:21 2024 +0530"
      },
      "message": "Specify license for Xtensa port (#17)\n\n"
    },
    {
      "commit": "840e3a47254c9f58790d133ae1647c142f74ebdf",
      "tree": "8e06d0287365a81535e569c89259c00aaa77d021",
      "parents": [
        "abc22103e1e6634b33457d4127bff1ab62f27f90"
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      "author": {
        "name": "Trong Nguyen",
        "email": "147012384+TrongNguyenR@users.noreply.github.com",
        "time": "Mon Nov 25 12:35:15 2024 +0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Nov 25 13:35:15 2024 +0800"
      },
      "message": "Add new port layer for CCRH U2x and GHS U2x (#16)\n\nCo-authored-by: Duc Dat Le \u003cduc.le.xm@renesas.com\u003e"
    },
    {
      "commit": "abc22103e1e6634b33457d4127bff1ab62f27f90",
      "tree": "9eb8d5efa2ec622ab94e878180354b0bb893dad1",
      "parents": [
        "dc3afc6e837426b4bda81bbb6cf45bfb6f34c7e9"
      ],
      "author": {
        "name": "Ian Thompson",
        "email": "101299961+ianstcdns@users.noreply.github.com",
        "time": "Mon Oct 14 14:56:15 2024 -0700"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Mon Oct 14 14:56:15 2024 -0700"
      },
      "message": "Update Xtensa FreeRTOS support to v11 (#15)\n\n* Cadence/Xtensa: Initial port from v10.4.4-stable\r\n\r\n- Import from https://github.com/foss-xtensa/amazon-freertos\r\n- Various updates to enable build and passing first round of tests\r\n\r\n* Cadence/Xtensa: kernel builds, demos passing\r\n\r\nUpdate Xtensa port to version 3.00\r\n\r\n* Incorporate Xtensa fixes from ThirdParty/XCC/Xtensa\r\n\r\nWarning fixes. (FreeRTOS#356)\r\nb5a9229563cff507dc34bff55ffeeffcb0ca8d2e\r\n\r\nEnable use of --text-section-literals in Xtensa port (#485)\r\nb00250372eed15192a76186def3f275f7ca42020\r\n\r\nAdded better pointer declaration readability (#567)\r\n24ade42a37849f8ad05b9ced2a0c967ae5f79d1f\r\n\r\nAdded support of 64bit events. (#597)\r\n91c20f5f425b18b641765217586a82a62e1aa45a\r\n\r\ntree-wide: Unify formatting of __cplusplus ifdefs\r\nc1980cedb110e3826fbf22d93fccaa2ca3d9daf8\r\n\r\n* Copyright and whitespace updates\r\n\r\nPulled formatting changes from ThirdParty/XCC/Xtensa\r\nNo functional changes\r\n\r\n* Minor fixes to example build\r\n\r\nFix incorrect readme path\r\nFix directory separators on windows\r\n\r\nCommand-line test suite passing\r\n\r\n* Fix build error\r\n\r\nRemove newlib reent pointer reference\r\n\r\n* Fix warnings and whitespace issues\r\n\r\nIncorporate recent fixes from legacy Xtensa repo\r\n\r\n* Cadence/Xtensa: Fix bug in tickless idle implementation\r\n\r\nCritical section nesting counter was not being incremented/decremented during vPortSuppressTicksAndSleeep() so the call to vTaskStepTick() might reenable interrupts and cause a spurious timer expiry.\r\n\r\n* Cadence/Xtensa: fix to handle wider range of timer ISRs\r\n\r\n- Signed comparison is more flexible for tickless idle / variable frequency support\r\n\r\n* Cadence/Xtensa: newlib fixes\r\n\r\n- Provide clib/newlib DEINIT function for reentrancy structure to prevent closing of stdin/stdout/stderr on TLS cleanup in task exit.\r\n\r\n* Cadence/Xtensa: Update overlay build flags\r\n\r\nIncrease debugging visibility with -Os; enable thread-safe CLIB support\r\n\r\n* Cadence/Xtensa: Fix overlay race condition\r\n\r\n- Context switch during overlay use could result in overlay scratch register corruption\r\n- Highly recommend RJ-2024.4 tools or later, which also contains a fix to liboverlay.a\r\n\r\n* Cadence/Xtensa: Makefile update to simplify custom config params\r\n\r\n- Allow config parameters to be passed through Makefile chain as CFGFLAGS\r\n\r\n* Cadence/Xtensa: fix incorrect ifdefs\r\n\r\n- Check for windowed ABI, not whether HW supports windowing\r\n\r\n* Cadence/Xtensa: Release coprocessor ownership on task deletion\r\n\r\n- Resolve issue where it is possible for a task to exit\r\nwhile owning one or more coprocessors, and the\r\nownership is not given up properly.\r\n\r\n* Cadence/Xtensa: Merge NX + MPU support\r\n\r\n- Add privilege syscall handling for XEA3\r\n- Add MPU region restore for windowed/call0 configs\r\n- Separate privileged and user-mode task init for NX\r\n- Optimize privilege syscall handler to skip tail-chain and MPU restore\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n* Cadence/Xtensa: Simplify syscall handling for windowed NX\r\n\r\n- Save and restore a2 for syscall arg/return\r\n- Add an extra 4 bytes to Exception frame struct\r\n- Avoid rotw since it may not handle underflow condition\r\n- Clean up comments and XT_STK_XTRA_SZ logic\r\n- MPU restore logic cannot be easily skipped at this time\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n* Cadence/Xtensa: Restrict overlay build to windowd ABI configs\r\n\r\n- Overlay support requires Windowed ABI; won\u0027t work with call0\r\n- Update README as well\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n* Cadence/Xtensa: Remove unused code\r\n\r\n- _xt_idle is legacy code and is unreferenced.\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n* Cadence/Xtensa: Limit overlay builds to LX\r\n\r\n- Generate error earlier for overlay build attempt on NX\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n* Cadence/Xtensa: Fix timer selection logic\r\n\r\n- XCHAL_INT_LEVEL() macro requires interrupt number, not timer ID\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n* Cadence/Xtensa: Prepare for Upstreaming\r\n\r\n- Relocate example test code according to suggested naming conventions\r\n- Modularize build for multiple configs--optionally reroute output\r\n- Update port README\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n* Cadence/Xtensa: Minor cleanup\r\n\r\n- No functional changes\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n* Cadence/Xtensa: Add portMEMORY_BARRIER() macro\r\n\r\n- Cherry picked from FreeRTOS-Kernel commit #190906ae\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e\r\n\r\n---------\r\n\r\nSigned-off-by: Ian Thompson \u003cianst@cadence.com\u003e"
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