)]}'
{
  "commit": "0037a6c574f43937d181d4d47fdc2bdd562bbcc3",
  "tree": "4561d5a5882a6656c878a9bc5f15bed9ed699490",
  "parents": [
    "524e78d58b6ee60f74e9b7028f266c5722bf4c24"
  ],
  "author": {
    "name": "Emmanuel Puerto",
    "email": "50575011+e-puerto@users.noreply.github.com",
    "time": "Wed Sep 09 20:06:16 2020 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Sep 09 11:06:16 2020 -0700"
  },
  "message": "RISC-V: Add RV32E / FPU support for GCC (#140)\n\n* Change vPortSetupTimerInterrupt in order to have 64bits access on rv64\r\n\r\n* Support RV32E - RISC-V architecture (GCC)\r\n\r\nSigned-off-by: Emmanuel Puerto \u003cemmanuel.puerto@sifive.com\u003e\r\n\r\n* Support FPU - RISC-V architecture (GCC)\r\n\r\nSigned-off-by: Emmanuel Puerto \u003cemmanuel.puerto@sifive.com\u003e\r\n\r\n* Fix interrupt managment and FPU initialization",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ac3f6dbe2e80e91fb2c773eb144c54cbb640614a",
      "old_mode": 33188,
      "old_path": "portable/GCC/RISC-V/port.c",
      "new_id": "a0acdf4c8e16bbf44cc0f36566654f94b85312db",
      "new_mode": 33188,
      "new_path": "portable/GCC/RISC-V/port.c"
    },
    {
      "type": "modify",
      "old_id": "7f9c48476298fe912f2b754e36caf3270db75b8f",
      "old_mode": 33188,
      "old_path": "portable/GCC/RISC-V/portASM.S",
      "new_id": "4a6192130bd76585d8a0f3a29d5d7b22d1730e73",
      "new_mode": 33188,
      "new_path": "portable/GCC/RISC-V/portASM.S"
    }
  ]
}