tree 4561d5a5882a6656c878a9bc5f15bed9ed699490
parent 524e78d58b6ee60f74e9b7028f266c5722bf4c24
author Emmanuel Puerto <50575011+e-puerto@users.noreply.github.com> 1599674776 +0200
committer GitHub <noreply@github.com> 1599674776 -0700
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RISC-V: Add RV32E / FPU support for GCC (#140)

* Change vPortSetupTimerInterrupt in order to have 64bits access on rv64

* Support RV32E - RISC-V architecture (GCC)

Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>

* Support FPU - RISC-V architecture (GCC)

Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>

* Fix interrupt managment and FPU initialization