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 * Copyright 2013 Altera Corporation. All Rights Reserved.
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 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
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/*!
 * \file
 *
 * Contains the definition of an opaque data structure that contains raw
 * configuration information for a clock group.
 */

#ifndef __ALT_CLK_GRP_H__
#define __ALT_CLK_GRP_H__

#include "hwlib.h"
#include "socal/alt_clkmgr.h"

#ifdef __cplusplus
extern "C"
{
#endif  /* __cplusplus */

/*!
 * This type definition enumerates the clock groups
 */
typedef enum ALT_CLK_GRP_e
{
    ALT_MAIN_PLL_CLK_GRP,        /*!< Main PLL clock group */

    ALT_PERIPH_PLL_CLK_GRP,      /*!< Peripheral PLL clock group */

    ALT_SDRAM_PLL_CLK_GRP        /*!< SDRAM PLL clock group */

} ALT_CLK_GRP_t;

/*!
 * This type definition defines an opaque data structure for holding the
 * configuration settings for a complete clock group.
 */
typedef struct ALT_CLK_GROUP_RAW_CFG_s
{
    uint32_t      verid;     /*!< SoC FPGA version identifier. This field
                              *   encapsulates the silicon identifier and
                              *   version information associated with this
                              *   clock group configuration. It is used to
                              *   assert that this clock group configuration
                              *   is valid for this device. */

    uint32_t      siliid2;   /*!< Reserved register - reserved for future
                              *   device IDs or capability flags. */

    ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */

    /*!
     * This union holds the register values for configuration of the set of
     * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
     * identifies the valid clock group union data member.
     */
    union ALT_CLK_GROUP_RAW_CFG_u
    {
        /*! Clock group configuration for Main PLL group. */
        union
        {
            ALT_CLKMGR_MAINPLL_t     fld; /*!< Field access. */
            ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */
        } mainpllgrp;

        /*! Clock group configuration for Peripheral PLL group. */
        union
        {
            ALT_CLKMGR_PERPLL_t     fld; /*!< Field access. */
            ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */
        } perpllgrp;

        /*! Clock group configuration for SDRAM PLL group. */
        union
        {
            ALT_CLKMGR_SDRPLL_t     fld; /*!< Field access. */
            ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */
        } sdrpllgrp;

    } clkgrp;
} ALT_CLK_GROUP_RAW_CFG_t;

#ifdef __cplusplus
}
#endif  /* __cplusplus */
#endif  /* __ALT_CLK_GRP_H__ */