/* ---------------------------------------------------------------------------- */
/*                  Atmel Microcontroller Software Support                      */
/*                       SAM Software Package License                           */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) 2014, Atmel Corporation                                        */
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/* All rights reserved.                                                         */
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/* modification, are permitted provided that the following condition is met:    */
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/* this list of conditions and the disclaimer below.                            */
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/* this software without specific prior written permission.                     */
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/* ---------------------------------------------------------------------------- */

#ifndef _SAM_SSC_INSTANCE_
#define _SAM_SSC_INSTANCE_

/* ========== Register definition for SSC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  #define REG_SSC_CR                       (0x40004000U) /**< \brief (SSC) Control Register */
  #define REG_SSC_CMR                      (0x40004004U) /**< \brief (SSC) Clock Mode Register */
  #define REG_SSC_RCMR                     (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
  #define REG_SSC_RFMR                     (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
  #define REG_SSC_TCMR                     (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
  #define REG_SSC_TFMR                     (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
  #define REG_SSC_RHR                      (0x40004020U) /**< \brief (SSC) Receive Holding Register */
  #define REG_SSC_THR                      (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
  #define REG_SSC_RSHR                     (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
  #define REG_SSC_TSHR                     (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
  #define REG_SSC_RC0R                     (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
  #define REG_SSC_RC1R                     (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
  #define REG_SSC_SR                       (0x40004040U) /**< \brief (SSC) Status Register */
  #define REG_SSC_IER                      (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
  #define REG_SSC_IDR                      (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
  #define REG_SSC_IMR                      (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
  #define REG_SSC_WPMR                     (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
  #define REG_SSC_WPSR                     (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
  #define REG_SSC_VERSION                  (0x400040FCU) /**< \brief (SSC) Version Register */
#else
  #define REG_SSC_CR      (*(__O  uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */
  #define REG_SSC_CMR     (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
  #define REG_SSC_RCMR    (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
  #define REG_SSC_RFMR    (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
  #define REG_SSC_TCMR    (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
  #define REG_SSC_TFMR    (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
  #define REG_SSC_RHR     (*(__I  uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
  #define REG_SSC_THR     (*(__O  uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
  #define REG_SSC_RSHR    (*(__I  uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
  #define REG_SSC_TSHR    (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
  #define REG_SSC_RC0R    (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
  #define REG_SSC_RC1R    (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
  #define REG_SSC_SR      (*(__I  uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */
  #define REG_SSC_IER     (*(__O  uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
  #define REG_SSC_IDR     (*(__O  uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
  #define REG_SSC_IMR     (*(__I  uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
  #define REG_SSC_WPMR    (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
  #define REG_SSC_WPSR    (*(__I  uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
  #define REG_SSC_VERSION (*(__I  uint32_t*)0x400040FCU) /**< \brief (SSC) Version Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#endif /* _SAM_SSC_INSTANCE_ */