/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
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* of this software and associated documentation files (the "Software"), to deal
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
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******************************************************************************/
/******************************************************************************
*
* microblaze_flush_cache_ext()
*
* Flush the entire L2 Cache
*
*
*******************************************************************************/

#include "xparameters.h"

#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN	16

	.text
	.globl	microblaze_flush_cache_ext
	.ent	microblaze_flush_cache_ext
	.align	2

microblaze_flush_cache_ext:

#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
	addik	r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))

	addik	r6, r0, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
	andi	r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)

Loop_start:
	wdc.ext.flush r5, r6
	bgtid	r6,Loop_start
	addik	r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
#endif
	rtsd	r15, 8
	nop
	.end	microblaze_flush_cache_ext