/******************************************************************************
*
* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
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* of this software and associated documentation files (the "Software"), to deal
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* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
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******************************************************************************/
/******************************************************************************
*
* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len)
*
*Flush a L2 Cache range
*
*Parameters:
*	'cacheaddr' - address in the L2 cache where the flush begins
*	'len    '   - length (in bytes) worth of L2 cache to be flushed
*
*******************************************************************************/

#include "xparameters.h"

#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN	16

	.text
	.globl	microblaze_flush_cache_ext_range
	.ent	microblaze_flush_cache_ext_range
	.align	2

microblaze_flush_cache_ext_range:
#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
	beqi	r6, Loop_done

	addik	r6, r6, -1
	add	r6, r5, r6

	andi	r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
	andi	r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)

	rsubk	r6, r5, r6
Loop_start:
	wdc.ext.flush r5, r6
	bneid	r6, Loop_start
	addik	r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)

Loop_done:
#endif
	rtsd	r15, 8
	nop

	.end	microblaze_flush_cache_ext_range