)]}'
{
  "commit": "2dfdfc4ba4d8bb487c8ea6b5428d7d742ce162b8",
  "tree": "d42ed3f0cb697ade597aca63a1ffd9c0725ab75c",
  "parents": [
    "8e89acfc98909923476849a2493c5fa576ff0094"
  ],
  "author": {
    "name": "Paul Bartell",
    "email": "pbartell@amazon.com",
    "time": "Wed Jun 29 22:05:26 2022 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Jun 30 10:35:26 2022 +0530"
  },
  "message": "Add Cortex M7 r0p1 Errata 837070 workaround to CM4_MPU ports (#513)\n\n* Clarify Cortex M7 r0p1 errata number in r0p1 specific port.\r\n\r\n* Add ARM Cortex M7 r0p0 / r0p1 Errata 837070 workaround to CM4 MPU ports.\r\n\r\nOptionally, enable the errata workaround by defining configTARGET_ARM_CM7_r0p0 or configTARGET_ARM_CM7_r0p1 in FreeRTOSConfig.h.\r\n\r\n* Add r0p1 errata support to IAR port as well\r\n\r\nSigned-off-by: Gaurav Aggarwal \u003caggarg@amazon.com\u003e\r\n\r\n* Change macro name to configENABLE_ERRATA_837070_WORKAROUND\r\n\r\nSigned-off-by: Gaurav Aggarwal \u003caggarg@amazon.com\u003e\r\n\r\nCo-authored-by: Gaurav Aggarwal \u003caggarg@amazon.com\u003e",
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