/*******************************************************************************
*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
*  //
*  // Permission is hereby granted, free of charge, to any person obtaining
*  // a copy of this software and associated documentation files (the
*  // "Software"), to deal in the Software without restriction, including
*  // without limitation the rights to use, copy, modify, merge, publish,
*  // distribute, sublicense, and/or sell copies of the Software, and to
*  // permit persons to whom the Software is furnished to do so, subject to
*  // the following conditions:
*  //
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*  // in all copies or substantial portions of the Software.
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*  --------------------------------------------------------------------------------
*
*       XTENSA INITIALIZATION ROUTINES CODED IN C
*
*  This file contains miscellaneous Xtensa RTOS-generic initialization functions
*  that are implemented in C.
*
*******************************************************************************/


#ifdef XT_BOARD
    #include    <xtensa/xtbsp.h>
#endif

#include    "xtensa_rtos.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include    "esp32s2/clk.h"
#elif CONFIG_IDF_TARGET_ESP32
#include    "esp32/clk.h"
#endif

#ifdef XT_RTOS_TIMER_INT

    unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */

    void _xt_tick_divisor_init( void )
    {
        _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
    }

/* Deprecated, to be removed */
    int xt_clock_freq( void )
    {
        return esp_clk_cpu_freq();
    }

#endif /* XT_RTOS_TIMER_INT */