)]}'
{
  "commit": "4e3bf0f5c0efecf731c4e562defdba8aa01c15cb",
  "tree": "fa8ffb2e1378f768da5e2c1ff992d4884d735a02",
  "parents": [
    "56428a9831775a202a21a00ddf9be84ddcc1c4e2"
  ],
  "author": {
    "name": "Gaurav-Aggarwal-AWS",
    "email": "33462878+aggarg@users.noreply.github.com",
    "time": "Tue Jun 22 18:51:58 2021 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Jun 22 18:51:58 2021 -0700"
  },
  "message": "Add Cortex-A53 port with system register interface for CPU interface access (#357)\n\nThe difference between this port and portable/GCC/ARM_CA53_64_BIT is\r\nthat this port uses System Register interface to access CPU interface\r\nwhile the other one uses Memory-mapped interface.\r\n\r\nSigned-off-by: Gaurav Aggarwal \r\nCo-authored-by: Cobus van Eeden \u003c35851496+cobusve@users.noreply.github.com\u003e",
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