diff --git a/Demo/MB91460_Softune/91467d_FreeRTOS.prj b/Demo/MB91460_Softune/91467d_FreeRTOS.prj
index e05a92c..4d9d63e 100644
--- a/Demo/MB91460_Softune/91467d_FreeRTOS.prj
+++ b/Demo/MB91460_Softune/91467d_FreeRTOS.prj
@@ -140,9 +140,10 @@
 F7-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdarg.h
 F7-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h
 F7-13=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\string.h
-F8=2 c 1 SRC\vectors.c
+F8=3 c 1 SRC\vectors.c
 F8-1=- SRC\mb91467d.h
 F8-2=- SRC\watchdog\watchdog.h
+F8-3=- SRC\FreeRTOSConfig.h
 F9=1 a 1 SRC\mb91467d.asm
 F9-1=- SRC\mb91467d.h
 F10=0 a 1 SRC\Start91460.asm
diff --git a/Demo/MB91460_Softune/91467d_FreeRTOS.wsp b/Demo/MB91460_Softune/91467d_FreeRTOS.wsp
index 512ab5b..0a0ae78 100644
--- a/Demo/MB91460_Softune/91467d_FreeRTOS.wsp
+++ b/Demo/MB91460_Softune/91467d_FreeRTOS.wsp
@@ -19,7 +19,5 @@
 
 [EditState]
 STATE-1=SRC\main.c:18
-STATE-2=..\..\Source\queue.c:988
-STATE-3=..\..\Source\tasks.c:1342
-Count=3
+Count=1
 
diff --git a/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h b/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
index af11cda..3eee30d 100644
--- a/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
+++ b/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
@@ -78,4 +78,6 @@
 #define INCLUDE_vTaskDelay				1
 #define INCLUDE_vResumeFromISR          1
 
+#define configKERNEL_INTERRUPT_PRIORITY 30
+
 #endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/MB91460_Softune/SRC/main.c b/Demo/MB91460_Softune/SRC/main.c
index 0128f0b..30bcb17 100644
--- a/Demo/MB91460_Softune/SRC/main.c
+++ b/Demo/MB91460_Softune/SRC/main.c
@@ -1,30 +1,72 @@
-/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
-/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
-/* ELIGIBILITY FOR ANY PURPOSES.											 */
-/*				 (C) Fujitsu Microelectronics Europe GmbH				  */
-/*------------------------------------------------------------------------
-  MAIN.C
-  - description
-  - See README.TXT for project description and disclaimer.
--------------------------------------------------------------------------*/
+/*
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with FreeRTOS.org; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+	A special exception to the GPL can be applied should you wish to distribute
+	a combined work that includes FreeRTOS.org, without being obliged to provide
+	the source code for any proprietary components.  See the licensing section
+	of http://www.FreeRTOS.org for full details of how and when the exception
+	can be applied.
+
+	***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
+	***************************************************************************
+*/
 
 
 /*
  * Creates all the demo application tasks, then starts the scheduler.  The WEB
  * documentation provides more details of the demo application tasks.
  * 
- * Main.c also creates a task called "Check".  This only executes every three 
- * seconds but has the highest priority so is guaranteed to get processor time.  
- * Its main function is to check that all the other tasks are still operational.
- * Each task (other than the "flash" tasks) maintains a unique count that is 
- * incremented each time the task successfully completes its function.  Should 
- * any error occur within such a task the count is permanently halted.  The 
- * check task inspects the count of each task to ensure it has changed since
- * the last time the check task executed.  If all the count variables have 
- * changed all the tasks are still executing error free, and the check task
- * toggles the onboard LED.  Should any task contain an error at any time 
+ * In addition to the standard demo tasks, the follow demo specific tasks are
+ * create:
+ *
+ * The "Check" task.  This only executes every three seconds but has the highest 
+ * priority so is guaranteed to get processor time.  Its main function is to 
+ * check that all the other tasks are still operational.  Most tasks maintain 
+ * a unique count that is incremented each time the task successfully completes 
+ * its function.  Should any error occur within such a task the count is 
+ * permanently halted.  The check task inspects the count of each task to ensure 
+ * it has changed since the last time the check task executed.  If all the count 
+ * variables have changed all the tasks are still executing error free, and the 
+ * check task toggles the onboard LED.  Should any task contain an error at any time 
  * the LED toggle rate will change from 3 seconds to 500ms.
  *
+ * The "Register Check" tasks.  These tasks fill the CPU registers with known
+ * values, then check that each register still contains the expected value 0 the
+ * discovery of an unexpected value being indicative of an error in the RTOS
+ * context switch mechanism.  The register check tasks operate at low priority
+ * so are switched in and out frequently.
+ *
+ * The "Trace Utility" task.  This can be used to obtain trace and debug 
+ * information via UART5.
  */
 
 
@@ -72,7 +114,7 @@
 top of the page.  When the system is operating error free the 'Check' task
 toggles an LED every three seconds.  If an error is discovered in any task the
 rate is increased to 500 milliseconds.  [in this case the '*' characters on the 
-LCD represent LED's]*/
+LCD represent LEDs]*/
 #define mainNO_ERROR_CHECK_DELAY		( ( portTickType ) 3000 / portTICK_RATE_MS  )
 #define mainERROR_CHECK_DELAY			( ( portTickType ) 500 / portTICK_RATE_MS  )
 
@@ -94,7 +136,7 @@
  * The function that implements the Check task.  See the comments at the head
  * of the page for implementation details.
  */ 
-static void vErrorChecks( void *pvParameters );
+static void prvErrorChecks( void *pvParameters );
 
 /*
  * Called by the Check task.  Returns pdPASS if all the other tasks are found
@@ -147,8 +189,9 @@
 	vCreateBlockTimeTasks();
 
 	/* Start the 'Check' task which is defined in this file. */
-	xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
+	xTaskCreate( prvErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
 
+	/* Start the 'Register Test' tasks as described at the top of this file. */
 	xTaskCreate( vFirstRegisterTestTask, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
 	xTaskCreate( vSecondRegisterTestTask, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
 
@@ -176,7 +219,7 @@
 }
 /*-----------------------------------------------------------*/
 
-static void vErrorChecks( void *pvParameters )
+static void prvErrorChecks( void *pvParameters )
 {
 portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime;
 
@@ -292,6 +335,8 @@
 		lReturn = pdFAIL;
 	}
 
+	/* Record the current values of the register check cycle counters so we
+	can ensure they are still running the next time this function is called. */
 	ulLastRegTest1Counter = ulRegTest1Counter;
 	ulLastRegTest2Counter = ulRegTest2Counter;
 
@@ -317,29 +362,29 @@
 }
 /*-----------------------------------------------------------*/
 
-/* The below callback function is called from Delayed ISR if configUSE_IDLE_HOOK 
-is configured as 1. */  
+/* Idle hook function. */
 #if configUSE_IDLE_HOOK == 1
 	void vApplicationIdleHook( void )
 	{
-		/* Are we using the idle task to kick the watchdog? */
+		/* Are we using the idle task to kick the watchdog?  See watchdog.h
+		for watchdog kicking options. Note this is for demonstration only
+		and is not a suggested method of servicing the watchdog in a real
+		application. */
 		#if WATCHDOG == WTC_IN_IDLE
 			Kick_Watchdog();
 		#endif
-
-		#if configUSE_CO_ROUTINES == 1		
-			vCoRoutineSchedule();
-		#endif
 	}
 #endif
 /*-----------------------------------------------------------*/
 
-/*
-The below callback function is called from Tick ISR if configUSE_TICK_HOOK 
-is configured as 1. */  
+/* Tick hook function. */
 #if configUSE_TICK_HOOK == 1
 	void vApplicationTickHook( void )
 	{
+		/* Are we using the tick to kick the watchdog?  See watchdog.h
+		for watchdog kicking options.  Note this is for demonstration
+		only and is not a suggested method of servicing the watchdog in
+		a real application. */
 		#if WATCHDOG == WTC_IN_TICK
 			Kick_Watchdog();
 		#endif
diff --git a/Demo/MB91460_Softune/SRC/serial/serial.c b/Demo/MB91460_Softune/SRC/serial/serial.c
index 090d799..2a9bc43 100644
--- a/Demo/MB91460_Softune/SRC/serial/serial.c
+++ b/Demo/MB91460_Softune/SRC/serial/serial.c
@@ -1,5 +1,5 @@
 /*
-	FreeRTOS.org V4.7.0 - Copyright (C) 2003-2007 Richard Barry.
+	FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
 
 	This file is part of the FreeRTOS.org distribution.
 
@@ -19,23 +19,30 @@
 
 	A special exception to the GPL can be applied should you wish to distribute
 	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
+	the source code for any proprietary components.  See the licensing section
 	of http://www.FreeRTOS.org for full details of how and when the exception
 	can be applied.
 
 	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
 
-	Also see http://www.SafeRTOS.com a version that has been certified for use
-	in safety critical systems, plus commercial licensing, development and
-	support options.
+	Please ensure to read the configuration and relevant port sections of the 
+	online documentation.
+
+	+++ http://www.FreeRTOS.org +++
+	Documentation, latest information, license and contact details.  
+
+	+++ http://www.SafeRTOS.com +++
+	A version that is certified for use in safety critical systems.
+
+	+++ http://www.OpenRTOS.com +++
+	Commercial support, development, porting, licensing and training services.
+
 	***************************************************************************
 */
 
 
-/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   
+/* 
+ * BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   
  * 
  * This file only supports UART 2
  */
@@ -63,8 +70,6 @@
 
 xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
 {
-//unsigned portLONG ulBaudRateCount;
-
 	portENTER_CRITICAL();
 	{
 		/* Create the queues used by the com test task. */
@@ -78,10 +83,10 @@
 		SMR02 = 0x0d;	/* enable SOT3, Reset, normal mode */
 		SSR02 = 0x02;	/* LSB first, enable receive interrupts */
 
-		PFR20_D0 = 1;	// enable UART
-		PFR20_D1 = 1;	// enable UART
+		PFR20_D0 = 1;	/* enable UART */
+		PFR20_D1 = 1;	/* enable UART */
 
-		EPFR20_D1 = 0;   // enable UART
+		EPFR20_D1 = 0;  /* enable UART */
 	}
 	portEXIT_CRITICAL();
 	
diff --git a/Demo/MB91460_Softune/SRC/vectors.c b/Demo/MB91460_Softune/SRC/vectors.c
index c99e149..3d94b66 100644
--- a/Demo/MB91460_Softune/SRC/vectors.c
+++ b/Demo/MB91460_Softune/SRC/vectors.c
@@ -17,6 +17,7 @@
 
 #include "mb91467d.h"
 #include "watchdog.h"
+#include "FreeRTOSConfig.h"
 
 /*------------------------------------------------------------------------
   InitIrqLevels()
@@ -34,133 +35,133 @@
 	/*  ICRxx */ 
 	/* Softune Workbench Monitor Debugger is using ext int0 for abort function */
 	/*  ICR00 = 31;  *//* External Interrupt 0		 */
-					/* External Interrupt 1		*/				 
-	ICR01 = 31;		/* External Interrupt 2		*/
-					/* External Interrupt 3		*/
-	ICR02 = 31;		/* External Interrupt 4		*/
-					/* External Interrupt 5		*/
-	ICR03 = 31;		/* External Interrupt 6		*/
-					/* External Interrupt 7		*/
-	ICR04 = 31;		/* External Interrupt 8		*/
-					/* External Interrupt 9		*/
-	ICR05 = 31;		/* External Interrupt 10	*/
-					/* External Interrupt 11	*/
-	ICR06 = 31;		/* External Interrupt 12	*/
-					/* External Interrupt 13	*/
-	ICR07 = 31;		/* External Interrupt 14	*/
-					/* External Interrupt 15	*/
-	ICR08 = 30;		/* Reload Timer 0			*/
-					/* Reload Timer 1			*/
-	ICR09 = 31;		/* Reload Timer 2			*/
-					/* Reload Timer 3			*/
-	ICR10 = 31;		/* Reload Timer 4			*/
-					/* Reload Timer 5			*/
-	ICR11 = 31;		/* Reload Timer 6			*/
-					/* Reload Timer 7			*/
-	ICR12 = 31;		/* Free Run Timer 0			*/
-					/* Free Run Timer 1			*/
-	ICR13 = 31;		/* Free Run Timer 2			*/
-					/* Free Run Timer 3			*/
-	ICR14 = 31;		/* Free Run Timer 4			*/
-					/* Free Run Timer 5			*/
-	ICR15 = 31;		/* Free Run Timer 6			*/
-					/* Free Run Timer 7			*/
-	ICR16 = 31;		/* CAN 0					*/
-					/* CAN 1					*/
-	ICR17 = 31;		/* CAN 2					*/
-					/* CAN 3					*/
-	ICR18 = 31;		/* CAN 4					*/
-					/* CAN 5					*/
-	ICR19 = 31;		/* USART (LIN) 0 RX			*/
-					/* USART (LIN) 0 TX			*/
-	ICR20 = 31;		/* USART (LIN) 1 RX			*/
-					/* USART (LIN) 1 TX			*/
-	ICR21 = 30;		/* USART (LIN) 2 RX			*/
-					/* USART (LIN) 2 TX			*/
-	ICR22 = 31;		/* USART (LIN) 3 RX			*/
-					/* USART (LIN) 3 TX			*/
-	ICR23 = 30;		/* System Reserved			*/
-					/* Delayed Interrupt		*/
-	ICR24 = 31;		/* System Reserved			*/
-					/* System Reserved			*/
-	ICR25 = 31;		/* USART (LIN, FIFO) 4 RX	*/
-					/* USART (LIN, FIFO) 4 TX	*/
-	ICR26 = 30;		/* USART (LIN, FIFO) 5 RX	*/
-					/* USART (LIN, FIFO) 5 TX	*/
-	ICR27 = 31;		/* USART (LIN, FIFO) 6 RX	*/
-					/* USART (LIN, FIFO) 6 TX	*/
-	ICR28 = 31;		/* USART (LIN, FIFO) 7 RX	*/
-					/* USART (LIN, FIFO) 7 TX	*/
-	ICR29 = 31;		/* I2C 0 / I2C 2			*/
-					/* I2C 1 / I2C 3			*/
-	ICR30 = 31;		/* USART (LIN, FIFO) 8 RX	*/
-					/* USART (LIN, FIFO) 8 TX	*/
-	ICR31 = 31;		/* USART (LIN, FIFO) 9 RX	*/
-					/* USART (LIN, FIFO) 9 TX	*/
-	ICR32 = 31;		/* USART (LIN, FIFO) 10 RX	*/
-					/* USART (LIN, FIFO) 10 TX	*/
-	ICR33 = 31;		/* USART (LIN, FIFO) 11 RX	*/
-					/* USART (LIN, FIFO) 11 TX	*/
-	ICR34 = 31;		/* USART (LIN, FIFO) 12 RX	*/
-					/* USART (LIN, FIFO) 12 TX	*/
-	ICR35 = 31;		/* USART (LIN, FIFO) 13 RX	*/
-					/* USART (LIN, FIFO) 13 TX	*/
-	ICR36 = 31;		/* USART (LIN, FIFO) 14 RX	*/
-					/* USART (LIN, FIFO) 14 TX	*/
-	ICR37 = 31;		/* USART (LIN, FIFO) 15 RX	*/
-					/* USART (LIN, FIFO) 15 TX	*/
-	ICR38 = 31;		/* Input Capture 0			*/
-					/* Input Capture 1			*/
-	ICR39 = 31;		/* Input Capture 2			*/
-					/* Input Capture 3			*/
-	ICR40 = 31;		/* Input Capture 4			*/
-					/* Input Capture 5			*/
-	ICR41 = 31;		/* Input Capture 6			*/
-					/* Input Capture 7			*/
-	ICR42 = 31;		/* Output Compare 0			*/
-					/* Output Compare 1			*/
-	ICR43 = 31;		/* Output Compare 2			*/
-					/* Output Compare 3			*/
-	ICR44 = 31;		/* Output Compare 4			*/
-					/* Output Compare 5			*/
-	ICR45 = 31;		/* Output Compare 6			*/
-					/* Output Compare 7			*/
-	ICR46 = 31;		/* Sound Generator			*/
-					/* Phase Frequ. Modulator	*/
-	ICR47 = 31;		/* System Reserved			*/
-					/* System Reserved			*/
-	ICR48 = 31;		/* Prog. Pulse Gen. 0		*/
-					/* Prog. Pulse Gen. 1		*/
-	ICR49 = 31;		/* Prog. Pulse Gen. 2		*/
-					/* Prog. Pulse Gen. 3		*/
-	ICR50 = 31;		/* Prog. Pulse Gen. 4		*/
-					/* Prog. Pulse Gen. 5		*/
-	ICR51 = 31;		/* Prog. Pulse Gen. 6		*/
-					/* Prog. Pulse Gen. 7		*/
-	ICR52 = 31;		/* Prog. Pulse Gen. 8		*/
-					/* Prog. Pulse Gen. 9		*/
-	ICR53 = 31;		/* Prog. Pulse Gen. 10		*/
-					/* Prog. Pulse Gen. 11		*/
-	ICR54 = 31;		/* Prog. Pulse Gen. 12		*/
-					/* Prog. Pulse Gen. 13		*/
-	ICR55 = 31;		/* Prog. Pulse Gen. 14		*/
-					/* Prog. Pulse Gen. 15		*/
-	ICR56 = 31;		/* Up/Down Counter 0		*/
-					/* Up/Down Counter 1		*/
-	ICR57 = 31;		/* Up/Down Counter 2		*/
-					/* Up/Down Counter 3		*/
-	ICR58 = 31;		/* Real Time Clock			*/
-					/* Calibration Unit			*/
-	ICR59 = 31;		/* A/D Converter 0			*/
-					/* -						*/
-	ICR60 = 31;		/* Alarm Comperator 0		*/
-					/* Alarm Comperator 1		*/
-	ICR61 = 31;		/* Low Volage Detector		*/
-					/* SMC Zero Point 0-5		*/
-	ICR62 = 31;		/* Timebase Overflow		*/
-					/* PLL Clock Gear			*/
-	ICR63 = 31;		/* DMA Controller			*/
-					/* Main/Sub OSC stability wait  */
+												/* External Interrupt 1		*/				 
+	ICR01 = 31;									/* External Interrupt 2		*/
+												/* External Interrupt 3		*/
+	ICR02 = 31;									/* External Interrupt 4		*/
+												/* External Interrupt 5		*/
+	ICR03 = 31;									/* External Interrupt 6		*/
+												/* External Interrupt 7		*/
+	ICR04 = 31;									/* External Interrupt 8		*/
+												/* External Interrupt 9		*/
+	ICR05 = 31;									/* External Interrupt 10	*/
+												/* External Interrupt 11	*/
+	ICR06 = 31;									/* External Interrupt 12	*/
+												/* External Interrupt 13	*/
+	ICR07 = 31;									/* External Interrupt 14	*/
+												/* External Interrupt 15	*/
+	ICR08 = configKERNEL_INTERRUPT_PRIORITY;	/* Reload Timer 0			*/
+												/* Reload Timer 1			*/
+	ICR09 = 31;									/* Reload Timer 2			*/
+												/* Reload Timer 3			*/
+	ICR10 = 31;									/* Reload Timer 4			*/
+												/* Reload Timer 5			*/
+	ICR11 = 31;									/* Reload Timer 6			*/
+												/* Reload Timer 7			*/
+	ICR12 = 31;									/* Free Run Timer 0			*/
+												/* Free Run Timer 1			*/
+	ICR13 = 31;									/* Free Run Timer 2			*/
+												/* Free Run Timer 3			*/
+	ICR14 = 31;									/* Free Run Timer 4			*/
+												/* Free Run Timer 5			*/
+	ICR15 = 31;									/* Free Run Timer 6			*/
+												/* Free Run Timer 7			*/
+	ICR16 = 31;									/* CAN 0					*/
+												/* CAN 1					*/
+	ICR17 = 31;									/* CAN 2					*/
+												/* CAN 3					*/
+	ICR18 = 31;									/* CAN 4					*/
+												/* CAN 5					*/
+	ICR19 = 31;									/* USART (LIN) 0 RX			*/
+												/* USART (LIN) 0 TX			*/
+	ICR20 = 31;									/* USART (LIN) 1 RX			*/
+												/* USART (LIN) 1 TX			*/
+	ICR21 = configKERNEL_INTERRUPT_PRIORITY;	/* USART (LIN) 2 RX			*/
+												/* USART (LIN) 2 TX			*/
+	ICR22 = 31;									/* USART (LIN) 3 RX			*/
+												/* USART (LIN) 3 TX			*/
+	ICR23 = configKERNEL_INTERRUPT_PRIORITY;	/* System Reserved			*/
+												/* Delayed Interrupt		*/
+	ICR24 = 31;									/* System Reserved			*/
+												/* System Reserved			*/
+	ICR25 = 31;									/* USART (LIN, FIFO) 4 RX	*/
+												/* USART (LIN, FIFO) 4 TX	*/
+	ICR26 = configKERNEL_INTERRUPT_PRIORITY;	/* USART (LIN, FIFO) 5 RX	*/
+												/* USART (LIN, FIFO) 5 TX	*/
+	ICR27 = 31;									/* USART (LIN, FIFO) 6 RX	*/
+												/* USART (LIN, FIFO) 6 TX	*/
+	ICR28 = 31;									/* USART (LIN, FIFO) 7 RX	*/
+												/* USART (LIN, FIFO) 7 TX	*/
+	ICR29 = 31;									/* I2C 0 / I2C 2			*/
+												/* I2C 1 / I2C 3			*/
+	ICR30 = 31;									/* USART (LIN, FIFO) 8 RX	*/
+												/* USART (LIN, FIFO) 8 TX	*/
+	ICR31 = 31;									/* USART (LIN, FIFO) 9 RX	*/
+												/* USART (LIN, FIFO) 9 TX	*/
+	ICR32 = 31;									/* USART (LIN, FIFO) 10 RX	*/
+												/* USART (LIN, FIFO) 10 TX	*/
+	ICR33 = 31;									/* USART (LIN, FIFO) 11 RX	*/
+												/* USART (LIN, FIFO) 11 TX	*/
+	ICR34 = 31;									/* USART (LIN, FIFO) 12 RX	*/
+												/* USART (LIN, FIFO) 12 TX	*/
+	ICR35 = 31;									/* USART (LIN, FIFO) 13 RX	*/
+												/* USART (LIN, FIFO) 13 TX	*/
+	ICR36 = 31;									/* USART (LIN, FIFO) 14 RX	*/
+												/* USART (LIN, FIFO) 14 TX	*/
+	ICR37 = 31;									/* USART (LIN, FIFO) 15 RX	*/
+												/* USART (LIN, FIFO) 15 TX	*/
+	ICR38 = 31;									/* Input Capture 0			*/
+												/* Input Capture 1			*/
+	ICR39 = 31;									/* Input Capture 2			*/
+												/* Input Capture 3			*/
+	ICR40 = 31;									/* Input Capture 4			*/
+												/* Input Capture 5			*/
+	ICR41 = 31;									/* Input Capture 6			*/
+												/* Input Capture 7			*/
+	ICR42 = 31;									/* Output Compare 0			*/
+												/* Output Compare 1			*/
+	ICR43 = 31;									/* Output Compare 2			*/
+												/* Output Compare 3			*/
+	ICR44 = 31;									/* Output Compare 4			*/
+												/* Output Compare 5			*/
+	ICR45 = 31;									/* Output Compare 6			*/
+												/* Output Compare 7			*/
+	ICR46 = 31;									/* Sound Generator			*/
+												/* Phase Frequ. Modulator	*/
+	ICR47 = 31;									/* System Reserved			*/
+												/* System Reserved			*/
+	ICR48 = 31;									/* Prog. Pulse Gen. 0		*/
+												/* Prog. Pulse Gen. 1		*/
+	ICR49 = 31;									/* Prog. Pulse Gen. 2		*/
+												/* Prog. Pulse Gen. 3		*/
+	ICR50 = 31;									/* Prog. Pulse Gen. 4		*/
+												/* Prog. Pulse Gen. 5		*/
+	ICR51 = 31;									/* Prog. Pulse Gen. 6		*/
+												/* Prog. Pulse Gen. 7		*/
+	ICR52 = 31;									/* Prog. Pulse Gen. 8		*/
+												/* Prog. Pulse Gen. 9		*/
+	ICR53 = 31;									/* Prog. Pulse Gen. 10		*/
+												/* Prog. Pulse Gen. 11		*/
+	ICR54 = 31;									/* Prog. Pulse Gen. 12		*/
+												/* Prog. Pulse Gen. 13		*/
+	ICR55 = 31;									/* Prog. Pulse Gen. 14		*/
+												/* Prog. Pulse Gen. 15		*/
+	ICR56 = 31;									/* Up/Down Counter 0		*/
+												/* Up/Down Counter 1		*/
+	ICR57 = 31;									/* Up/Down Counter 2		*/
+												/* Up/Down Counter 3		*/
+	ICR58 = 31;									/* Real Time Clock			*/
+												/* Calibration Unit			*/
+	ICR59 = 31;									/* A/D Converter 0			*/
+												/* -						*/
+	ICR60 = 31;									/* Alarm Comperator 0		*/
+												/* Alarm Comperator 1		*/
+	ICR61 = 31;									/* Low Volage Detector		*/
+												/* SMC Zero Point 0-5		*/
+	ICR62 = 31;									/* Timebase Overflow		*/
+												/* PLL Clock Gear			*/
+	ICR63 = 31;									/* DMA Controller			*/
+												/* Main/Sub OSC stability wait  */
 }
 
 
diff --git a/Demo/MB91460_Softune/SRC/vectors.h b/Demo/MB91460_Softune/SRC/vectors.h
index 058e000..579a7e1 100644
--- a/Demo/MB91460_Softune/SRC/vectors.h
+++ b/Demo/MB91460_Softune/SRC/vectors.h
@@ -9,5 +9,10 @@
   06.10.06  1.00   UMa    Initial Version
 -----------------------------------------------------------------------------*/
 
+#ifndef VECTORS_H
+#define VECTORS_H
 
-void InitIrqLevels(void);
+void InitIrqLevels( void );
+
+#endif
+
diff --git a/Demo/MB91460_Softune/SRC/watchdog/watchdog.h b/Demo/MB91460_Softune/SRC/watchdog/watchdog.h
index 9f95d24..e99e64e 100644
--- a/Demo/MB91460_Softune/SRC/watchdog/watchdog.h
+++ b/Demo/MB91460_Softune/SRC/watchdog/watchdog.h
@@ -6,6 +6,10 @@
   watchdog.h
   - This file contains the defines and function declaration for hardware watchdog.
 -------------------------------------------------------------------------*/
+
+#ifndef WATCHDOG_H
+#define WATCHDOG_H
+
 /* 
  * Clear watchdog defines 
  */
@@ -44,3 +48,5 @@
 void InitWatchdog (void);
 void vStartWatchdogTask(unsigned portSHORT);
 
+#endif
+