)]}'
{
  "commit": "6270e2aebfb24caead2dc928f31043cccd6b62fd",
  "tree": "f3b273b064af507d31540d8942c2b40722aa9af6",
  "parents": [
    "5da55ba8ade5f752104a3138609013d6d086ef31"
  ],
  "author": {
    "name": "Florian La Roche",
    "email": "florian.laroche@gmail.com",
    "time": "Tue Apr 09 07:21:12 2024 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Apr 09 10:51:12 2024 +0530"
  },
  "message": "Update the memory alignment within the Cortex-R5 port asm code (#1023)\n\nUpdate alignment in ARM_CR5 port.\r\n\r\nThis is the same patch as 553caa18ced4906cf5060823ada7a10e73c7b535\r\nprovided by Richard Barry for issue #426 (ARM_CA9).\r\n\r\nSigned-off-by: Florian La Roche \u003cFlorian.LaRoche@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1590ee4e8579b6c65d55485a22b54c7b26797210",
      "old_mode": 33188,
      "old_path": "portable/GCC/ARM_CR5/portASM.S",
      "new_id": "3c39ef1b664b44671f12b9c85fef364a51b66684",
      "new_mode": 33188,
      "new_path": "portable/GCC/ARM_CR5/portASM.S"
    }
  ]
}