)]}'
{
  "commit": "64fd9291ef668d0f3695771f0ce596d5e6c75802",
  "tree": "9fbec248a3c9ce1046a5351fa623a5de2ca97c31",
  "parents": [
    "bb47bc02f2a8705707258c254a3cea5bc74cc9e5"
  ],
  "author": {
    "name": "Saiiijchan",
    "email": "49641410+Saiiijchan@users.noreply.github.com",
    "time": "Thu Mar 13 23:40:51 2025 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Mar 13 21:10:51 2025 +0530"
  },
  "message": "RISC-V: refine fpu reg context offset (#1257)\n\nRISC-V: refine fpu reg context offset\n\npxCode and mstatus stored at index 0 and 1 are based on XLEN.\nTherefore, the correct formula to calculate the FPU register index\nshould be ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ).\n\nSigned-off-by: wangfei_chen \u003cwangfei_chen@realsil.com.cn\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d191b4aea36797e1ff8ee5ab09d0f671192a7675",
      "old_mode": 33188,
      "old_path": "portable/GCC/RISC-V/portContext.h",
      "new_id": "aa57f3ec1b691f92fbe305b74b4ccd7261fe7bcc",
      "new_mode": 33188,
      "new_path": "portable/GCC/RISC-V/portContext.h"
    }
  ]
}