
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 
* DO NOT EDIT.
*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
* 
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*

* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xzdma.h"

/*
* The configuration table for devices
*/

XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES] =
{
	{
		XPAR_PSU_ADMA_0_DEVICE_ID,
		XPAR_PSU_ADMA_0_BASEADDR,
		XPAR_PSU_ADMA_0_DMA_MODE,
		XPAR_PSU_ADMA_0_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_1_DEVICE_ID,
		XPAR_PSU_ADMA_1_BASEADDR,
		XPAR_PSU_ADMA_1_DMA_MODE,
		XPAR_PSU_ADMA_1_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_2_DEVICE_ID,
		XPAR_PSU_ADMA_2_BASEADDR,
		XPAR_PSU_ADMA_2_DMA_MODE,
		XPAR_PSU_ADMA_2_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_3_DEVICE_ID,
		XPAR_PSU_ADMA_3_BASEADDR,
		XPAR_PSU_ADMA_3_DMA_MODE,
		XPAR_PSU_ADMA_3_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_4_DEVICE_ID,
		XPAR_PSU_ADMA_4_BASEADDR,
		XPAR_PSU_ADMA_4_DMA_MODE,
		XPAR_PSU_ADMA_4_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_5_DEVICE_ID,
		XPAR_PSU_ADMA_5_BASEADDR,
		XPAR_PSU_ADMA_5_DMA_MODE,
		XPAR_PSU_ADMA_5_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_6_DEVICE_ID,
		XPAR_PSU_ADMA_6_BASEADDR,
		XPAR_PSU_ADMA_6_DMA_MODE,
		XPAR_PSU_ADMA_6_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_ADMA_7_DEVICE_ID,
		XPAR_PSU_ADMA_7_BASEADDR,
		XPAR_PSU_ADMA_7_DMA_MODE,
		XPAR_PSU_ADMA_7_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_0_DEVICE_ID,
		XPAR_PSU_GDMA_0_BASEADDR,
		XPAR_PSU_GDMA_0_DMA_MODE,
		XPAR_PSU_GDMA_0_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_1_DEVICE_ID,
		XPAR_PSU_GDMA_1_BASEADDR,
		XPAR_PSU_GDMA_1_DMA_MODE,
		XPAR_PSU_GDMA_1_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_2_DEVICE_ID,
		XPAR_PSU_GDMA_2_BASEADDR,
		XPAR_PSU_GDMA_2_DMA_MODE,
		XPAR_PSU_GDMA_2_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_3_DEVICE_ID,
		XPAR_PSU_GDMA_3_BASEADDR,
		XPAR_PSU_GDMA_3_DMA_MODE,
		XPAR_PSU_GDMA_3_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_4_DEVICE_ID,
		XPAR_PSU_GDMA_4_BASEADDR,
		XPAR_PSU_GDMA_4_DMA_MODE,
		XPAR_PSU_GDMA_4_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_5_DEVICE_ID,
		XPAR_PSU_GDMA_5_BASEADDR,
		XPAR_PSU_GDMA_5_DMA_MODE,
		XPAR_PSU_GDMA_5_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_6_DEVICE_ID,
		XPAR_PSU_GDMA_6_BASEADDR,
		XPAR_PSU_GDMA_6_DMA_MODE,
		XPAR_PSU_GDMA_6_IS_CACHE_COHERENT
	},
	{
		XPAR_PSU_GDMA_7_DEVICE_ID,
		XPAR_PSU_GDMA_7_BASEADDR,
		XPAR_PSU_GDMA_7_DMA_MODE,
		XPAR_PSU_GDMA_7_IS_CACHE_COHERENT
	}
};