/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
* 
*  This program is free software; you can redistribute it and/or modify
*  it under the terms of the GNU General Public License as published by
*  the Free Software Foundation; either version 2 of the License, or
*  (at your option) any later version.
*
*  This program is distributed in the hope that it will be useful,
*  but WITHOUT ANY WARRANTY; without even the implied warranty of
*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*  GNU General Public License for more details.
* 
*  You should have received a copy of the GNU General Public License along
*  with this program; if not, see <http://www.gnu.org/licenses/>
* 
* 
******************************************************************************/
/****************************************************************************/
/**
*
* @file psu_init_gpl.h
*
* This file is automatically generated
*
*****************************************************************************/


#undef CRL_APB_RPLL_CFG_OFFSET 
#define CRL_APB_RPLL_CFG_OFFSET                                                    0XFF5E0034
#undef CRL_APB_RPLL_CTRL_OFFSET 
#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
#undef CRL_APB_RPLL_CTRL_OFFSET 
#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
#undef CRL_APB_RPLL_CTRL_OFFSET 
#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
#undef CRL_APB_RPLL_CTRL_OFFSET 
#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
#undef CRL_APB_RPLL_CTRL_OFFSET 
#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 
#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
#undef CRL_APB_IOPLL_CFG_OFFSET 
#define CRL_APB_IOPLL_CFG_OFFSET                                                   0XFF5E0024
#undef CRL_APB_IOPLL_CTRL_OFFSET 
#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
#undef CRL_APB_IOPLL_CTRL_OFFSET 
#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
#undef CRL_APB_IOPLL_CTRL_OFFSET 
#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
#undef CRL_APB_IOPLL_CTRL_OFFSET 
#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
#undef CRL_APB_IOPLL_CTRL_OFFSET 
#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 
#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
#undef CRF_APB_APLL_CFG_OFFSET 
#define CRF_APB_APLL_CFG_OFFSET                                                    0XFD1A0024
#undef CRF_APB_APLL_CTRL_OFFSET 
#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
#undef CRF_APB_APLL_CTRL_OFFSET 
#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
#undef CRF_APB_APLL_CTRL_OFFSET 
#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
#undef CRF_APB_APLL_CTRL_OFFSET 
#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
#undef CRF_APB_APLL_CTRL_OFFSET 
#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET 
#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
#undef CRF_APB_DPLL_CFG_OFFSET 
#define CRF_APB_DPLL_CFG_OFFSET                                                    0XFD1A0030
#undef CRF_APB_DPLL_CTRL_OFFSET 
#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
#undef CRF_APB_DPLL_CTRL_OFFSET 
#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
#undef CRF_APB_DPLL_CTRL_OFFSET 
#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
#undef CRF_APB_DPLL_CTRL_OFFSET 
#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
#undef CRF_APB_DPLL_CTRL_OFFSET 
#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 
#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
#undef CRF_APB_VPLL_CFG_OFFSET 
#define CRF_APB_VPLL_CFG_OFFSET                                                    0XFD1A003C
#undef CRF_APB_VPLL_CTRL_OFFSET 
#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
#undef CRF_APB_VPLL_CTRL_OFFSET 
#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
#undef CRF_APB_VPLL_CTRL_OFFSET 
#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
#undef CRF_APB_VPLL_CTRL_OFFSET 
#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
#undef CRF_APB_VPLL_CTRL_OFFSET 
#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 
#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050

/*
* PLL loop filter resistor control
*/
#undef CRL_APB_RPLL_CFG_RES_DEFVAL 
#undef CRL_APB_RPLL_CFG_RES_SHIFT 
#undef CRL_APB_RPLL_CFG_RES_MASK 
#define CRL_APB_RPLL_CFG_RES_DEFVAL                            0x00000000
#define CRL_APB_RPLL_CFG_RES_SHIFT                             0
#define CRL_APB_RPLL_CFG_RES_MASK                              0x0000000FU

/*
* PLL charge pump control
*/
#undef CRL_APB_RPLL_CFG_CP_DEFVAL 
#undef CRL_APB_RPLL_CFG_CP_SHIFT 
#undef CRL_APB_RPLL_CFG_CP_MASK 
#define CRL_APB_RPLL_CFG_CP_DEFVAL                             0x00000000
#define CRL_APB_RPLL_CFG_CP_SHIFT                              5
#define CRL_APB_RPLL_CFG_CP_MASK                               0x000001E0U

/*
* PLL loop filter high frequency capacitor control
*/
#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL 
#undef CRL_APB_RPLL_CFG_LFHF_SHIFT 
#undef CRL_APB_RPLL_CFG_LFHF_MASK 
#define CRL_APB_RPLL_CFG_LFHF_DEFVAL                           0x00000000
#define CRL_APB_RPLL_CFG_LFHF_SHIFT                            10
#define CRL_APB_RPLL_CFG_LFHF_MASK                             0x00000C00U

/*
* Lock circuit counter setting
*/
#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 
#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 
#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK 
#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT                        13
#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK                         0x007FE000U

/*
* Lock circuit configuration settings for lock windowsize
*/
#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 
#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 
#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK 
#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT                        25
#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK                         0xFE000000U

/*
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
*/
#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 
#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 
#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK 
#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL                       0x00012C09
#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT                        20
#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK                         0x00700000U

/*
* The integer portion of the feedback divider to the PLL
*/
#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 
#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT 
#undef CRL_APB_RPLL_CTRL_FBDIV_MASK 
#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                         0x00012C09
#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                          8
#define CRL_APB_RPLL_CTRL_FBDIV_MASK                           0x00007F00U

/*
* This turns on the divide by 2 that is inside of the PLL. This does not c
    * hange the VCO frequency, just the output frequency
*/
#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL 
#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT 
#undef CRL_APB_RPLL_CTRL_DIV2_MASK 
#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                          0x00012C09
#define CRL_APB_RPLL_CTRL_DIV2_SHIFT                           16
#define CRL_APB_RPLL_CTRL_DIV2_MASK                            0x00010000U

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                        0x00012C09
#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                         3
#define CRL_APB_RPLL_CTRL_BYPASS_MASK                          0x00000008U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
#undef CRL_APB_RPLL_CTRL_RESET_MASK 
#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                         0x00012C09
#define CRL_APB_RPLL_CTRL_RESET_SHIFT                          0
#define CRL_APB_RPLL_CTRL_RESET_MASK                           0x00000001U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
#undef CRL_APB_RPLL_CTRL_RESET_MASK 
#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                         0x00012C09
#define CRL_APB_RPLL_CTRL_RESET_SHIFT                          0
#define CRL_APB_RPLL_CTRL_RESET_MASK                           0x00000001U

/*
* RPLL is locked
*/
#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 
#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 
#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 
#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                    0x00000018
#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                     1
#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                      0x00000002U
#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                        0x00012C09
#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                         3
#define CRL_APB_RPLL_CTRL_BYPASS_MASK                          0x00000008U

/*
* Divisor value for this clock.
*/
#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 
#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL               0x00000400
#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                8
#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                 0x00003F00U

/*
* PLL loop filter resistor control
*/
#undef CRL_APB_IOPLL_CFG_RES_DEFVAL 
#undef CRL_APB_IOPLL_CFG_RES_SHIFT 
#undef CRL_APB_IOPLL_CFG_RES_MASK 
#define CRL_APB_IOPLL_CFG_RES_DEFVAL                           0x00000000
#define CRL_APB_IOPLL_CFG_RES_SHIFT                            0
#define CRL_APB_IOPLL_CFG_RES_MASK                             0x0000000FU

/*
* PLL charge pump control
*/
#undef CRL_APB_IOPLL_CFG_CP_DEFVAL 
#undef CRL_APB_IOPLL_CFG_CP_SHIFT 
#undef CRL_APB_IOPLL_CFG_CP_MASK 
#define CRL_APB_IOPLL_CFG_CP_DEFVAL                            0x00000000
#define CRL_APB_IOPLL_CFG_CP_SHIFT                             5
#define CRL_APB_IOPLL_CFG_CP_MASK                              0x000001E0U

/*
* PLL loop filter high frequency capacitor control
*/
#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL 
#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT 
#undef CRL_APB_IOPLL_CFG_LFHF_MASK 
#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL                          0x00000000
#define CRL_APB_IOPLL_CFG_LFHF_SHIFT                           10
#define CRL_APB_IOPLL_CFG_LFHF_MASK                            0x00000C00U

/*
* Lock circuit counter setting
*/
#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 
#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 
#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 
#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL                      0x00000000
#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT                       13
#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK                        0x007FE000U

/*
* Lock circuit configuration settings for lock windowsize
*/
#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 
#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 
#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 
#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL                      0x00000000
#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT                       25
#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK                        0xFE000000U

/*
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
*/
#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 
#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 
#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 
#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL                      0x00012C09
#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT                       20
#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK                        0x00700000U

/*
* The integer portion of the feedback divider to the PLL
*/
#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 
#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 
#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK 
#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                        0x00012C09
#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                         8
#define CRL_APB_IOPLL_CTRL_FBDIV_MASK                          0x00007F00U

/*
* This turns on the divide by 2 that is inside of the PLL. This does not c
    * hange the VCO frequency, just the output frequency
*/
#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 
#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT 
#undef CRL_APB_IOPLL_CTRL_DIV2_MASK 
#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                         0x00012C09
#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                          16
#define CRL_APB_IOPLL_CTRL_DIV2_MASK                           0x00010000U

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                       0x00012C09
#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                        3
#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                         0x00000008U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                        0x00012C09
#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                         0
#define CRL_APB_IOPLL_CTRL_RESET_MASK                          0x00000001U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                        0x00012C09
#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                         0
#define CRL_APB_IOPLL_CTRL_RESET_MASK                          0x00000001U

/*
* IOPLL is locked
*/
#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 
#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 
#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                   0x00000018
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                    0
#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                     0x00000001U
#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                       0x00012C09
#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                        3
#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                         0x00000008U

/*
* Divisor value for this clock.
*/
#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL              0x00000400
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT               8
#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                0x00003F00U

/*
* PLL loop filter resistor control
*/
#undef CRF_APB_APLL_CFG_RES_DEFVAL 
#undef CRF_APB_APLL_CFG_RES_SHIFT 
#undef CRF_APB_APLL_CFG_RES_MASK 
#define CRF_APB_APLL_CFG_RES_DEFVAL                            0x00000000
#define CRF_APB_APLL_CFG_RES_SHIFT                             0
#define CRF_APB_APLL_CFG_RES_MASK                              0x0000000FU

/*
* PLL charge pump control
*/
#undef CRF_APB_APLL_CFG_CP_DEFVAL 
#undef CRF_APB_APLL_CFG_CP_SHIFT 
#undef CRF_APB_APLL_CFG_CP_MASK 
#define CRF_APB_APLL_CFG_CP_DEFVAL                             0x00000000
#define CRF_APB_APLL_CFG_CP_SHIFT                              5
#define CRF_APB_APLL_CFG_CP_MASK                               0x000001E0U

/*
* PLL loop filter high frequency capacitor control
*/
#undef CRF_APB_APLL_CFG_LFHF_DEFVAL 
#undef CRF_APB_APLL_CFG_LFHF_SHIFT 
#undef CRF_APB_APLL_CFG_LFHF_MASK 
#define CRF_APB_APLL_CFG_LFHF_DEFVAL                           0x00000000
#define CRF_APB_APLL_CFG_LFHF_SHIFT                            10
#define CRF_APB_APLL_CFG_LFHF_MASK                             0x00000C00U

/*
* Lock circuit counter setting
*/
#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 
#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 
#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK 
#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT                        13
#define CRF_APB_APLL_CFG_LOCK_CNT_MASK                         0x007FE000U

/*
* Lock circuit configuration settings for lock windowsize
*/
#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 
#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 
#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK 
#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT                        25
#define CRF_APB_APLL_CFG_LOCK_DLY_MASK                         0xFE000000U

/*
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
*/
#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 
#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 
#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK 
#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL                       0x00012C09
#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT                        20
#define CRF_APB_APLL_CTRL_PRE_SRC_MASK                         0x00700000U

/*
* The integer portion of the feedback divider to the PLL
*/
#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL 
#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT 
#undef CRF_APB_APLL_CTRL_FBDIV_MASK 
#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                         0x00012C09
#define CRF_APB_APLL_CTRL_FBDIV_SHIFT                          8
#define CRF_APB_APLL_CTRL_FBDIV_MASK                           0x00007F00U

/*
* This turns on the divide by 2 that is inside of the PLL. This does not c
    * hange the VCO frequency, just the output frequency
*/
#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL 
#undef CRF_APB_APLL_CTRL_DIV2_SHIFT 
#undef CRF_APB_APLL_CTRL_DIV2_MASK 
#define CRF_APB_APLL_CTRL_DIV2_DEFVAL                          0x00012C09
#define CRF_APB_APLL_CTRL_DIV2_SHIFT                           16
#define CRF_APB_APLL_CTRL_DIV2_MASK                            0x00010000U

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                        0x00012C09
#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                         3
#define CRF_APB_APLL_CTRL_BYPASS_MASK                          0x00000008U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
#undef CRF_APB_APLL_CTRL_RESET_MASK 
#define CRF_APB_APLL_CTRL_RESET_DEFVAL                         0x00012C09
#define CRF_APB_APLL_CTRL_RESET_SHIFT                          0
#define CRF_APB_APLL_CTRL_RESET_MASK                           0x00000001U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
#undef CRF_APB_APLL_CTRL_RESET_MASK 
#define CRF_APB_APLL_CTRL_RESET_DEFVAL                         0x00012C09
#define CRF_APB_APLL_CTRL_RESET_SHIFT                          0
#define CRF_APB_APLL_CTRL_RESET_MASK                           0x00000001U

/*
* APLL is locked
*/
#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 
#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 
#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK 
#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                    0x00000038
#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                     0
#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                      0x00000001U
#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                        0x00012C09
#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                         3
#define CRF_APB_APLL_CTRL_BYPASS_MASK                          0x00000008U

/*
* Divisor value for this clock.
*/
#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U

/*
* PLL loop filter resistor control
*/
#undef CRF_APB_DPLL_CFG_RES_DEFVAL 
#undef CRF_APB_DPLL_CFG_RES_SHIFT 
#undef CRF_APB_DPLL_CFG_RES_MASK 
#define CRF_APB_DPLL_CFG_RES_DEFVAL                            0x00000000
#define CRF_APB_DPLL_CFG_RES_SHIFT                             0
#define CRF_APB_DPLL_CFG_RES_MASK                              0x0000000FU

/*
* PLL charge pump control
*/
#undef CRF_APB_DPLL_CFG_CP_DEFVAL 
#undef CRF_APB_DPLL_CFG_CP_SHIFT 
#undef CRF_APB_DPLL_CFG_CP_MASK 
#define CRF_APB_DPLL_CFG_CP_DEFVAL                             0x00000000
#define CRF_APB_DPLL_CFG_CP_SHIFT                              5
#define CRF_APB_DPLL_CFG_CP_MASK                               0x000001E0U

/*
* PLL loop filter high frequency capacitor control
*/
#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL 
#undef CRF_APB_DPLL_CFG_LFHF_SHIFT 
#undef CRF_APB_DPLL_CFG_LFHF_MASK 
#define CRF_APB_DPLL_CFG_LFHF_DEFVAL                           0x00000000
#define CRF_APB_DPLL_CFG_LFHF_SHIFT                            10
#define CRF_APB_DPLL_CFG_LFHF_MASK                             0x00000C00U

/*
* Lock circuit counter setting
*/
#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 
#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 
#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK 
#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT                        13
#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK                         0x007FE000U

/*
* Lock circuit configuration settings for lock windowsize
*/
#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 
#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 
#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK 
#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT                        25
#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK                         0xFE000000U

/*
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
*/
#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 
#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 
#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK 
#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL                       0x00002C09
#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT                        20
#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK                         0x00700000U

/*
* The integer portion of the feedback divider to the PLL
*/
#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 
#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT 
#undef CRF_APB_DPLL_CTRL_FBDIV_MASK 
#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                         0x00002C09
#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                          8
#define CRF_APB_DPLL_CTRL_FBDIV_MASK                           0x00007F00U

/*
* This turns on the divide by 2 that is inside of the PLL. This does not c
    * hange the VCO frequency, just the output frequency
*/
#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL 
#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT 
#undef CRF_APB_DPLL_CTRL_DIV2_MASK 
#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                          0x00002C09
#define CRF_APB_DPLL_CTRL_DIV2_SHIFT                           16
#define CRF_APB_DPLL_CTRL_DIV2_MASK                            0x00010000U

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                        0x00002C09
#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                         3
#define CRF_APB_DPLL_CTRL_BYPASS_MASK                          0x00000008U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
#undef CRF_APB_DPLL_CTRL_RESET_MASK 
#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                         0x00002C09
#define CRF_APB_DPLL_CTRL_RESET_SHIFT                          0
#define CRF_APB_DPLL_CTRL_RESET_MASK                           0x00000001U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
#undef CRF_APB_DPLL_CTRL_RESET_MASK 
#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                         0x00002C09
#define CRF_APB_DPLL_CTRL_RESET_SHIFT                          0
#define CRF_APB_DPLL_CTRL_RESET_MASK                           0x00000001U

/*
* DPLL is locked
*/
#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 
#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 
#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 
#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                    0x00000038
#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                     1
#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                      0x00000002U
#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                        0x00002C09
#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                         3
#define CRF_APB_DPLL_CTRL_BYPASS_MASK                          0x00000008U

/*
* Divisor value for this clock.
*/
#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U

/*
* PLL loop filter resistor control
*/
#undef CRF_APB_VPLL_CFG_RES_DEFVAL 
#undef CRF_APB_VPLL_CFG_RES_SHIFT 
#undef CRF_APB_VPLL_CFG_RES_MASK 
#define CRF_APB_VPLL_CFG_RES_DEFVAL                            0x00000000
#define CRF_APB_VPLL_CFG_RES_SHIFT                             0
#define CRF_APB_VPLL_CFG_RES_MASK                              0x0000000FU

/*
* PLL charge pump control
*/
#undef CRF_APB_VPLL_CFG_CP_DEFVAL 
#undef CRF_APB_VPLL_CFG_CP_SHIFT 
#undef CRF_APB_VPLL_CFG_CP_MASK 
#define CRF_APB_VPLL_CFG_CP_DEFVAL                             0x00000000
#define CRF_APB_VPLL_CFG_CP_SHIFT                              5
#define CRF_APB_VPLL_CFG_CP_MASK                               0x000001E0U

/*
* PLL loop filter high frequency capacitor control
*/
#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL 
#undef CRF_APB_VPLL_CFG_LFHF_SHIFT 
#undef CRF_APB_VPLL_CFG_LFHF_MASK 
#define CRF_APB_VPLL_CFG_LFHF_DEFVAL                           0x00000000
#define CRF_APB_VPLL_CFG_LFHF_SHIFT                            10
#define CRF_APB_VPLL_CFG_LFHF_MASK                             0x00000C00U

/*
* Lock circuit counter setting
*/
#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 
#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 
#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK 
#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT                        13
#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK                         0x007FE000U

/*
* Lock circuit configuration settings for lock windowsize
*/
#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 
#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 
#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK 
#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT                        25
#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK                         0xFE000000U

/*
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
*/
#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 
#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 
#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK 
#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL                       0x00012809
#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT                        20
#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK                         0x00700000U

/*
* The integer portion of the feedback divider to the PLL
*/
#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 
#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT 
#undef CRF_APB_VPLL_CTRL_FBDIV_MASK 
#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                         0x00012809
#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                          8
#define CRF_APB_VPLL_CTRL_FBDIV_MASK                           0x00007F00U

/*
* This turns on the divide by 2 that is inside of the PLL. This does not c
    * hange the VCO frequency, just the output frequency
*/
#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL 
#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT 
#undef CRF_APB_VPLL_CTRL_DIV2_MASK 
#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                          0x00012809
#define CRF_APB_VPLL_CTRL_DIV2_SHIFT                           16
#define CRF_APB_VPLL_CTRL_DIV2_MASK                            0x00010000U

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                        0x00012809
#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                         3
#define CRF_APB_VPLL_CTRL_BYPASS_MASK                          0x00000008U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
#undef CRF_APB_VPLL_CTRL_RESET_MASK 
#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                         0x00012809
#define CRF_APB_VPLL_CTRL_RESET_SHIFT                          0
#define CRF_APB_VPLL_CTRL_RESET_MASK                           0x00000001U

/*
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
    * in BYPASS.
*/
#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
#undef CRF_APB_VPLL_CTRL_RESET_MASK 
#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                         0x00012809
#define CRF_APB_VPLL_CTRL_RESET_SHIFT                          0
#define CRF_APB_VPLL_CTRL_RESET_MASK                           0x00000001U

/*
* VPLL is locked
*/
#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 
#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 
#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 
#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                    0x00000038
#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                     2
#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                      0x00000004U
#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044

/*
* Bypasses the PLL clock. The usable clock will be determined from the POS
    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
    * clock and 4 cycles of the new clock. This is not usually an issue, but d
    * esigners must be aware.)
*/
#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                        0x00012809
#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                         3
#define CRF_APB_VPLL_CTRL_BYPASS_MASK                          0x00000008U

/*
* Divisor value for this clock.
*/
#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U
#undef CRL_APB_GEM3_REF_CTRL_OFFSET 
#define CRL_APB_GEM3_REF_CTRL_OFFSET                                               0XFF5E005C
#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET 
#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET                                            0XFF5E0100
#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET 
#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 
#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
#undef CRL_APB_QSPI_REF_CTRL_OFFSET 
#define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
#undef CRL_APB_SDIO1_REF_CTRL_OFFSET 
#define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET 
#define IOU_SLCR_SDIO_CLK_CTRL_OFFSET                                              0XFF18030C
#undef CRL_APB_UART0_REF_CTRL_OFFSET 
#define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
#undef CRL_APB_UART1_REF_CTRL_OFFSET 
#define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
#undef CRL_APB_I2C0_REF_CTRL_OFFSET 
#define CRL_APB_I2C0_REF_CTRL_OFFSET                                               0XFF5E0120
#undef CRL_APB_I2C1_REF_CTRL_OFFSET 
#define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
#undef CRL_APB_CAN1_REF_CTRL_OFFSET 
#define CRL_APB_CAN1_REF_CTRL_OFFSET                                               0XFF5E0088
#undef CRL_APB_CPU_R5_CTRL_OFFSET 
#define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET 
#define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
#undef CRL_APB_PCAP_CTRL_OFFSET 
#define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET 
#define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET 
#define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
#undef CRL_APB_DBG_LPD_CTRL_OFFSET 
#define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
#undef CRL_APB_ADMA_REF_CTRL_OFFSET 
#define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
#undef CRL_APB_PL0_REF_CTRL_OFFSET 
#define CRL_APB_PL0_REF_CTRL_OFFSET                                                0XFF5E00C0
#undef CRL_APB_AMS_REF_CTRL_OFFSET 
#define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
#undef CRL_APB_DLL_REF_CTRL_OFFSET 
#define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 
#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
#undef CRF_APB_SATA_REF_CTRL_OFFSET 
#define CRF_APB_SATA_REF_CTRL_OFFSET                                               0XFD1A00A0
#undef CRF_APB_PCIE_REF_CTRL_OFFSET 
#define CRF_APB_PCIE_REF_CTRL_OFFSET                                               0XFD1A00B4
#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 
#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 
#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
#undef CRF_APB_DP_STC_REF_CTRL_OFFSET 
#define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
#undef CRF_APB_ACPU_CTRL_OFFSET 
#define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
#undef CRF_APB_DBG_FPD_CTRL_OFFSET 
#define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
#undef CRF_APB_DDR_CTRL_OFFSET 
#define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
#undef CRF_APB_GPU_REF_CTRL_OFFSET 
#define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
#undef CRF_APB_GDMA_REF_CTRL_OFFSET 
#define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
#undef CRF_APB_DPDMA_REF_CTRL_OFFSET 
#define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET 
#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 
#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET 
#define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 
#define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET                                            0XFF180380
#undef FPD_SLCR_WDT_CLK_SEL_OFFSET 
#define FPD_SLCR_WDT_CLK_SEL_OFFSET                                                0XFD610100
#undef IOU_SLCR_WDT_CLK_SEL_OFFSET 
#define IOU_SLCR_WDT_CLK_SEL_OFFSET                                                0XFF180300
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET                                         0XFF410050

/*
* Clock active for the RX channel
*/
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 
#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL                 0x00002500
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT                  26
#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK                   0x04000000U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 
#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL                    0x00002500
#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT                     25
#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK                      0x02000000U

/*
* 6 bit divider
*/
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL                  0x00002500
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT                   16
#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK                    0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL                  0x00002500
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL                    0x00002500
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT                     0
#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* 6 bit divider
*/
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL               0x00051000
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT                8
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK                 0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL                 0x00051000
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT                  0
#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK                   0x00000007U

/*
* 6 bit divider
*/
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL               0x00051000
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT                16
#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK                 0x003F0000U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL                 0x00051000
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT                  24
#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK                   0x01000000U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                0x00052000
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                 25
#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                  0x02000000U

/*
* 6 bit divider
*/
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL              0x00052000
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT               16
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL              0x00052000
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT               8
#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                0x00052000
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                 0
#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                  0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL               0x00052000
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                25
#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                 0x02000000U

/*
* 6 bit divider
*/
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL             0x00052000
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT              16
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK               0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL             0x00052000
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT              8
#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK               0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL               0x00052000
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                0
#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                 0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 
#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                    0x01000800
#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                     24
#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                      0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                  0x01000800
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                   16
#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                    0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                  0x01000800
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                    0x01000800
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                     0
#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                   0x01000F00
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                    24
#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                     0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                 0x01000F00
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                  16
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                   0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                 0x01000F00
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                  8
#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                   0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                   0x01000F00
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                    0
#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                     0x00000007U

/*
* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
    * [51] 1: MIO [76]
*/
#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 
#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 
#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 
#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL         0x00000000
#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT          17
#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK           0x00020000U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK 
#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                   0x01001800
#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                    24
#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                     0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                 0x01001800
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                  16
#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                   0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                 0x01001800
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                  8
#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                   0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                   0x01001800
#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                    0
#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                     0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK 
#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                   0x01001800
#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                    24
#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                     0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                 0x01001800
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                  16
#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                   0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                 0x01001800
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                  8
#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                   0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                   0x01001800
#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                    0
#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                     0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 
#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL                    0x01000500
#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT                     24
#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK                      0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL                  0x01000500
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT                   16
#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK                    0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL                  0x01000500
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL                    0x01000500
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT                     0
#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 
#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                    0x01000500
#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                     24
#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                      0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                  0x01000500
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                   16
#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                    0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                  0x01000500
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                    0x01000500
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                     0
#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 
#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL                    0x01001800
#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT                     24
#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK                      0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL                  0x01001800
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT                   16
#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK                    0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL                  0x01001800
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL                    0x01001800
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT                     0
#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* Turing this off will shut down the OCM, some parts of the APM, and preve
    * nt transactions going from the FPD to the LPD and could lead to system h
    * ang
*/
#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 
#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK 
#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                      0x03000600
#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                       24
#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                        0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                    0x03000600
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                     8
#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                      0x00003F00U

/*
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 
#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                      0x03000600
#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                       0
#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                        0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 
#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                  0x00001500
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                   24
#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                    0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                0x00001500
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                 8
#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                  0x00003F00U

/*
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                  0x00001500
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                   0
#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                    0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT 
#undef CRL_APB_PCAP_CTRL_CLKACT_MASK 
#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                        0x00001500
#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                         24
#define CRL_APB_PCAP_CTRL_CLKACT_MASK                          0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK 
#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                      0x00001500
#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                       8
#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                        0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK 
#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                        0x00001500
#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                         0
#define CRL_APB_PCAP_CTRL_SRCSEL_MASK                          0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 
#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                  0x01000500
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                   24
#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                    0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                0x01000500
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                 8
#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                  0x00003F00U

/*
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                  0x01000500
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                   0
#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                    0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 
#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                   0x01001800
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                    24
#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                     0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                 0x01001800
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                  8
#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                   0x00003F00U

/*
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                   0x01001800
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                    0
#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                     0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 
#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 
#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                     0x01002000
#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                      24
#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                       0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                   0x01002000
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                    8
#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                     0x00003F00U

/*
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                     0x01002000
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                      0
#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                       0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 
#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                    0x00002000
#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                     24
#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                      0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                  0x00002000
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                    0x00002000
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                     0
#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK 
#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL                     0x00052000
#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT                      24
#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK                       0x01000000U

/*
* 6 bit divider
*/
#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL                   0x00052000
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT                    16
#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK                     0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL                   0x00052000
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT                    8
#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK                     0x00003F00U

/*
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL                     0x00052000
#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT                      0
#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK                       0x00000007U

/*
* 6 bit divider
*/
#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 
#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                   0x01001800
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                    16
#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                     0x003F0000U

/*
* 6 bit divider
*/
#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                   0x01001800
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                    8
#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                     0x00003F00U

/*
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
    *  usually an issue, but designers must be aware.)
*/
#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                     0x01001800
#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                      0
#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                       0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 
#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                     0x01001800
#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                      24
#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                       0x01000000U

/*
* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
    *  of the old clock and 4 cycles of the new clock. This is not usually an
    * issue, but designers must be aware.)
*/
#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                     0x00000000
#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                      0
#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                       0x00000007U

/*
* 6 bit divider
*/
#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 
#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL             0x00001800
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT              8
#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK               0x00003F00U

/*
* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
    *  only be toggled after 4 cycles of the old clock and 4 cycles of the new
    *  clock. This is not usually an issue, but designers must be aware.)
*/
#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 
#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 
#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL               0x00001800
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                0
#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                 0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 
#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 
#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL               0x00001800
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                24
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                 0x01000000U

/*
* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog
    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
    *  is not usually an issue, but designers must be aware.)
*/
#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 
#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL                    0x01001600
#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT                     0
#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 
#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK 
#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL                    0x01001600
#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT                     24
#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK                      0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL                  0x01001600
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only
    *  be toggled after 4 cycles of the old clock and 4 cycles of the new cloc
    * k. This is not usually an issue, but designers must be aware.)
*/
#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL                    0x00001500
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT                     0
#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 
#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 
#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL                    0x00001500
#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT                     24
#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK                      0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL                  0x00001500
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 6 bit divider
*/
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL              0x01002300
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT               16
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                0x003F0000U

/*
* 6 bit divider
*/
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL              0x01002300
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT               8
#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                0x00003F00U

/*
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
    * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
    * les of the new clock. This is not usually an issue, but designers must b
    * e aware.)
*/
#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                0x01002300
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                 0
#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                  0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 
#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                0x01002300
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                 24
#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                  0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL              0x01032300
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT               16
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                0x003F0000U

/*
* 6 bit divider
*/
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL              0x01032300
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT               8
#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                0x00003F00U

/*
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
    * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
    * les of the new clock. This is not usually an issue, but designers must b
    * e aware.)
*/
#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                0x01032300
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                 0
#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                  0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 
#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                0x01032300
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                 24
#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                  0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                0x01203200
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                 16
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                  0x003F0000U

/*
* 6 bit divider
*/
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                0x01203200
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                 8
#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                  0x00003F00U

/*
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
    * led after 4 cycles of the old clock and 4 cycles of the new clock. This
    * is not usually an issue, but designers must be aware.)
*/
#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                  0x01203200
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                   0
#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                    0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 
#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                  0x01203200
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                   24
#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                    0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK 
#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                      0x03000400
#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                       8
#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                        0x00003F00U

/*
* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft
    * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
    * usually an issue, but designers must be aware.)
*/
#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK 
#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                        0x03000400
#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                         0
#define CRF_APB_ACPU_CTRL_SRCSEL_MASK                          0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock. For the half spee
    * d APU Clock
*/
#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 
#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 
#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                   0x03000400
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                    25
#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                     0x02000000U

/*
* Clock active signal. Switch to 0 to disable the clock. For the full spee
    * d ACPUX Clock. This will shut off the high speed clock to the entire APU
*/
#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 
#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 
#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                   0x03000400
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                    24
#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                     0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                   0x01002500
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                    8
#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                     0x00003F00U

/*
* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
    *  is not usually an issue, but designers must be aware.)
*/
#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                     0x01002500
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                      0
#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                       0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 
#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 
#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                     0x01002500
#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                      24
#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                       0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK 
#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                       0x01000500
#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                        8
#define CRF_APB_DDR_CTRL_DIVISOR0_MASK                         0x00003F00U

/*
* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles
    * of the old clock and 4 cycles of the new clock. This is not usually an i
    * ssue, but designers must be aware.)
*/
#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_DDR_CTRL_SRCSEL_MASK 
#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                         0x01000500
#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                          0
#define CRF_APB_DDR_CTRL_SRCSEL_MASK                           0x00000007U

/*
* 6 bit divider
*/
#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                   0x00001500
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                    8
#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                     0x00003F00U

/*
* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog
    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
    *  is not usually an issue, but designers must be aware.)
*/
#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 
#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                     0x00001500
#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                      0
#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                       0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock, which will stop c
    * lock for GPU (and both Pixel Processors).
*/
#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 
#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK 
#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                     0x00001500
#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                      24
#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                       0x01000000U

/*
* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
    * k only to this Pixel Processor
*/
#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 
#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 
#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                 0x00001500
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                  25
#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                   0x02000000U

/*
* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
    * k only to this Pixel Processor
*/
#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 
#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 
#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                 0x00001500
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                  26
#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                   0x04000000U

/*
* 6 bit divider
*/
#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                  0x01000500
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                   8
#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U

/*
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
    * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
    * usually an issue, but designers must be aware.)
*/
#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                    0x01000500
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                     0
#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                      0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 
#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 
#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                    0x01000500
#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                     24
#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                      0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                 0x01000500
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                  8
#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                   0x00003F00U

/*
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
    * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
    * usually an issue, but designers must be aware.)
*/
#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                   0x01000500
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                    0
#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                     0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 
#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                   0x01000500
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                    24
#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                     0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                0x01000400
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                 8
#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                  0x00003F00U

/*
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
    * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
    * usually an issue, but designers must be aware.)
*/
#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                  0x01000400
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                   0
#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                    0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 
#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                  0x01000400
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                   24
#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                    0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL               0x01000800
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                8
#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                 0x00003F00U

/*
* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog
    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
    *  is not usually an issue, but designers must be aware.)
*/
#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                 0x01000800
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                  0
#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                   0x00000007U

/*
* Clock active signal. Switch to 0 to disable the clock
*/
#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 
#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 
#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                 0x01000800
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                  24
#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                   0x01000000U

/*
* 6 bit divider
*/
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 
#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                 0x00000A00
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                  8
#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                   0x00003F00U

/*
* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
    *  is not usually an issue, but designers must be aware.)
*/
#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 
#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 
#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                   0x00000A00
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                    0
#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                     0x00000007U

/*
* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se
    * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
    *  clock for the APB interface of TTC0
*/
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL               0x00000000
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT                0
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK                 0x00000003U

/*
* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se
    * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
    *  clock for the APB interface of TTC1
*/
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL               0x00000000
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT                2
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK                 0x0000000CU

/*
* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se
    * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
    *  clock for the APB interface of TTC2
*/
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL               0x00000000
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT                4
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK                 0x00000030U

/*
* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se
    * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
    *  clock for the APB interface of TTC3
*/
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 
#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL               0x00000000
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT                6
#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK                 0x000000C0U

/*
* System watchdog timer clock source selection: 0: Internal APB clock 1: E
    * xternal (PL clock via EMIO or Pinout clock via MIO)
*/
#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 
#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                     0x00000000
#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT                      0
#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK                       0x00000001U

/*
* System watchdog timer clock source selection: 0: internal clock APB cloc
    * k 1: external clock from PL via EMIO, or from pinout via MIO
*/
#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 
#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                     0x00000000
#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT                      0
#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK                       0x00000001U

/*
* System watchdog timer clock source selection: 0: internal clock APB cloc
    * k 1: external clock pss_ref_clk
*/
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 
#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL              0x00000000
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT               0
#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK                0x00000001U
#undef CRF_APB_RST_DDR_SS_OFFSET 
#define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
#undef DDRC_MSTR_OFFSET 
#define DDRC_MSTR_OFFSET                                                           0XFD070000
#undef DDRC_MRCTRL0_OFFSET 
#define DDRC_MRCTRL0_OFFSET                                                        0XFD070010
#undef DDRC_DERATEEN_OFFSET 
#define DDRC_DERATEEN_OFFSET                                                       0XFD070020
#undef DDRC_DERATEINT_OFFSET 
#define DDRC_DERATEINT_OFFSET                                                      0XFD070024
#undef DDRC_PWRCTL_OFFSET 
#define DDRC_PWRCTL_OFFSET                                                         0XFD070030
#undef DDRC_PWRTMG_OFFSET 
#define DDRC_PWRTMG_OFFSET                                                         0XFD070034
#undef DDRC_RFSHCTL0_OFFSET 
#define DDRC_RFSHCTL0_OFFSET                                                       0XFD070050
#undef DDRC_RFSHCTL1_OFFSET 
#define DDRC_RFSHCTL1_OFFSET                                                       0XFD070054
#undef DDRC_RFSHCTL3_OFFSET 
#define DDRC_RFSHCTL3_OFFSET                                                       0XFD070060
#undef DDRC_RFSHTMG_OFFSET 
#define DDRC_RFSHTMG_OFFSET                                                        0XFD070064
#undef DDRC_ECCCFG0_OFFSET 
#define DDRC_ECCCFG0_OFFSET                                                        0XFD070070
#undef DDRC_ECCCFG1_OFFSET 
#define DDRC_ECCCFG1_OFFSET                                                        0XFD070074
#undef DDRC_CRCPARCTL1_OFFSET 
#define DDRC_CRCPARCTL1_OFFSET                                                     0XFD0700C4
#undef DDRC_CRCPARCTL2_OFFSET 
#define DDRC_CRCPARCTL2_OFFSET                                                     0XFD0700C8
#undef DDRC_INIT0_OFFSET 
#define DDRC_INIT0_OFFSET                                                          0XFD0700D0
#undef DDRC_INIT1_OFFSET 
#define DDRC_INIT1_OFFSET                                                          0XFD0700D4
#undef DDRC_INIT2_OFFSET 
#define DDRC_INIT2_OFFSET                                                          0XFD0700D8
#undef DDRC_INIT3_OFFSET 
#define DDRC_INIT3_OFFSET                                                          0XFD0700DC
#undef DDRC_INIT4_OFFSET 
#define DDRC_INIT4_OFFSET                                                          0XFD0700E0
#undef DDRC_INIT5_OFFSET 
#define DDRC_INIT5_OFFSET                                                          0XFD0700E4
#undef DDRC_INIT6_OFFSET 
#define DDRC_INIT6_OFFSET                                                          0XFD0700E8
#undef DDRC_INIT7_OFFSET 
#define DDRC_INIT7_OFFSET                                                          0XFD0700EC
#undef DDRC_DIMMCTL_OFFSET 
#define DDRC_DIMMCTL_OFFSET                                                        0XFD0700F0
#undef DDRC_RANKCTL_OFFSET 
#define DDRC_RANKCTL_OFFSET                                                        0XFD0700F4
#undef DDRC_DRAMTMG0_OFFSET 
#define DDRC_DRAMTMG0_OFFSET                                                       0XFD070100
#undef DDRC_DRAMTMG1_OFFSET 
#define DDRC_DRAMTMG1_OFFSET                                                       0XFD070104
#undef DDRC_DRAMTMG2_OFFSET 
#define DDRC_DRAMTMG2_OFFSET                                                       0XFD070108
#undef DDRC_DRAMTMG3_OFFSET 
#define DDRC_DRAMTMG3_OFFSET                                                       0XFD07010C
#undef DDRC_DRAMTMG4_OFFSET 
#define DDRC_DRAMTMG4_OFFSET                                                       0XFD070110
#undef DDRC_DRAMTMG5_OFFSET 
#define DDRC_DRAMTMG5_OFFSET                                                       0XFD070114
#undef DDRC_DRAMTMG6_OFFSET 
#define DDRC_DRAMTMG6_OFFSET                                                       0XFD070118
#undef DDRC_DRAMTMG7_OFFSET 
#define DDRC_DRAMTMG7_OFFSET                                                       0XFD07011C
#undef DDRC_DRAMTMG8_OFFSET 
#define DDRC_DRAMTMG8_OFFSET                                                       0XFD070120
#undef DDRC_DRAMTMG9_OFFSET 
#define DDRC_DRAMTMG9_OFFSET                                                       0XFD070124
#undef DDRC_DRAMTMG11_OFFSET 
#define DDRC_DRAMTMG11_OFFSET                                                      0XFD07012C
#undef DDRC_DRAMTMG12_OFFSET 
#define DDRC_DRAMTMG12_OFFSET                                                      0XFD070130
#undef DDRC_ZQCTL0_OFFSET 
#define DDRC_ZQCTL0_OFFSET                                                         0XFD070180
#undef DDRC_ZQCTL1_OFFSET 
#define DDRC_ZQCTL1_OFFSET                                                         0XFD070184
#undef DDRC_DFITMG0_OFFSET 
#define DDRC_DFITMG0_OFFSET                                                        0XFD070190
#undef DDRC_DFITMG1_OFFSET 
#define DDRC_DFITMG1_OFFSET                                                        0XFD070194
#undef DDRC_DFILPCFG0_OFFSET 
#define DDRC_DFILPCFG0_OFFSET                                                      0XFD070198
#undef DDRC_DFILPCFG1_OFFSET 
#define DDRC_DFILPCFG1_OFFSET                                                      0XFD07019C
#undef DDRC_DFIUPD0_OFFSET 
#define DDRC_DFIUPD0_OFFSET                                                        0XFD0701A0
#undef DDRC_DFIUPD1_OFFSET 
#define DDRC_DFIUPD1_OFFSET                                                        0XFD0701A4
#undef DDRC_DFIMISC_OFFSET 
#define DDRC_DFIMISC_OFFSET                                                        0XFD0701B0
#undef DDRC_DFITMG2_OFFSET 
#define DDRC_DFITMG2_OFFSET                                                        0XFD0701B4
#undef DDRC_DBICTL_OFFSET 
#define DDRC_DBICTL_OFFSET                                                         0XFD0701C0
#undef DDRC_ADDRMAP0_OFFSET 
#define DDRC_ADDRMAP0_OFFSET                                                       0XFD070200
#undef DDRC_ADDRMAP1_OFFSET 
#define DDRC_ADDRMAP1_OFFSET                                                       0XFD070204
#undef DDRC_ADDRMAP2_OFFSET 
#define DDRC_ADDRMAP2_OFFSET                                                       0XFD070208
#undef DDRC_ADDRMAP3_OFFSET 
#define DDRC_ADDRMAP3_OFFSET                                                       0XFD07020C
#undef DDRC_ADDRMAP4_OFFSET 
#define DDRC_ADDRMAP4_OFFSET                                                       0XFD070210
#undef DDRC_ADDRMAP5_OFFSET 
#define DDRC_ADDRMAP5_OFFSET                                                       0XFD070214
#undef DDRC_ADDRMAP6_OFFSET 
#define DDRC_ADDRMAP6_OFFSET                                                       0XFD070218
#undef DDRC_ADDRMAP7_OFFSET 
#define DDRC_ADDRMAP7_OFFSET                                                       0XFD07021C
#undef DDRC_ADDRMAP8_OFFSET 
#define DDRC_ADDRMAP8_OFFSET                                                       0XFD070220
#undef DDRC_ADDRMAP9_OFFSET 
#define DDRC_ADDRMAP9_OFFSET                                                       0XFD070224
#undef DDRC_ADDRMAP10_OFFSET 
#define DDRC_ADDRMAP10_OFFSET                                                      0XFD070228
#undef DDRC_ADDRMAP11_OFFSET 
#define DDRC_ADDRMAP11_OFFSET                                                      0XFD07022C
#undef DDRC_ODTCFG_OFFSET 
#define DDRC_ODTCFG_OFFSET                                                         0XFD070240
#undef DDRC_ODTMAP_OFFSET 
#define DDRC_ODTMAP_OFFSET                                                         0XFD070244
#undef DDRC_SCHED_OFFSET 
#define DDRC_SCHED_OFFSET                                                          0XFD070250
#undef DDRC_PERFLPR1_OFFSET 
#define DDRC_PERFLPR1_OFFSET                                                       0XFD070264
#undef DDRC_PERFWR1_OFFSET 
#define DDRC_PERFWR1_OFFSET                                                        0XFD07026C
#undef DDRC_DQMAP0_OFFSET 
#define DDRC_DQMAP0_OFFSET                                                         0XFD070280
#undef DDRC_DQMAP1_OFFSET 
#define DDRC_DQMAP1_OFFSET                                                         0XFD070284
#undef DDRC_DQMAP2_OFFSET 
#define DDRC_DQMAP2_OFFSET                                                         0XFD070288
#undef DDRC_DQMAP3_OFFSET 
#define DDRC_DQMAP3_OFFSET                                                         0XFD07028C
#undef DDRC_DQMAP4_OFFSET 
#define DDRC_DQMAP4_OFFSET                                                         0XFD070290
#undef DDRC_DQMAP5_OFFSET 
#define DDRC_DQMAP5_OFFSET                                                         0XFD070294
#undef DDRC_DBG0_OFFSET 
#define DDRC_DBG0_OFFSET                                                           0XFD070300
#undef DDRC_DBGCMD_OFFSET 
#define DDRC_DBGCMD_OFFSET                                                         0XFD07030C
#undef DDRC_SWCTL_OFFSET 
#define DDRC_SWCTL_OFFSET                                                          0XFD070320
#undef DDRC_PCCFG_OFFSET 
#define DDRC_PCCFG_OFFSET                                                          0XFD070400
#undef DDRC_PCFGR_0_OFFSET 
#define DDRC_PCFGR_0_OFFSET                                                        0XFD070404
#undef DDRC_PCFGW_0_OFFSET 
#define DDRC_PCFGW_0_OFFSET                                                        0XFD070408
#undef DDRC_PCTRL_0_OFFSET 
#define DDRC_PCTRL_0_OFFSET                                                        0XFD070490
#undef DDRC_PCFGQOS0_0_OFFSET 
#define DDRC_PCFGQOS0_0_OFFSET                                                     0XFD070494
#undef DDRC_PCFGQOS1_0_OFFSET 
#define DDRC_PCFGQOS1_0_OFFSET                                                     0XFD070498
#undef DDRC_PCFGR_1_OFFSET 
#define DDRC_PCFGR_1_OFFSET                                                        0XFD0704B4
#undef DDRC_PCFGW_1_OFFSET 
#define DDRC_PCFGW_1_OFFSET                                                        0XFD0704B8
#undef DDRC_PCTRL_1_OFFSET 
#define DDRC_PCTRL_1_OFFSET                                                        0XFD070540
#undef DDRC_PCFGQOS0_1_OFFSET 
#define DDRC_PCFGQOS0_1_OFFSET                                                     0XFD070544
#undef DDRC_PCFGQOS1_1_OFFSET 
#define DDRC_PCFGQOS1_1_OFFSET                                                     0XFD070548
#undef DDRC_PCFGR_2_OFFSET 
#define DDRC_PCFGR_2_OFFSET                                                        0XFD070564
#undef DDRC_PCFGW_2_OFFSET 
#define DDRC_PCFGW_2_OFFSET                                                        0XFD070568
#undef DDRC_PCTRL_2_OFFSET 
#define DDRC_PCTRL_2_OFFSET                                                        0XFD0705F0
#undef DDRC_PCFGQOS0_2_OFFSET 
#define DDRC_PCFGQOS0_2_OFFSET                                                     0XFD0705F4
#undef DDRC_PCFGQOS1_2_OFFSET 
#define DDRC_PCFGQOS1_2_OFFSET                                                     0XFD0705F8
#undef DDRC_PCFGR_3_OFFSET 
#define DDRC_PCFGR_3_OFFSET                                                        0XFD070614
#undef DDRC_PCFGW_3_OFFSET 
#define DDRC_PCFGW_3_OFFSET                                                        0XFD070618
#undef DDRC_PCTRL_3_OFFSET 
#define DDRC_PCTRL_3_OFFSET                                                        0XFD0706A0
#undef DDRC_PCFGQOS0_3_OFFSET 
#define DDRC_PCFGQOS0_3_OFFSET                                                     0XFD0706A4
#undef DDRC_PCFGQOS1_3_OFFSET 
#define DDRC_PCFGQOS1_3_OFFSET                                                     0XFD0706A8
#undef DDRC_PCFGWQOS0_3_OFFSET 
#define DDRC_PCFGWQOS0_3_OFFSET                                                    0XFD0706AC
#undef DDRC_PCFGWQOS1_3_OFFSET 
#define DDRC_PCFGWQOS1_3_OFFSET                                                    0XFD0706B0
#undef DDRC_PCFGR_4_OFFSET 
#define DDRC_PCFGR_4_OFFSET                                                        0XFD0706C4
#undef DDRC_PCFGW_4_OFFSET 
#define DDRC_PCFGW_4_OFFSET                                                        0XFD0706C8
#undef DDRC_PCTRL_4_OFFSET 
#define DDRC_PCTRL_4_OFFSET                                                        0XFD070750
#undef DDRC_PCFGQOS0_4_OFFSET 
#define DDRC_PCFGQOS0_4_OFFSET                                                     0XFD070754
#undef DDRC_PCFGQOS1_4_OFFSET 
#define DDRC_PCFGQOS1_4_OFFSET                                                     0XFD070758
#undef DDRC_PCFGWQOS0_4_OFFSET 
#define DDRC_PCFGWQOS0_4_OFFSET                                                    0XFD07075C
#undef DDRC_PCFGWQOS1_4_OFFSET 
#define DDRC_PCFGWQOS1_4_OFFSET                                                    0XFD070760
#undef DDRC_PCFGR_5_OFFSET 
#define DDRC_PCFGR_5_OFFSET                                                        0XFD070774
#undef DDRC_PCFGW_5_OFFSET 
#define DDRC_PCFGW_5_OFFSET                                                        0XFD070778
#undef DDRC_PCTRL_5_OFFSET 
#define DDRC_PCTRL_5_OFFSET                                                        0XFD070800
#undef DDRC_PCFGQOS0_5_OFFSET 
#define DDRC_PCFGQOS0_5_OFFSET                                                     0XFD070804
#undef DDRC_PCFGQOS1_5_OFFSET 
#define DDRC_PCFGQOS1_5_OFFSET                                                     0XFD070808
#undef DDRC_PCFGWQOS0_5_OFFSET 
#define DDRC_PCFGWQOS0_5_OFFSET                                                    0XFD07080C
#undef DDRC_PCFGWQOS1_5_OFFSET 
#define DDRC_PCFGWQOS1_5_OFFSET                                                    0XFD070810
#undef DDRC_SARBASE0_OFFSET 
#define DDRC_SARBASE0_OFFSET                                                       0XFD070F04
#undef DDRC_SARSIZE0_OFFSET 
#define DDRC_SARSIZE0_OFFSET                                                       0XFD070F08
#undef DDRC_SARBASE1_OFFSET 
#define DDRC_SARBASE1_OFFSET                                                       0XFD070F0C
#undef DDRC_SARSIZE1_OFFSET 
#define DDRC_SARSIZE1_OFFSET                                                       0XFD070F10
#undef DDRC_DFITMG0_SHADOW_OFFSET 
#define DDRC_DFITMG0_SHADOW_OFFSET                                                 0XFD072190
#undef CRF_APB_RST_DDR_SS_OFFSET 
#define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
#undef DDR_PHY_PGCR0_OFFSET 
#define DDR_PHY_PGCR0_OFFSET                                                       0XFD080010
#undef DDR_PHY_PGCR2_OFFSET 
#define DDR_PHY_PGCR2_OFFSET                                                       0XFD080018
#undef DDR_PHY_PGCR3_OFFSET 
#define DDR_PHY_PGCR3_OFFSET                                                       0XFD08001C
#undef DDR_PHY_PGCR5_OFFSET 
#define DDR_PHY_PGCR5_OFFSET                                                       0XFD080024
#undef DDR_PHY_PTR0_OFFSET 
#define DDR_PHY_PTR0_OFFSET                                                        0XFD080040
#undef DDR_PHY_PTR1_OFFSET 
#define DDR_PHY_PTR1_OFFSET                                                        0XFD080044
#undef DDR_PHY_PLLCR0_OFFSET 
#define DDR_PHY_PLLCR0_OFFSET                                                      0XFD080068
#undef DDR_PHY_DSGCR_OFFSET 
#define DDR_PHY_DSGCR_OFFSET                                                       0XFD080090
#undef DDR_PHY_GPR0_OFFSET 
#define DDR_PHY_GPR0_OFFSET                                                        0XFD0800C0
#undef DDR_PHY_DCR_OFFSET 
#define DDR_PHY_DCR_OFFSET                                                         0XFD080100
#undef DDR_PHY_DTPR0_OFFSET 
#define DDR_PHY_DTPR0_OFFSET                                                       0XFD080110
#undef DDR_PHY_DTPR1_OFFSET 
#define DDR_PHY_DTPR1_OFFSET                                                       0XFD080114
#undef DDR_PHY_DTPR2_OFFSET 
#define DDR_PHY_DTPR2_OFFSET                                                       0XFD080118
#undef DDR_PHY_DTPR3_OFFSET 
#define DDR_PHY_DTPR3_OFFSET                                                       0XFD08011C
#undef DDR_PHY_DTPR4_OFFSET 
#define DDR_PHY_DTPR4_OFFSET                                                       0XFD080120
#undef DDR_PHY_DTPR5_OFFSET 
#define DDR_PHY_DTPR5_OFFSET                                                       0XFD080124
#undef DDR_PHY_DTPR6_OFFSET 
#define DDR_PHY_DTPR6_OFFSET                                                       0XFD080128
#undef DDR_PHY_RDIMMGCR0_OFFSET 
#define DDR_PHY_RDIMMGCR0_OFFSET                                                   0XFD080140
#undef DDR_PHY_RDIMMGCR1_OFFSET 
#define DDR_PHY_RDIMMGCR1_OFFSET                                                   0XFD080144
#undef DDR_PHY_RDIMMCR0_OFFSET 
#define DDR_PHY_RDIMMCR0_OFFSET                                                    0XFD080150
#undef DDR_PHY_RDIMMCR1_OFFSET 
#define DDR_PHY_RDIMMCR1_OFFSET                                                    0XFD080154
#undef DDR_PHY_MR0_OFFSET 
#define DDR_PHY_MR0_OFFSET                                                         0XFD080180
#undef DDR_PHY_MR1_OFFSET 
#define DDR_PHY_MR1_OFFSET                                                         0XFD080184
#undef DDR_PHY_MR2_OFFSET 
#define DDR_PHY_MR2_OFFSET                                                         0XFD080188
#undef DDR_PHY_MR3_OFFSET 
#define DDR_PHY_MR3_OFFSET                                                         0XFD08018C
#undef DDR_PHY_MR4_OFFSET 
#define DDR_PHY_MR4_OFFSET                                                         0XFD080190
#undef DDR_PHY_MR5_OFFSET 
#define DDR_PHY_MR5_OFFSET                                                         0XFD080194
#undef DDR_PHY_MR6_OFFSET 
#define DDR_PHY_MR6_OFFSET                                                         0XFD080198
#undef DDR_PHY_MR11_OFFSET 
#define DDR_PHY_MR11_OFFSET                                                        0XFD0801AC
#undef DDR_PHY_MR12_OFFSET 
#define DDR_PHY_MR12_OFFSET                                                        0XFD0801B0
#undef DDR_PHY_MR13_OFFSET 
#define DDR_PHY_MR13_OFFSET                                                        0XFD0801B4
#undef DDR_PHY_MR14_OFFSET 
#define DDR_PHY_MR14_OFFSET                                                        0XFD0801B8
#undef DDR_PHY_MR22_OFFSET 
#define DDR_PHY_MR22_OFFSET                                                        0XFD0801D8
#undef DDR_PHY_DTCR0_OFFSET 
#define DDR_PHY_DTCR0_OFFSET                                                       0XFD080200
#undef DDR_PHY_DTCR1_OFFSET 
#define DDR_PHY_DTCR1_OFFSET                                                       0XFD080204
#undef DDR_PHY_CATR0_OFFSET 
#define DDR_PHY_CATR0_OFFSET                                                       0XFD080240
#undef DDR_PHY_DQSDR0_OFFSET 
#define DDR_PHY_DQSDR0_OFFSET                                                      0XFD080250
#undef DDR_PHY_BISTLSR_OFFSET 
#define DDR_PHY_BISTLSR_OFFSET                                                     0XFD080414
#undef DDR_PHY_RIOCR5_OFFSET 
#define DDR_PHY_RIOCR5_OFFSET                                                      0XFD0804F4
#undef DDR_PHY_ACIOCR0_OFFSET 
#define DDR_PHY_ACIOCR0_OFFSET                                                     0XFD080500
#undef DDR_PHY_ACIOCR2_OFFSET 
#define DDR_PHY_ACIOCR2_OFFSET                                                     0XFD080508
#undef DDR_PHY_ACIOCR3_OFFSET 
#define DDR_PHY_ACIOCR3_OFFSET                                                     0XFD08050C
#undef DDR_PHY_ACIOCR4_OFFSET 
#define DDR_PHY_ACIOCR4_OFFSET                                                     0XFD080510
#undef DDR_PHY_IOVCR0_OFFSET 
#define DDR_PHY_IOVCR0_OFFSET                                                      0XFD080520
#undef DDR_PHY_VTCR0_OFFSET 
#define DDR_PHY_VTCR0_OFFSET                                                       0XFD080528
#undef DDR_PHY_VTCR1_OFFSET 
#define DDR_PHY_VTCR1_OFFSET                                                       0XFD08052C
#undef DDR_PHY_ACBDLR1_OFFSET 
#define DDR_PHY_ACBDLR1_OFFSET                                                     0XFD080544
#undef DDR_PHY_ACBDLR2_OFFSET 
#define DDR_PHY_ACBDLR2_OFFSET                                                     0XFD080548
#undef DDR_PHY_ACBDLR6_OFFSET 
#define DDR_PHY_ACBDLR6_OFFSET                                                     0XFD080558
#undef DDR_PHY_ACBDLR7_OFFSET 
#define DDR_PHY_ACBDLR7_OFFSET                                                     0XFD08055C
#undef DDR_PHY_ACBDLR8_OFFSET 
#define DDR_PHY_ACBDLR8_OFFSET                                                     0XFD080560
#undef DDR_PHY_ACBDLR9_OFFSET 
#define DDR_PHY_ACBDLR9_OFFSET                                                     0XFD080564
#undef DDR_PHY_ZQCR_OFFSET 
#define DDR_PHY_ZQCR_OFFSET                                                        0XFD080680
#undef DDR_PHY_ZQ0PR0_OFFSET 
#define DDR_PHY_ZQ0PR0_OFFSET                                                      0XFD080684
#undef DDR_PHY_ZQ0OR0_OFFSET 
#define DDR_PHY_ZQ0OR0_OFFSET                                                      0XFD080694
#undef DDR_PHY_ZQ0OR1_OFFSET 
#define DDR_PHY_ZQ0OR1_OFFSET                                                      0XFD080698
#undef DDR_PHY_ZQ1PR0_OFFSET 
#define DDR_PHY_ZQ1PR0_OFFSET                                                      0XFD0806A4
#undef DDR_PHY_DX0GCR0_OFFSET 
#define DDR_PHY_DX0GCR0_OFFSET                                                     0XFD080700
#undef DDR_PHY_DX0GCR4_OFFSET 
#define DDR_PHY_DX0GCR4_OFFSET                                                     0XFD080710
#undef DDR_PHY_DX0GCR5_OFFSET 
#define DDR_PHY_DX0GCR5_OFFSET                                                     0XFD080714
#undef DDR_PHY_DX0GCR6_OFFSET 
#define DDR_PHY_DX0GCR6_OFFSET                                                     0XFD080718
#undef DDR_PHY_DX1GCR0_OFFSET 
#define DDR_PHY_DX1GCR0_OFFSET                                                     0XFD080800
#undef DDR_PHY_DX1GCR4_OFFSET 
#define DDR_PHY_DX1GCR4_OFFSET                                                     0XFD080810
#undef DDR_PHY_DX1GCR5_OFFSET 
#define DDR_PHY_DX1GCR5_OFFSET                                                     0XFD080814
#undef DDR_PHY_DX1GCR6_OFFSET 
#define DDR_PHY_DX1GCR6_OFFSET                                                     0XFD080818
#undef DDR_PHY_DX2GCR0_OFFSET 
#define DDR_PHY_DX2GCR0_OFFSET                                                     0XFD080900
#undef DDR_PHY_DX2GCR1_OFFSET 
#define DDR_PHY_DX2GCR1_OFFSET                                                     0XFD080904
#undef DDR_PHY_DX2GCR4_OFFSET 
#define DDR_PHY_DX2GCR4_OFFSET                                                     0XFD080910
#undef DDR_PHY_DX2GCR5_OFFSET 
#define DDR_PHY_DX2GCR5_OFFSET                                                     0XFD080914
#undef DDR_PHY_DX2GCR6_OFFSET 
#define DDR_PHY_DX2GCR6_OFFSET                                                     0XFD080918
#undef DDR_PHY_DX3GCR0_OFFSET 
#define DDR_PHY_DX3GCR0_OFFSET                                                     0XFD080A00
#undef DDR_PHY_DX3GCR1_OFFSET 
#define DDR_PHY_DX3GCR1_OFFSET                                                     0XFD080A04
#undef DDR_PHY_DX3GCR4_OFFSET 
#define DDR_PHY_DX3GCR4_OFFSET                                                     0XFD080A10
#undef DDR_PHY_DX3GCR5_OFFSET 
#define DDR_PHY_DX3GCR5_OFFSET                                                     0XFD080A14
#undef DDR_PHY_DX3GCR6_OFFSET 
#define DDR_PHY_DX3GCR6_OFFSET                                                     0XFD080A18
#undef DDR_PHY_DX4GCR0_OFFSET 
#define DDR_PHY_DX4GCR0_OFFSET                                                     0XFD080B00
#undef DDR_PHY_DX4GCR1_OFFSET 
#define DDR_PHY_DX4GCR1_OFFSET                                                     0XFD080B04
#undef DDR_PHY_DX4GCR4_OFFSET 
#define DDR_PHY_DX4GCR4_OFFSET                                                     0XFD080B10
#undef DDR_PHY_DX4GCR5_OFFSET 
#define DDR_PHY_DX4GCR5_OFFSET                                                     0XFD080B14
#undef DDR_PHY_DX4GCR6_OFFSET 
#define DDR_PHY_DX4GCR6_OFFSET                                                     0XFD080B18
#undef DDR_PHY_DX5GCR0_OFFSET 
#define DDR_PHY_DX5GCR0_OFFSET                                                     0XFD080C00
#undef DDR_PHY_DX5GCR1_OFFSET 
#define DDR_PHY_DX5GCR1_OFFSET                                                     0XFD080C04
#undef DDR_PHY_DX5GCR4_OFFSET 
#define DDR_PHY_DX5GCR4_OFFSET                                                     0XFD080C10
#undef DDR_PHY_DX5GCR5_OFFSET 
#define DDR_PHY_DX5GCR5_OFFSET                                                     0XFD080C14
#undef DDR_PHY_DX5GCR6_OFFSET 
#define DDR_PHY_DX5GCR6_OFFSET                                                     0XFD080C18
#undef DDR_PHY_DX6GCR0_OFFSET 
#define DDR_PHY_DX6GCR0_OFFSET                                                     0XFD080D00
#undef DDR_PHY_DX6GCR1_OFFSET 
#define DDR_PHY_DX6GCR1_OFFSET                                                     0XFD080D04
#undef DDR_PHY_DX6GCR4_OFFSET 
#define DDR_PHY_DX6GCR4_OFFSET                                                     0XFD080D10
#undef DDR_PHY_DX6GCR5_OFFSET 
#define DDR_PHY_DX6GCR5_OFFSET                                                     0XFD080D14
#undef DDR_PHY_DX6GCR6_OFFSET 
#define DDR_PHY_DX6GCR6_OFFSET                                                     0XFD080D18
#undef DDR_PHY_DX7GCR0_OFFSET 
#define DDR_PHY_DX7GCR0_OFFSET                                                     0XFD080E00
#undef DDR_PHY_DX7GCR1_OFFSET 
#define DDR_PHY_DX7GCR1_OFFSET                                                     0XFD080E04
#undef DDR_PHY_DX7GCR4_OFFSET 
#define DDR_PHY_DX7GCR4_OFFSET                                                     0XFD080E10
#undef DDR_PHY_DX7GCR5_OFFSET 
#define DDR_PHY_DX7GCR5_OFFSET                                                     0XFD080E14
#undef DDR_PHY_DX7GCR6_OFFSET 
#define DDR_PHY_DX7GCR6_OFFSET                                                     0XFD080E18
#undef DDR_PHY_DX8GCR0_OFFSET 
#define DDR_PHY_DX8GCR0_OFFSET                                                     0XFD080F00
#undef DDR_PHY_DX8GCR1_OFFSET 
#define DDR_PHY_DX8GCR1_OFFSET                                                     0XFD080F04
#undef DDR_PHY_DX8GCR4_OFFSET 
#define DDR_PHY_DX8GCR4_OFFSET                                                     0XFD080F10
#undef DDR_PHY_DX8GCR5_OFFSET 
#define DDR_PHY_DX8GCR5_OFFSET                                                     0XFD080F14
#undef DDR_PHY_DX8GCR6_OFFSET 
#define DDR_PHY_DX8GCR6_OFFSET                                                     0XFD080F18
#undef DDR_PHY_DX8SL0OSC_OFFSET 
#define DDR_PHY_DX8SL0OSC_OFFSET                                                   0XFD081400
#undef DDR_PHY_DX8SL0PLLCR0_OFFSET 
#define DDR_PHY_DX8SL0PLLCR0_OFFSET                                                0XFD081404
#undef DDR_PHY_DX8SL0DQSCTL_OFFSET 
#define DDR_PHY_DX8SL0DQSCTL_OFFSET                                                0XFD08141C
#undef DDR_PHY_DX8SL0DXCTL2_OFFSET 
#define DDR_PHY_DX8SL0DXCTL2_OFFSET                                                0XFD08142C
#undef DDR_PHY_DX8SL0IOCR_OFFSET 
#define DDR_PHY_DX8SL0IOCR_OFFSET                                                  0XFD081430
#undef DDR_PHY_DX8SL1OSC_OFFSET 
#define DDR_PHY_DX8SL1OSC_OFFSET                                                   0XFD081440
#undef DDR_PHY_DX8SL1PLLCR0_OFFSET 
#define DDR_PHY_DX8SL1PLLCR0_OFFSET                                                0XFD081444
#undef DDR_PHY_DX8SL1DQSCTL_OFFSET 
#define DDR_PHY_DX8SL1DQSCTL_OFFSET                                                0XFD08145C
#undef DDR_PHY_DX8SL1DXCTL2_OFFSET 
#define DDR_PHY_DX8SL1DXCTL2_OFFSET                                                0XFD08146C
#undef DDR_PHY_DX8SL1IOCR_OFFSET 
#define DDR_PHY_DX8SL1IOCR_OFFSET                                                  0XFD081470
#undef DDR_PHY_DX8SL2OSC_OFFSET 
#define DDR_PHY_DX8SL2OSC_OFFSET                                                   0XFD081480
#undef DDR_PHY_DX8SL2PLLCR0_OFFSET 
#define DDR_PHY_DX8SL2PLLCR0_OFFSET                                                0XFD081484
#undef DDR_PHY_DX8SL2DQSCTL_OFFSET 
#define DDR_PHY_DX8SL2DQSCTL_OFFSET                                                0XFD08149C
#undef DDR_PHY_DX8SL2DXCTL2_OFFSET 
#define DDR_PHY_DX8SL2DXCTL2_OFFSET                                                0XFD0814AC
#undef DDR_PHY_DX8SL2IOCR_OFFSET 
#define DDR_PHY_DX8SL2IOCR_OFFSET                                                  0XFD0814B0
#undef DDR_PHY_DX8SL3OSC_OFFSET 
#define DDR_PHY_DX8SL3OSC_OFFSET                                                   0XFD0814C0
#undef DDR_PHY_DX8SL3PLLCR0_OFFSET 
#define DDR_PHY_DX8SL3PLLCR0_OFFSET                                                0XFD0814C4
#undef DDR_PHY_DX8SL3DQSCTL_OFFSET 
#define DDR_PHY_DX8SL3DQSCTL_OFFSET                                                0XFD0814DC
#undef DDR_PHY_DX8SL3DXCTL2_OFFSET 
#define DDR_PHY_DX8SL3DXCTL2_OFFSET                                                0XFD0814EC
#undef DDR_PHY_DX8SL3IOCR_OFFSET 
#define DDR_PHY_DX8SL3IOCR_OFFSET                                                  0XFD0814F0
#undef DDR_PHY_DX8SL4OSC_OFFSET 
#define DDR_PHY_DX8SL4OSC_OFFSET                                                   0XFD081500
#undef DDR_PHY_DX8SL4PLLCR0_OFFSET 
#define DDR_PHY_DX8SL4PLLCR0_OFFSET                                                0XFD081504
#undef DDR_PHY_DX8SL4DQSCTL_OFFSET 
#define DDR_PHY_DX8SL4DQSCTL_OFFSET                                                0XFD08151C
#undef DDR_PHY_DX8SL4DXCTL2_OFFSET 
#define DDR_PHY_DX8SL4DXCTL2_OFFSET                                                0XFD08152C
#undef DDR_PHY_DX8SL4IOCR_OFFSET 
#define DDR_PHY_DX8SL4IOCR_OFFSET                                                  0XFD081530
#undef DDR_PHY_DX8SLBPLLCR0_OFFSET 
#define DDR_PHY_DX8SLBPLLCR0_OFFSET                                                0XFD0817C4
#undef DDR_PHY_DX8SLBDQSCTL_OFFSET 
#define DDR_PHY_DX8SLBDQSCTL_OFFSET                                                0XFD0817DC

/*
* DDR block level reset inside of the DDR Sub System
*/
#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                    0x0000000F
#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                     3
#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                      0x00000008U

/*
* Indicates the configuration of the device used in the system. - 00 - x4
    * device - 01 - x8 device - 10 - x16 device - 11 - x32 device
*/
#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL 
#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT 
#undef DDRC_MSTR_DEVICE_CONFIG_MASK 
#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL                         0x03040001
#define DDRC_MSTR_DEVICE_CONFIG_SHIFT                          30
#define DDRC_MSTR_DEVICE_CONFIG_MASK                           0xC0000000U

/*
* Choose which registers are used. - 0 - Original registers - 1 - Shadow r
    * egisters
*/
#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL 
#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT 
#undef DDRC_MSTR_FREQUENCY_MODE_MASK 
#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL                        0x03040001
#define DDRC_MSTR_FREQUENCY_MODE_SHIFT                         29
#define DDRC_MSTR_FREQUENCY_MODE_MASK                          0x20000000U

/*
* Only present for multi-rank configurations. Each bit represents one rank
    * . For two-rank configurations, only bits[25:24] are present. - 1 - popul
    * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow
    * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others -
    * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
    * k - 0011 - Two ranks - 1111 - Four ranks
*/
#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL 
#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT 
#undef DDRC_MSTR_ACTIVE_RANKS_MASK 
#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL                          0x03040001
#define DDRC_MSTR_ACTIVE_RANKS_SHIFT                           24
#define DDRC_MSTR_ACTIVE_RANKS_MASK                            0x03000000U

/*
* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for
    * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur
    * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other
    * values are reserved. This controls the burst size used to access the SDR
    * AM. This must match the burst length mode register setting in the SDRAM.
    *  (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100)
    * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
    *  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
*/
#undef DDRC_MSTR_BURST_RDWR_DEFVAL 
#undef DDRC_MSTR_BURST_RDWR_SHIFT 
#undef DDRC_MSTR_BURST_RDWR_MASK 
#define DDRC_MSTR_BURST_RDWR_DEFVAL                            0x03040001
#define DDRC_MSTR_BURST_RDWR_SHIFT                             16
#define DDRC_MSTR_BURST_RDWR_MASK                              0x000F0000U

/*
* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low
    * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for
    * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC
    * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
    * s bit must be set to '0'.
*/
#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL 
#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT 
#undef DDRC_MSTR_DLL_OFF_MODE_MASK 
#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL                          0x03040001
#define DDRC_MSTR_DLL_OFF_MODE_SHIFT                           15
#define DDRC_MSTR_DLL_OFF_MODE_MASK                            0x00008000U

/*
* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full
    *  DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter
    * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is
    * only supported when the SDRAM bus width is a multiple of 16, and quarter
    *  bus width mode is only supported when the SDRAM bus width is a multiple
    *  of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
    * th refers to DQ bus width (excluding any ECC width).
*/
#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 
#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 
#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK 
#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL                        0x03040001
#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT                         12
#define DDRC_MSTR_DATA_BUS_WIDTH_MASK                          0x00003000U

/*
* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D
    * RAM in normal mode (1N). This register can be changed, only when the Con
    * troller is in self-refresh mode. This signal must be set the same value
    * as MR3 bit A3. Note: Geardown mode is not supported if the configuration
    *  parameter MEMC_CMD_RTN2IDLE is set
*/
#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL 
#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT 
#undef DDRC_MSTR_GEARDOWN_MODE_MASK 
#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL                         0x03040001
#define DDRC_MSTR_GEARDOWN_MODE_SHIFT                          11
#define DDRC_MSTR_GEARDOWN_MODE_MASK                           0x00000800U

/*
* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin
    * g, all command signals (except chip select) are held for 2 clocks on the
    *  SDRAM bus. Chip select is asserted on the second cycle of the command N
    * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti
    * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
    * s set Note: 2T timing is not supported in DDR4 geardown mode.
*/
#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 
#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 
#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK 
#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL                     0x03040001
#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT                      10
#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK                       0x00000400U

/*
* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci
    * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full
    * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer
    * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is
    *  disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl
    * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
    * , and this bit must be set to '0'
*/
#undef DDRC_MSTR_BURSTCHOP_DEFVAL 
#undef DDRC_MSTR_BURSTCHOP_SHIFT 
#undef DDRC_MSTR_BURSTCHOP_MASK 
#define DDRC_MSTR_BURSTCHOP_DEFVAL                             0x03040001
#define DDRC_MSTR_BURSTCHOP_SHIFT                              9
#define DDRC_MSTR_BURSTCHOP_MASK                               0x00000200U

/*
* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
    * evice in use Present only in designs configured to support LPDDR4.
*/
#undef DDRC_MSTR_LPDDR4_DEFVAL 
#undef DDRC_MSTR_LPDDR4_SHIFT 
#undef DDRC_MSTR_LPDDR4_MASK 
#define DDRC_MSTR_LPDDR4_DEFVAL                                0x03040001
#define DDRC_MSTR_LPDDR4_SHIFT                                 5
#define DDRC_MSTR_LPDDR4_MASK                                  0x00000020U

/*
* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
    * in use Present only in designs configured to support DDR4.
*/
#undef DDRC_MSTR_DDR4_DEFVAL 
#undef DDRC_MSTR_DDR4_SHIFT 
#undef DDRC_MSTR_DDR4_MASK 
#define DDRC_MSTR_DDR4_DEFVAL                                  0x03040001
#define DDRC_MSTR_DDR4_SHIFT                                   4
#define DDRC_MSTR_DDR4_MASK                                    0x00000010U

/*
* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
    * evice in use Present only in designs configured to support LPDDR3.
*/
#undef DDRC_MSTR_LPDDR3_DEFVAL 
#undef DDRC_MSTR_LPDDR3_SHIFT 
#undef DDRC_MSTR_LPDDR3_MASK 
#define DDRC_MSTR_LPDDR3_DEFVAL                                0x03040001
#define DDRC_MSTR_LPDDR3_SHIFT                                 3
#define DDRC_MSTR_LPDDR3_MASK                                  0x00000008U

/*
* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
    * evice in use Present only in designs configured to support LPDDR2.
*/
#undef DDRC_MSTR_LPDDR2_DEFVAL 
#undef DDRC_MSTR_LPDDR2_SHIFT 
#undef DDRC_MSTR_LPDDR2_MASK 
#define DDRC_MSTR_LPDDR2_DEFVAL                                0x03040001
#define DDRC_MSTR_LPDDR2_SHIFT                                 2
#define DDRC_MSTR_LPDDR2_MASK                                  0x00000004U

/*
* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
    * vice in use Only present in designs that support DDR3.
*/
#undef DDRC_MSTR_DDR3_DEFVAL 
#undef DDRC_MSTR_DDR3_SHIFT 
#undef DDRC_MSTR_DDR3_MASK 
#define DDRC_MSTR_DDR3_DEFVAL                                  0x03040001
#define DDRC_MSTR_DDR3_SHIFT                                   0
#define DDRC_MSTR_DDR3_MASK                                    0x00000001U

/*
* Setting this register bit to 1 triggers a mode register read or write op
    * eration. When the MR operation is complete, the uMCTL2 automatically cle
    * ars this bit. The other register fields of this register must be written
    *  in a separate APB transaction, before setting this mr_wr bit. It is rec
    * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
    * ating modes.
*/
#undef DDRC_MRCTRL0_MR_WR_DEFVAL 
#undef DDRC_MRCTRL0_MR_WR_SHIFT 
#undef DDRC_MRCTRL0_MR_WR_MASK 
#define DDRC_MRCTRL0_MR_WR_DEFVAL                              0x00000030
#define DDRC_MRCTRL0_MR_WR_SHIFT                               31
#define DDRC_MRCTRL0_MR_WR_MASK                                0x80000000U

/*
* Address of the mode register that is to be written to. - 0000 - MR0 - 00
    * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR
    * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data
    * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als
    * o used for writing to control words of RDIMMs. In that case, it correspo
    * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[
    * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a
    * s the bit[2:0] must be set to an appropriate value which is considered b
    * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
    * DIMMs.
*/
#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL 
#undef DDRC_MRCTRL0_MR_ADDR_SHIFT 
#undef DDRC_MRCTRL0_MR_ADDR_MASK 
#define DDRC_MRCTRL0_MR_ADDR_DEFVAL                            0x00000030
#define DDRC_MRCTRL0_MR_ADDR_SHIFT                             12
#define DDRC_MRCTRL0_MR_ADDR_MASK                              0x0000F000U

/*
* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire
    * d to access all ranks, so all bits should be set to 1. However, for mult
    * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess
    * ary to access ranks individually. Examples (assume uMCTL2 is configured
    * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x
    * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
    * ks 0, 1, 2 and 3
*/
#undef DDRC_MRCTRL0_MR_RANK_DEFVAL 
#undef DDRC_MRCTRL0_MR_RANK_SHIFT 
#undef DDRC_MRCTRL0_MR_RANK_MASK 
#define DDRC_MRCTRL0_MR_RANK_DEFVAL                            0x00000030
#define DDRC_MRCTRL0_MR_RANK_SHIFT                             4
#define DDRC_MRCTRL0_MR_RANK_MASK                              0x00000030U

/*
* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b
    * efore automatic SDRAM initialization routine or not. For DDR4, this bit
    * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init
    * ialization. For LPDDR4, this bit can be used to program additional mode
    * registers before automatic SDRAM initialization if necessary. Note: This
    *  must be cleared to 0 after completing Software operation. Otherwise, SD
    * RAM initialization routine will not re-start. - 0 - Software interventio
    * n is not allowed - 1 - Software intervention is allowed
*/
#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 
#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT 
#undef DDRC_MRCTRL0_SW_INIT_INT_MASK 
#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL                        0x00000030
#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT                         3
#define DDRC_MRCTRL0_SW_INIT_INT_MASK                          0x00000008U

/*
* Indicates whether the mode register operation is MRS in PDA mode or not
    * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
*/
#undef DDRC_MRCTRL0_PDA_EN_DEFVAL 
#undef DDRC_MRCTRL0_PDA_EN_SHIFT 
#undef DDRC_MRCTRL0_PDA_EN_MASK 
#define DDRC_MRCTRL0_PDA_EN_DEFVAL                             0x00000030
#define DDRC_MRCTRL0_PDA_EN_SHIFT                              2
#define DDRC_MRCTRL0_PDA_EN_MASK                               0x00000004U

/*
* Indicates whether the mode register operation is MRS or WR/RD for MPR (o
    * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
*/
#undef DDRC_MRCTRL0_MPR_EN_DEFVAL 
#undef DDRC_MRCTRL0_MPR_EN_SHIFT 
#undef DDRC_MRCTRL0_MPR_EN_MASK 
#define DDRC_MRCTRL0_MPR_EN_DEFVAL                             0x00000030
#define DDRC_MRCTRL0_MPR_EN_SHIFT                              1
#define DDRC_MRCTRL0_MPR_EN_MASK                               0x00000002U

/*
* Indicates whether the mode register operation is read or write. Only use
    * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
*/
#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL 
#undef DDRC_MRCTRL0_MR_TYPE_SHIFT 
#undef DDRC_MRCTRL0_MR_TYPE_MASK 
#define DDRC_MRCTRL0_MR_TYPE_DEFVAL                            0x00000030
#define DDRC_MRCTRL0_MR_TYPE_SHIFT                             0
#define DDRC_MRCTRL0_MR_TYPE_MASK                              0x00000001U

/*
* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us
    * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d
    * esigns configured to support LPDDR4. The required number of cycles for d
    * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
    * eriod, and rounding up the next integer.
*/
#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 
#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 
#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK 
#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL                   0x00000000
#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT                    8
#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK                     0x00000300U

/*
* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/
    * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
    * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
*/
#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL 
#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT 
#undef DDRC_DERATEEN_DERATE_BYTE_MASK 
#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL                       0x00000000
#define DDRC_DERATEEN_DERATE_BYTE_SHIFT                        4
#define DDRC_DERATEEN_DERATE_BYTE_MASK                         0x000000F0U

/*
* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl
    * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all
    *  LPDDR2 speed grades as derating value of +1.875 ns is less than a core_
    * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
    * 75 ns is less than a core_ddrc_core_clk period or not.
*/
#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL 
#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT 
#undef DDRC_DERATEEN_DERATE_VALUE_MASK 
#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL                      0x00000000
#define DDRC_DERATEEN_DERATE_VALUE_SHIFT                       1
#define DDRC_DERATEEN_DERATE_VALUE_MASK                        0x00000002U

/*
* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin
    * g parameter derating is enabled using MR4 read value. Present only in de
    * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
    * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
*/
#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 
#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT 
#undef DDRC_DERATEEN_DERATE_ENABLE_MASK 
#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL                     0x00000000
#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT                      0
#define DDRC_DERATEEN_DERATE_ENABLE_MASK                       0x00000001U

/*
* Interval between two MR4 reads, used to derate the timing parameters. Pr
    * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
    * egister must not be set to zero
*/
#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL 
#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 
#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 
#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL                
#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT                 0
#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK                  0xFFFFFFFFU

/*
* Self refresh state is an intermediate state to enter to Self refresh pow
    * er down state or exit Self refresh power down state for LPDDR4. This reg
    * ister controls transition from the Self refresh state. - 1 - Prohibit tr
    * ansition from Self refresh state - 0 - Allow transition from Self refres
    * h state
*/
#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 
#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 
#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK 
#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL                     0x00000000
#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT                      6
#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK                       0x00000040U

/*
* A value of 1 to this register causes system to move to Self Refresh stat
    * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode.
    * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
    * re Entry to Self Refresh - 0 - Software Exit from Self Refresh
*/
#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL 
#undef DDRC_PWRCTL_SELFREF_SW_SHIFT 
#undef DDRC_PWRCTL_SELFREF_SW_MASK 
#define DDRC_PWRCTL_SELFREF_SW_DEFVAL                          0x00000000
#define DDRC_PWRCTL_SELFREF_SW_SHIFT                           5
#define DDRC_PWRCTL_SELFREF_SW_MASK                            0x00000020U

/*
* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode
    *  when the transaction store is empty. This register must be reset to '0'
    *  to bring uMCTL2 out of maximum power saving mode. Present only in desig
    * ns configured to support DDR4. For non-DDR4, this register should not be
    *  set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if
    * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
    * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
*/
#undef DDRC_PWRCTL_MPSM_EN_DEFVAL 
#undef DDRC_PWRCTL_MPSM_EN_SHIFT 
#undef DDRC_PWRCTL_MPSM_EN_MASK 
#define DDRC_PWRCTL_MPSM_EN_DEFVAL                             0x00000000
#define DDRC_PWRCTL_MPSM_EN_SHIFT                              4
#define DDRC_PWRCTL_MPSM_EN_MASK                               0x00000010U

/*
* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req
    * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted.
    *  Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only
    *  be asserted in Self Refresh. In DDR4, can be asserted in following: - i
    * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca
    * n be asserted in following: - in Self Refresh - in Power Down - in Deep
    * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse
    * rted in following: - in Self Refresh Power Down - in Power Down - during
    *  Normal operation (Clock Stop)
*/
#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 
#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 
#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL             0x00000000
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT              3
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK               0x00000008U

/*
* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the
    *  transaction store is empty. This register must be reset to '0' to bring
    *  uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM
    *  initialization on deep power-down exit. Present only in designs configu
    * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
    * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
*/
#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 
#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 
#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL                    0x00000000
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT                     2
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK                      0x00000004U

/*
* If true then the uMCTL2 goes into power-down after a programmable number
    *  of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_
    * x32). This register bit may be re-programmed during the course of normal
    *  operation.
*/
#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 
#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT 
#undef DDRC_PWRCTL_POWERDOWN_EN_MASK 
#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL                        0x00000000
#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT                         1
#define DDRC_PWRCTL_POWERDOWN_EN_MASK                          0x00000002U

/*
* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program
    * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.
    * selfref_to_x32)'. This register bit may be re-programmed during the cour
    * se of normal operation.
*/
#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL 
#undef DDRC_PWRCTL_SELFREF_EN_SHIFT 
#undef DDRC_PWRCTL_SELFREF_EN_MASK 
#define DDRC_PWRCTL_SELFREF_EN_DEFVAL                          0x00000000
#define DDRC_PWRCTL_SELFREF_EN_SHIFT                           0
#define DDRC_PWRCTL_SELFREF_EN_MASK                            0x00000001U

/*
* After this many clocks of NOP or deselect the uMCTL2 automatically puts
    * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
    * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
*/
#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 
#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 
#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK 
#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL                      0x00402010
#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT                       16
#define DDRC_PWRTMG_SELFREF_TO_X32_MASK                        0x00FF0000U

/*
* Minimum deep power-down time. For mDDR, value from the JEDEC specificati
    * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL
    * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE
    * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i
    * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
    * ONLY.
*/
#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL 
#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT 
#undef DDRC_PWRTMG_T_DPD_X4096_MASK 
#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL                         0x00402010
#define DDRC_PWRTMG_T_DPD_X4096_SHIFT                          8
#define DDRC_PWRTMG_T_DPD_X4096_MASK                           0x0000FF00U

/*
* After this many clocks of NOP or deselect the uMCTL2 automatically puts
    * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
    * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
*/
#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 
#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 
#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 
#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL                    0x00402010
#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT                     0
#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK                      0x0000001FU

/*
* Threshold value in number of clock cycles before the critical refresh or
    *  page timer expires. A critical refresh is to be issued before this thre
    * shold is reached. It is recommended that this not be changed from the de
    * fault value, currently shown as 0x2. It must always be less than interna
    * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u
    * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i
    * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n
    * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
    * cks.
*/
#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 
#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 
#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 
#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL                    0x00210000
#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT                     20
#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK                      0x00F00000U

/*
* If the refresh timer (tRFCnom, also known as tREFI) has expired at least
    *  once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then
    *  a speculative refresh may be performed. A speculative refresh is a refr
    * esh performed at a time when refresh would be useful, but before it is a
    * bsolutely required. When the SDRAM bus is idle for a period of time dete
    * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired
    *  at least once since the last refresh, then a speculative refresh is per
    * formed. Speculative refreshes continues successively until there are no
    * refreshes pending or until new reads or writes are issued to the uMCTL2.
    *  FOR PERFORMANCE ONLY.
*/
#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 
#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 
#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 
#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL                    0x00210000
#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT                     12
#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK                      0x0001F000U

/*
* The programmed value + 1 is the number of refresh timeouts that is allow
    * ed to accumulate before traffic is blocked and the refreshes are forced
    * to execute. Closing pages to perform a refresh is a one-time penalty tha
    * t must be paid for each group of refreshes. Therefore, performing refres
    * hes in a burst reduces the per-refresh penalty of these page closings. H
    * igher numbers for RFSHCTL.refresh_burst slightly increases utilization;
    * lower numbers decreases the worst-case latency associated with refreshes
    * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh
    *  For information on burst refresh feature refer to section 3.9 of DDR2 J
    * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe
    * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF
    * I cycles using the burst refresh feature. In DDR4 mode, according to Fin
    * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre
    * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda
    * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens
    * ure that tRFCmax is not violated due to a PHY-initiated update occurring
    *  shortly before a refresh burst was due. In this situation, the refresh
    * burst will be delayed until the PHY-initiated update is complete.
*/
#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 
#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 
#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK 
#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL                     0x00210000
#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT                      4
#define DDRC_RFSHCTL0_REFRESH_BURST_MASK                       0x000001F0U

/*
* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
    * traffic to flow to other banks. Per bank refresh is not supported by all
    *  LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
    * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
*/
#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 
#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 
#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 
#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL                  0x00210000
#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT                   2
#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK                    0x00000004U

/*
* Refresh timer start for rank 1 (only present in multi-rank configuration
    * s). This is useful in staggering the refreshes to multiple ranks to help
    *  traffic to proceed. This is explained in Refresh Controls section of ar
    * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
*/
#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 
#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 
#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL    0x00000000
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT     16
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK      0x0FFF0000U

/*
* Refresh timer start for rank 0 (only present in multi-rank configuration
    * s). This is useful in staggering the refreshes to multiple ranks to help
    *  traffic to proceed. This is explained in Refresh Controls section of ar
    * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
*/
#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 
#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 
#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL    0x00000000
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT     0
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK      0x00000FFFU

/*
* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix
    * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11
    * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No
    * te: The on-the-fly modes is not supported in this version of the uMCTL2.
    *  Note: This must be set up while the Controller is in reset or while the
    *  Controller is in self-refresh mode. Changing this during normal operati
    * on is not allowed. Making this a dynamic register will be supported in f
    * uture version of the uMCTL2.
*/
#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 
#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 
#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK 
#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL                      0x00000000
#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT                       4
#define DDRC_RFSHCTL3_REFRESH_MODE_MASK                        0x00000070U

/*
* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
    * the refresh register(s) have been updated. The value is automatically up
    * dated when exiting reset, so it does not need to be toggled initially.
*/
#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 
#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 
#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 
#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL              0x00000000
#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT               1
#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK                0x00000002U

/*
* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres
    * h is disabled, the SoC core must generate refreshes using the registers
    * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a
    * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1
    * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4
    *  CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
    * isable auto-refresh is not supported, and this bit must be set to '0'. T
    * his register field is changeable on the fly.
*/
#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 
#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 
#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 
#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL                  0x00000000
#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT                   0
#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK                    0x00000001U

/*
* tREFI: Average time interval between refreshes per rank (Specification:
    * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2,
    *  LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre
    * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE
    * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
    *  register should be set to tREFIpb For configurations with MEMC_FREQ_RAT
    * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val
    * ue is different depending on the refresh mode. The user should program t
    * he appropriate value from the spec based on the value programmed in the
    * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea
    * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
    * an 0x1. Unit: Multiples of 32 clocks.
*/
#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 
#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 
#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 
#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL                      0x0062008C
#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT                       16
#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK                        0x0FFF0000U

/*
* Used only when LPDDR3 memory type is connected. Should only be changed w
    * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r
    * equired by some LPDDR3 devices which comply with earlier versions of the
    *  LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
    *  - tREFBW parameter used
*/
#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 
#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 
#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL                   0x0062008C
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT                    15
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK                     0x00008000U

/*
* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F
    * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t
    * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro
    * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using
    * all-bank refreshes, the tRFCmin value in the above equations is equal to
    *  tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq
    * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
    * equations is different depending on the refresh mode (fixed 1X,2X,4X) an
    * d the device density. The user should program the appropriate value from
    *  the spec based on the 'refresh_mode' and the device density that is use
    * d. Unit: Clocks.
*/
#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 
#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT 
#undef DDRC_RFSHTMG_T_RFC_MIN_MASK 
#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL                          0x0062008C
#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT                           0
#define DDRC_RFSHTMG_T_RFC_MIN_MASK                            0x000003FFU

/*
* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
    * SE_RMW is defined
*/
#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 
#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT 
#undef DDRC_ECCCFG0_DIS_SCRUB_MASK 
#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL                          0x00000000
#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT                           4
#define DDRC_ECCCFG0_DIS_SCRUB_MASK                            0x00000010U

/*
* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
    * er 1 beat - all other settings are reserved for future use
*/
#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL 
#undef DDRC_ECCCFG0_ECC_MODE_SHIFT 
#undef DDRC_ECCCFG0_ECC_MODE_MASK 
#define DDRC_ECCCFG0_ECC_MODE_DEFVAL                           0x00000000
#define DDRC_ECCCFG0_ECC_MODE_SHIFT                            0
#define DDRC_ECCCFG0_ECC_MODE_MASK                             0x00000007U

/*
* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da
    * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
    * a_poison_en=1
*/
#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 
#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 
#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK 
#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL                    0x00000000
#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT                     1
#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK                      0x00000002U

/*
* Enable ECC data poisoning - introduces ECC errors on writes to address s
    * pecified by the ECCPOISONADDR0/1 registers
*/
#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 
#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 
#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK 
#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL                     0x00000000
#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT                      0
#define DDRC_ECCCFG1_DATA_POISON_EN_MASK                       0x00000001U

/*
* The maximum number of DFI PHY clock cycles allowed from the assertion of
    *  the dfi_rddata_en signal to the assertion of each of the corresponding
    * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing
    * parameter tphy_rdlat. Refer to PHY specification for correct value. This
    *  value it only used for detecting read data timeout when DDR4 retry is e
    * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value:
    *  - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r
    * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1
    *  : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d
    * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
    * rdlat < 'd114 Unit: DFI Clocks
*/
#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 
#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 
#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 
#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL                 0x10000200
#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT                  24
#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK                   0x3F000000U

/*
* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa
    * re has an option to read the mode registers in the DRAM before the hardw
    * are begins the retry process - 1: Wait for software to read/write the mo
    * de registers before hardware begins the retry. After software is done wi
    * th its operations, it will clear the alert interrupt register bit - 0: H
    * ardware can begin the retry right away after the dfi_alert_n pulse goes
    * away. The value on this register is valid only when retry is enabled (PA
    * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t
    * he software doesn't clear the interrupt register after handling the pari
    * ty/CRC error, then the hardware will not begin the retry process and the
    *  system will hang. In the case of Parity/CRC error, there are two possib
    * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten
    * t parity' mode register bit is NOT set: the commands sent during retry a
    * nd normal operation are executed without parity checking. The value in t
    * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent
    * parity' mode register bit is SET: Parity checking is done for commands s
    * ent during retry and normal operation. If multiple errors occur before M
    * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
    * t care'.
*/
#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 
#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 
#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 
#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL               0x10000200
#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT                9
#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK                 0x00000200U

/*
* - 1: Enable command retry mechanism in case of C/A Parity or CRC error -
    *  0: Disable command retry mechanism when C/A Parity or CRC features are
    * enabled. Note that retry functionality is not supported if burst chop is
    *  enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF
    * SHCTL3.dis_auto_refresh = 1)
*/
#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 
#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 
#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 
#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL         0x10000200
#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT          8
#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK           0x00000100U

/*
* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no
    * t includes DM signal Present only in designs configured to support DDR4.
*/
#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 
#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 
#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK 
#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL                      0x10000200
#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT                       7
#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK                        0x00000080U

/*
* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio
    * n of CRC The setting of this register should match the CRC mode register
    *  setting in the DRAM.
*/
#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 
#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 
#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK 
#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL                      0x10000200
#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT                       4
#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK                        0x00000010U

/*
* C/A Parity enable register - 1: Enable generation of C/A parity and dete
    * ction of C/A parity error - 0: Disable generation of C/A parity and disa
    * ble detection of C/A parity error If RCD's parity error detection or SDR
    * AM's parity detection is enabled, this register should be 1.
*/
#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 
#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 
#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 
#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL                   0x10000200
#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT                    0
#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK                     0x00000001U

/*
* Value from the DRAM spec indicating the maximum width of the dfi_alert_n
    *  pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M
    * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT
    * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i
    * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
*/
#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 
#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 
#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 
#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL              0x0030050C
#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT               16
#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK                0x01FF0000U

/*
* Value from the DRAM spec indicating the maximum width of the dfi_alert_n
    *  pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX
    * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW
    * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille
    * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
*/
#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 
#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 
#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 
#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL              0x0030050C
#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT               8
#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK                0x00001F00U

/*
* Indicates the maximum duration in number of DRAM clock cycles for which
    * a command should be held in the Command Retry FIFO before it is popped o
    * ut. Every location in the Command Retry FIFO has an associated down coun
    * ting timer that will use this register as the start value. The down coun
    * ting starts when a command is loaded into the FIFO. The timer counts dow
    * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe
    * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err
    * or occurs before the counter reaches zero. The counter is reset to 0, af
    * ter all the commands in the FIFO are retried. Recommended(minimum) value
    * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK)
    * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten
    * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable
    * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R
    * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
    * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be
    *  in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n
    * ) should be considered. Note 3: Use the worst case(longer) value for PHY
    *  Latencies/Board delay Note 4: The Recommended values are minimum value
    * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max
    *  value can be set to this register is defined below: - MEMC_BURST_LENGTH
    *  == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2
    *  Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b
    * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod
    * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C
    * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC=
    * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16
    *  Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full
    * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod
    * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC
    * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF
    * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma
    * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal
    * .
*/
#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 
#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 
#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 
#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL    0x0030050C
#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT     0
#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK      0x0000003FU

/*
* If lower bit is enabled the SDRAM initialization routine is skipped. The
    *  upper bit decides what state the controller starts up in when reset is
    * removed - 00 - SDRAM Intialization routine is run after power-up - 01 -
    * SDRAM Intialization routine is skipped after power-up. Controller starts
    *  up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p
    * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ
    * ation routine is run after power-up. Note: The only 2'b00 is supported f
    * or LPDDR4 in this version of the uMCTL2.
*/
#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 
#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 
#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK 
#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL                       0x0002004E
#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT                        30
#define DDRC_INIT0_SKIP_DRAM_INIT_MASK                         0xC0000000U

/*
* Cycles to wait after driving CKE high to start the SDRAM initialization
    * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req
    * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD
    * R3 typically requires this to be programmed for a delay of 200 us. LPDDR
    * 4 typically requires this to be programmed for a delay of 2 us. For conf
    * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi
    * ded by 2, and round it up to next integer value.
*/
#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL 
#undef DDRC_INIT0_POST_CKE_X1024_SHIFT 
#undef DDRC_INIT0_POST_CKE_X1024_MASK 
#define DDRC_INIT0_POST_CKE_X1024_DEFVAL                       0x0002004E
#define DDRC_INIT0_POST_CKE_X1024_SHIFT                        16
#define DDRC_INIT0_POST_CKE_X1024_MASK                         0x03FF0000U

/*
* Cycles to wait after reset before driving CKE high to start the SDRAM in
    * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi
    * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD
    * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati
    * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by
    * 2, and round it up to next integer value.
*/
#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL 
#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT 
#undef DDRC_INIT0_PRE_CKE_X1024_MASK 
#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL                        0x0002004E
#define DDRC_INIT0_PRE_CKE_X1024_SHIFT                         0
#define DDRC_INIT0_PRE_CKE_X1024_MASK                          0x00000FFFU

/*
* Number of cycles to assert SDRAM reset signal during init sequence. This
    *  is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo
    * r use with a DDR PHY, this should be set to a minimum of 1
*/
#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 
#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 
#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK 
#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL                      0x00000000
#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT                       16
#define DDRC_INIT1_DRAM_RSTN_X1024_MASK                        0x01FF0000U

/*
* Cycles to wait after completing the SDRAM initialization sequence before
    *  starting the dynamic scheduler. Unit: Counts of a global timer that pul
    * ses every 32 clock cycles. There is no known specific requirement for th
    * is; it may be set to zero.
*/
#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 
#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT 
#undef DDRC_INIT1_FINAL_WAIT_X32_MASK 
#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL                       0x00000000
#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT                        8
#define DDRC_INIT1_FINAL_WAIT_X32_MASK                         0x00007F00U

/*
* Wait period before driving the OCD complete command to SDRAM. Unit: Coun
    * ts of a global timer that pulses every 32 clock cycles. There is no know
    * n specific requirement for this; it may be set to zero.
*/
#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL 
#undef DDRC_INIT1_PRE_OCD_X32_SHIFT 
#undef DDRC_INIT1_PRE_OCD_X32_MASK 
#define DDRC_INIT1_PRE_OCD_X32_DEFVAL                          0x00000000
#define DDRC_INIT1_PRE_OCD_X32_SHIFT                           0
#define DDRC_INIT1_PRE_OCD_X32_MASK                            0x0000000FU

/*
* Idle time after the reset command, tINIT4. Present only in designs confi
    * gured to support LPDDR2. Unit: 32 clock cycles.
*/
#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 
#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 
#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 
#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL                 0x00000D05
#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT                  8
#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK                   0x0000FF00U

/*
* Time to wait after the first CKE high, tINIT2. Present only in designs c
    * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t
    * ypically requires 5 x tCK delay.
*/
#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 
#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 
#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 
#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL                  0x00000D05
#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT                   0
#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK                    0x0000000FU

/*
* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he
    * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value
    * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP
    * DDR3/LPDDR4 - Value to write to MR1 register
*/
#undef DDRC_INIT3_MR_DEFVAL 
#undef DDRC_INIT3_MR_SHIFT 
#undef DDRC_INIT3_MR_MASK 
#define DDRC_INIT3_MR_DEFVAL                                   0x00000510
#define DDRC_INIT3_MR_SHIFT                                    16
#define DDRC_INIT3_MR_MASK                                     0xFFFF0000U

/*
* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti
    * ng in this register is ignored. The uMCTL2 sets those bits appropriately
    * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu
    * ation mode training is enabled, this bit is set appropriately by the uMC
    * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/
    * LPDDR3/LPDDR4 - Value to write to MR2 register
*/
#undef DDRC_INIT3_EMR_DEFVAL 
#undef DDRC_INIT3_EMR_SHIFT 
#undef DDRC_INIT3_EMR_MASK 
#define DDRC_INIT3_EMR_DEFVAL                                  0x00000510
#define DDRC_INIT3_EMR_SHIFT                                   0
#define DDRC_INIT3_EMR_MASK                                    0x0000FFFFU

/*
* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2
    * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus
    * ed
*/
#undef DDRC_INIT4_EMR2_DEFVAL 
#undef DDRC_INIT4_EMR2_SHIFT 
#undef DDRC_INIT4_EMR2_MASK 
#define DDRC_INIT4_EMR2_DEFVAL                                 0x00000000
#define DDRC_INIT4_EMR2_SHIFT                                  16
#define DDRC_INIT4_EMR2_MASK                                   0xFFFF0000U

/*
* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3
    * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis
    * ter
*/
#undef DDRC_INIT4_EMR3_DEFVAL 
#undef DDRC_INIT4_EMR3_SHIFT 
#undef DDRC_INIT4_EMR3_MASK 
#define DDRC_INIT4_EMR3_DEFVAL                                 0x00000000
#define DDRC_INIT4_EMR3_SHIFT                                  0
#define DDRC_INIT4_EMR3_MASK                                   0x0000FFFFU

/*
* ZQ initial calibration, tZQINIT. Present only in designs configured to s
    * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica
    * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir
    * es 1 us.
*/
#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 
#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 
#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK 
#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL                       0x00100004
#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT                        16
#define DDRC_INIT5_DEV_ZQINIT_X32_MASK                         0x00FF0000U

/*
* Maximum duration of the auto initialization, tINIT5. Present only in des
    * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir
    * es 10 us.
*/
#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 
#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 
#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 
#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL                  0x00100004
#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT                   0
#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK                    0x000003FFU

/*
* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs
    * only.
*/
#undef DDRC_INIT6_MR4_DEFVAL 
#undef DDRC_INIT6_MR4_SHIFT 
#undef DDRC_INIT6_MR4_MASK 
#define DDRC_INIT6_MR4_DEFVAL                                  0x00000000
#define DDRC_INIT6_MR4_SHIFT                                   16
#define DDRC_INIT6_MR4_MASK                                    0xFFFF0000U

/*
* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs
    * only.
*/
#undef DDRC_INIT6_MR5_DEFVAL 
#undef DDRC_INIT6_MR5_SHIFT 
#undef DDRC_INIT6_MR5_MASK 
#define DDRC_INIT6_MR5_DEFVAL                                  0x00000000
#define DDRC_INIT6_MR5_SHIFT                                   0
#define DDRC_INIT6_MR5_MASK                                    0x0000FFFFU

/*
* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs
    * only.
*/
#undef DDRC_INIT7_MR6_DEFVAL 
#undef DDRC_INIT7_MR6_SHIFT 
#undef DDRC_INIT7_MR6_MASK 
#define DDRC_INIT7_MR6_DEFVAL                                  
#define DDRC_INIT7_MR6_SHIFT                                   16
#define DDRC_INIT7_MR6_MASK                                    0xFFFF0000U

/*
* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
    * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r
    * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp
    * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled.
*/
#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 
#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 
#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 
#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL              0x00000000
#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT               5
#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK                0x00000020U

/*
* Enable for BG1 bit of MRS command. BG1 bit of the mode register address
    * is specified as RFU (Reserved for Future Use) and must be programmed to
    * 0 during MRS. In case where DRAMs which do not have BG1 are attached and
    *  both the CA parity and the Output Inversion are enabled, this must be s
    * et to 0, so that the calculation of CA parity will not include BG1 bit.
    * Note: This has no effect on the address of any other memory accesses, or
    *  of software-driven mode register accesses. If address mirroring is enab
    * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En
    * abled - 0 - Disabled
*/
#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 
#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 
#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK 
#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL                         0x00000000
#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT                          4
#define DDRC_DIMMCTL_MRS_BG1_EN_MASK                           0x00000010U

/*
* Enable for A17 bit of MRS command. A17 bit of the mode register address
    * is specified as RFU (Reserved for Future Use) and must be programmed to
    * 0 during MRS. In case where DRAMs which do not have A17 are attached and
    *  the Output Inversion are enabled, this must be set to 0, so that the ca
    * lculation of CA parity will not include A17 bit. Note: This has no effec
    * t on the address of any other memory accesses, or of software-driven mod
    * e register accesses. - 1 - Enabled - 0 - Disabled
*/
#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 
#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT 
#undef DDRC_DIMMCTL_MRS_A17_EN_MASK 
#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL                         0x00000000
#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT                          3
#define DDRC_DIMMCTL_MRS_A17_EN_MASK                           0x00000008U

/*
* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM
    * M implements the Output Inversion feature by default, which means that t
    * he following address, bank address and bank group bits of B-side DRAMs a
    * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en
    * sures that, for mode register accesses generated by the uMCTL2 during th
    * e automatic initialization routine and enabling of a particular DDR4 fea
    * ture, separate A-side and B-side mode register accesses are generated. F
    * or B-side mode register accesses, these bits are inverted within the uMC
    * TL2 to compensate for this RDIMM inversion. Note: This has no effect on
    * the address of any other memory accesses, or of software-driven mode reg
    * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 -
    *  Do not implement output inversion for B-side DRAMs.
*/
#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 
#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 
#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 
#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL                 0x00000000
#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT                  2
#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK                   0x00000004U

/*
* Address Mirroring Enable (for multi-rank UDIMM implementations and multi
    * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement
    *  address mirroring for odd ranks, which means that the following address
    * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7,
    *  A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t
    * his bit ensures that, for mode register accesses during the automatic in
    * itialization routine, these bits are swapped within the uMCTL2 to compen
    * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial
    * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th
    * e automatic MRS access to enable/disable of a particular DDR4 feature. N
    * ote: This has no effect on the address of any other memory accesses, or
    * of software-driven mode register accesses. This is not supported for mDD
    * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1
    *  output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
    * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran
    * ks, implement address mirroring for MRS commands to during initializatio
    * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp
    * lements address mirroring) - 0 - Do not implement address mirroring
*/
#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 
#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 
#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 
#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL                  0x00000000
#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT                   1
#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK                    0x00000002U

/*
* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM
    * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3
    * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of
    *  software driven MR commands (via MRCTRL0/MRCTRL1), where software is re
    * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se
    * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma
    * nds to even and odd ranks seperately - 0 - Do not stagger accesses
*/
#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 
#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 
#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 
#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL                 0x00000000
#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT                  0
#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK                   0x00000001U

/*
* Only present for multi-rank configurations. Indicates the number of cloc
    * ks of gap in data responses when performing consecutive writes to differ
    * ent ranks. This is used to switch the delays in the PHY to match the ran
    * k requirements. This value should consider both PHY requirement and ODT
    * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v
    * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by
    * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas
    * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc
    * reased by 1. - ODT requirement: The value programmed in this register ta
    * kes care of the ODT switch off timing requirement when switching ranks d
    * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1
    *  For configurations with MEMC_FREQ_RATIO=1, program this to the larger o
    * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_
    * RATIO=2, program this to the larger value divided by two and round it up
    *  to the next integer.
*/
#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 
#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 
#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 
#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL                   0x0000066F
#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT                    8
#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK                     0x00000F00U

/*
* Only present for multi-rank configurations. Indicates the number of cloc
    * ks of gap in data responses when performing consecutive reads to differe
    * nt ranks. This is used to switch the delays in the PHY to match the rank
    *  requirements. This value should consider both PHY requirement and ODT r
    * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va
    * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only),
    * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only
    * ), should be increased by 1. - ODT requirement: The value programmed in
    * this register takes care of the ODT switch off timing requirement when s
    * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1,
    * program this to the larger of PHY requirement or ODT requirement. For co
    * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di
    * vided by two and round it up to the next integer.
*/
#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 
#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 
#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 
#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL                   0x0000066F
#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT                    4
#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK                     0x000000F0U

/*
* Only present for multi-rank configurations. Background: Reads to the sam
    * e rank can be performed back-to-back. Reads to different ranks require a
    * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is
    *  to avoid possible data bus contention as well as to give PHY enough tim
    * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus
    *  access on a cycle-by-cycle basis; therefore after a read is scheduled,
    * there are few clock cycles (determined by the value on RANKCTL.diff_rank
    * _rd_gap register) in which only reads from the same rank are eligible to
    *  be scheduled. This prevents reads from other ranks from having fair acc
    * ess to the data bus. This parameter represents the maximum number of rea
    * ds that can be scheduled consecutively to the same rank. After this numb
    * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by
    * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig
    * her numbers increase bandwidth utilization, lower numbers increase fairn
    * ess. This feature can be DISABLED by setting this register to 0. When se
    * t to 0, the Controller will stay on the same rank as long as commands ar
    * e available for it. Minimum programmable value is 0 (feature disabled) a
    * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
*/
#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 
#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT 
#undef DDRC_RANKCTL_MAX_RANK_RD_MASK 
#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL                        0x0000066F
#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT                         0
#define DDRC_RANKCTL_MAX_RANK_RD_MASK                          0x0000000FU

/*
* Minimum time between write and precharge to same bank. Unit: Clocks Spec
    * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks
    *  @400MHz and less for lower frequencies where: - WL = write latency - BL
    *  = burst length. This must match the value programmed in the BL bit of t
    * he mode register to the SDRAM. BST (burst terminate) is not supported at
    *  present. - tWR = Write recovery time. This comes directly from the SDRA
    * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p
    * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the
    *  above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT
    * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u
    * p to the next integer value.
*/
#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL 
#undef DDRC_DRAMTMG0_WR2PRE_SHIFT 
#undef DDRC_DRAMTMG0_WR2PRE_MASK 
#define DDRC_DRAMTMG0_WR2PRE_DEFVAL                            0x0F101B0F
#define DDRC_DRAMTMG0_WR2PRE_SHIFT                             24
#define DDRC_DRAMTMG0_WR2PRE_MASK                              0x7F000000U

/*
* tFAW Valid only when 8 or more banks(or banks x bank groups) are present
    * . In 8-bank design, at most 4 banks must be activated in a rolling windo
    * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi
    * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se
    * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration.
    *  Unit: Clocks
*/
#undef DDRC_DRAMTMG0_T_FAW_DEFVAL 
#undef DDRC_DRAMTMG0_T_FAW_SHIFT 
#undef DDRC_DRAMTMG0_T_FAW_MASK 
#define DDRC_DRAMTMG0_T_FAW_DEFVAL                             0x0F101B0F
#define DDRC_DRAMTMG0_T_FAW_SHIFT                              16
#define DDRC_DRAMTMG0_T_FAW_MASK                               0x003F0000U

/*
* tRAS(max): Maximum time between activate and precharge to same bank. Thi
    * s is the maximum time that a page can be kept open Minimum value of this
    *  register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO
    * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of
    * 1024 clocks.
*/
#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 
#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 
#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK 
#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL                         0x0F101B0F
#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT                          8
#define DDRC_DRAMTMG0_T_RAS_MAX_MASK                           0x00007F00U

/*
* tRAS(min): Minimum time between activate and precharge to the same bank.
    *  For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA
    * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T
    * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th
    * e next integer value. Unit: Clocks
*/
#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 
#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 
#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK 
#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL                         0x0F101B0F
#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT                          0
#define DDRC_DRAMTMG0_T_RAS_MIN_MASK                           0x0000003FU

/*
* tXP: Minimum time after power-down exit to any operation. For DDR3, this
    *  should be programmed to tXPDLL if slow powerdown exit is selected in MR
    * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf
    * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it
    * up to the next integer value. Units: Clocks
*/
#undef DDRC_DRAMTMG1_T_XP_DEFVAL 
#undef DDRC_DRAMTMG1_T_XP_SHIFT 
#undef DDRC_DRAMTMG1_T_XP_MASK 
#define DDRC_DRAMTMG1_T_XP_DEFVAL                              0x00080414
#define DDRC_DRAMTMG1_T_XP_SHIFT                               16
#define DDRC_DRAMTMG1_T_XP_MASK                                0x001F0000U

/*
* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL
    * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi
    * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2
    * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t
    * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4)
    *  - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_
    * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi
    * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo
    * ve value by 2 and round it up to the next integer value. Unit: Clocks.
*/
#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL 
#undef DDRC_DRAMTMG1_RD2PRE_SHIFT 
#undef DDRC_DRAMTMG1_RD2PRE_MASK 
#define DDRC_DRAMTMG1_RD2PRE_DEFVAL                            0x00080414
#define DDRC_DRAMTMG1_RD2PRE_SHIFT                             8
#define DDRC_DRAMTMG1_RD2PRE_MASK                              0x00001F00U

/*
* tRC: Minimum time between activates to same bank. For configurations wit
    * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege
    * r value. Unit: Clocks.
*/
#undef DDRC_DRAMTMG1_T_RC_DEFVAL 
#undef DDRC_DRAMTMG1_T_RC_SHIFT 
#undef DDRC_DRAMTMG1_T_RC_MASK 
#define DDRC_DRAMTMG1_T_RC_DEFVAL                              0x00080414
#define DDRC_DRAMTMG1_T_RC_SHIFT                               0
#define DDRC_DRAMTMG1_T_RC_MASK                                0x0000007FU

/*
* Set to WL Time from write command to write data on SDRAM interface. This
    *  must be set to WL. For mDDR, it should normally be set to 1. Note that,
    *  depending on the PHY, if using RDIMM, it may be necessary to use a valu
    * e of WL + 1 to compensate for the extra cycle of latency through the RDI
    * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate
    * d using the above equation by 2, and round it up to next integer. This r
    * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING
    *  is set), as the DFI read and write latencies defined in DFITMG0 and DFI
    * TMG1 are sufficient for those protocols Unit: clocks
*/
#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 
#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 
#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK 
#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL                     0x0305060D
#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT                      24
#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK                       0x3F000000U

/*
* Set to RL Time from read command to read data on SDRAM interface. This m
    * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma
    * t be necessary to use a value of RL + 1 to compensate for the extra cycl
    * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2
    * , divide the value calculated using the above equation by 2, and round i
    * t up to next integer. This register field is not required for DDR2 and D
    * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie
    * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit
    * : clocks
*/
#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 
#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT 
#undef DDRC_DRAMTMG2_READ_LATENCY_MASK 
#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL                      0x0305060D
#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT                       16
#define DDRC_DRAMTMG2_READ_LATENCY_MASK                        0x003F0000U

/*
* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L
    * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di
    * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL
    *  LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL
    * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write
    *  command. Include time for bus turnaround and all per-bank, per-rank, an
    * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b
    * urst length. This must match the value programmed in the BL bit of the m
    * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL
    * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE =
    * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d
    * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should
    * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal
    * culated using the above equation by 2, and round it up to next integer.
*/
#undef DDRC_DRAMTMG2_RD2WR_DEFVAL 
#undef DDRC_DRAMTMG2_RD2WR_SHIFT 
#undef DDRC_DRAMTMG2_RD2WR_MASK 
#define DDRC_DRAMTMG2_RD2WR_DEFVAL                             0x0305060D
#define DDRC_DRAMTMG2_RD2WR_SHIFT                              8
#define DDRC_DRAMTMG2_RD2WR_MASK                               0x00003F00U

/*
* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu
    * m time from write command to read command for same bank group. In others
    * , minimum time from write command to read command. Includes time for bus
    *  turnaround, recovery times, and all per-bank, per-rank, and global cons
    * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la
    * tency - BL = burst length. This must match the value programmed in the B
    * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea
    * d command delay for same bank group. This comes directly from the SDRAM
    * specification. - tWTR = internal write to read command delay. This comes
    *  directly from the SDRAM specification. Add one extra cycle for LPDDR2/L
    * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid
    * e the value calculated using the above equation by 2, and round it up to
    *  next integer.
*/
#undef DDRC_DRAMTMG2_WR2RD_DEFVAL 
#undef DDRC_DRAMTMG2_WR2RD_SHIFT 
#undef DDRC_DRAMTMG2_WR2RD_MASK 
#define DDRC_DRAMTMG2_WR2RD_DEFVAL                             0x0305060D
#define DDRC_DRAMTMG2_WR2RD_SHIFT                              0
#define DDRC_DRAMTMG2_WR2RD_MASK                               0x0000003FU

/*
* Time to wait after a mode register write or read (MRW or MRR). Present o
    * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty
    * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD
    * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist
    * er is used for the time from a MRW/MRR to all other commands. For LDPDR3
    * , this register is used for the time from a MRW/MRR to a MRW/MRR.
*/
#undef DDRC_DRAMTMG3_T_MRW_DEFVAL 
#undef DDRC_DRAMTMG3_T_MRW_SHIFT 
#undef DDRC_DRAMTMG3_T_MRW_MASK 
#define DDRC_DRAMTMG3_T_MRW_DEFVAL                             0x0050400C
#define DDRC_DRAMTMG3_T_MRW_SHIFT                              20
#define DDRC_DRAMTMG3_T_MRW_MASK                               0x3FF00000U

/*
* tMRD: Cycles to wait after a mode register write or read. Depending on t
    * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com
    * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim
    * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2,
    *  program this to (tMRD/2) and round it up to the next integer value. If
    * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
*/
#undef DDRC_DRAMTMG3_T_MRD_DEFVAL 
#undef DDRC_DRAMTMG3_T_MRD_SHIFT 
#undef DDRC_DRAMTMG3_T_MRD_MASK 
#define DDRC_DRAMTMG3_T_MRD_DEFVAL                             0x0050400C
#define DDRC_DRAMTMG3_T_MRD_SHIFT                              12
#define DDRC_DRAMTMG3_T_MRD_MASK                               0x0003F000U

/*
* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com
    * mand and following non-load mode command. If C/A parity for DDR4 is used
    * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or
    *  tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if
    * using RDIMM, depending on the PHY, it may be necessary to use a value of
    *  tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a
    * pplied to mode register writes by the RDIMM chip.
*/
#undef DDRC_DRAMTMG3_T_MOD_DEFVAL 
#undef DDRC_DRAMTMG3_T_MOD_SHIFT 
#undef DDRC_DRAMTMG3_T_MOD_MASK 
#define DDRC_DRAMTMG3_T_MOD_DEFVAL                             0x0050400C
#define DDRC_DRAMTMG3_T_MOD_SHIFT                              0
#define DDRC_DRAMTMG3_T_MOD_MASK                               0x000003FFU

/*
* tRCD - tAL: Minimum time from activate to read or write command to same
    * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD
    * - tAL)/2) and round it up to the next integer value. Minimum value allow
    * ed for this register is 1, which implies minimum (tRCD - tAL) value to b
    * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
*/
#undef DDRC_DRAMTMG4_T_RCD_DEFVAL 
#undef DDRC_DRAMTMG4_T_RCD_SHIFT 
#undef DDRC_DRAMTMG4_T_RCD_MASK 
#define DDRC_DRAMTMG4_T_RCD_DEFVAL                             0x05040405
#define DDRC_DRAMTMG4_T_RCD_SHIFT                              24
#define DDRC_DRAMTMG4_T_RCD_MASK                               0x1F000000U

/*
* DDR4: tCCD_L: This is the minimum time between two reads or two writes f
    * or same bank group. Others: tCCD: This is the minimum time between two r
    * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t
    * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U
    * nit: clocks.
*/
#undef DDRC_DRAMTMG4_T_CCD_DEFVAL 
#undef DDRC_DRAMTMG4_T_CCD_SHIFT 
#undef DDRC_DRAMTMG4_T_CCD_MASK 
#define DDRC_DRAMTMG4_T_CCD_DEFVAL                             0x05040405
#define DDRC_DRAMTMG4_T_CCD_SHIFT                              16
#define DDRC_DRAMTMG4_T_CCD_MASK                               0x000F0000U

/*
* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f
    * or same bank group. Others: tRRD: Minimum time between activates from ba
    * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi
    * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni
    * t: Clocks.
*/
#undef DDRC_DRAMTMG4_T_RRD_DEFVAL 
#undef DDRC_DRAMTMG4_T_RRD_SHIFT 
#undef DDRC_DRAMTMG4_T_RRD_MASK 
#define DDRC_DRAMTMG4_T_RRD_DEFVAL                             0x05040405
#define DDRC_DRAMTMG4_T_RRD_SHIFT                              8
#define DDRC_DRAMTMG4_T_RRD_MASK                               0x00000F00U

/*
* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ
    * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM
    * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t
    * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho
    * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
*/
#undef DDRC_DRAMTMG4_T_RP_DEFVAL 
#undef DDRC_DRAMTMG4_T_RP_SHIFT 
#undef DDRC_DRAMTMG4_T_RP_MASK 
#define DDRC_DRAMTMG4_T_RP_DEFVAL                              0x05040405
#define DDRC_DRAMTMG4_T_RP_SHIFT                               0
#define DDRC_DRAMTMG4_T_RP_MASK                                0x0000001FU

/*
* This is the time before Self Refresh Exit that CK is maintained as a val
    * id clock before issuing SRX. Specifies the clock stable time before SRX.
    *  Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK
    * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_
    * FREQ_RATIO=2, program this to recommended value divided by two and round
    *  it up to next integer.
*/
#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL 
#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT 
#undef DDRC_DRAMTMG5_T_CKSRX_MASK 
#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL                           0x05050403
#define DDRC_DRAMTMG5_T_CKSRX_SHIFT                            24
#define DDRC_DRAMTMG5_T_CKSRX_MASK                             0x0F000000U

/*
* This is the time after Self Refresh Down Entry that CK is maintained as
    * a valid clock. Specifies the clock disable delay after SRE. Recommended
    * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1
    * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations
    *  with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw
    * o and round it up to next integer.
*/
#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL 
#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT 
#undef DDRC_DRAMTMG5_T_CKSRE_MASK 
#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL                           0x05050403
#define DDRC_DRAMTMG5_T_CKSRE_SHIFT                            16
#define DDRC_DRAMTMG5_T_CKSRE_MASK                             0x000F0000U

/*
* Minimum CKE low width for Self refresh or Self refresh power down entry
    * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF
    * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2:
    * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ
    * _RATIO=2, program this to recommended value divided by two and round it
    * up to next integer.
*/
#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL 
#undef DDRC_DRAMTMG5_T_CKESR_SHIFT 
#undef DDRC_DRAMTMG5_T_CKESR_MASK 
#define DDRC_DRAMTMG5_T_CKESR_DEFVAL                           0x05050403
#define DDRC_DRAMTMG5_T_CKESR_SHIFT                            8
#define DDRC_DRAMTMG5_T_CKESR_MASK                             0x00003F00U

/*
* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr
    * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP
    * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/
    * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration
    * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and
    * round it up to the next integer value. Unit: Clocks.
*/
#undef DDRC_DRAMTMG5_T_CKE_DEFVAL 
#undef DDRC_DRAMTMG5_T_CKE_SHIFT 
#undef DDRC_DRAMTMG5_T_CKE_MASK 
#define DDRC_DRAMTMG5_T_CKE_DEFVAL                             0x05050403
#define DDRC_DRAMTMG5_T_CKE_SHIFT                              0
#define DDRC_DRAMTMG5_T_CKE_MASK                               0x0000001FU

/*
* This is the time after Deep Power Down Entry that CK is maintained as a
    * valid clock. Specifies the clock disable delay after DPDE. Recommended s
    * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_
    * FREQ_RATIO=2, program this to recommended value divided by two and round
    *  it up to next integer. This is only present for designs supporting mDDR
    *  or LPDDR2/LPDDR3 devices.
*/
#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 
#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT 
#undef DDRC_DRAMTMG6_T_CKDPDE_MASK 
#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL                          0x02020005
#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT                           24
#define DDRC_DRAMTMG6_T_CKDPDE_MASK                            0x0F000000U

/*
* This is the time before Deep Power Down Exit that CK is maintained as a
    * valid clock before issuing DPDX. Specifies the clock stable time before
    * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config
    * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid
    * ed by two and round it up to next integer. This is only present for desi
    * gns supporting mDDR or LPDDR2 devices.
*/
#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 
#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT 
#undef DDRC_DRAMTMG6_T_CKDPDX_MASK 
#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL                          0x02020005
#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT                           16
#define DDRC_DRAMTMG6_T_CKDPDX_MASK                            0x000F0000U

/*
* This is the time before Clock Stop Exit that CK is maintained as a valid
    *  clock before issuing Clock Stop Exit. Specifies the clock stable time b
    * efore next command after Clock Stop Exit. Recommended settings: - mDDR:
    * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio
    * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by
    * two and round it up to next integer. This is only present for designs su
    * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL 
#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT 
#undef DDRC_DRAMTMG6_T_CKCSX_MASK 
#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL                           0x02020005
#define DDRC_DRAMTMG6_T_CKCSX_SHIFT                            0
#define DDRC_DRAMTMG6_T_CKCSX_MASK                             0x0000000FU

/*
* This is the time after Power Down Entry that CK is maintained as a valid
    *  clock. Specifies the clock disable delay after PDE. Recommended setting
    * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration
    * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t
    * wo and round it up to next integer. This is only present for designs sup
    * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL 
#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT 
#undef DDRC_DRAMTMG7_T_CKPDE_MASK 
#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL                           0x00000202
#define DDRC_DRAMTMG7_T_CKPDE_SHIFT                            8
#define DDRC_DRAMTMG7_T_CKPDE_MASK                             0x00000F00U

/*
* This is the time before Power Down Exit that CK is maintained as a valid
    *  clock before issuing PDX. Specifies the clock stable time before PDX. R
    * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c
    * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value
    * divided by two and round it up to next integer. This is only present for
    *  designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL 
#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT 
#undef DDRC_DRAMTMG7_T_CKPDX_MASK 
#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL                           0x00000202
#define DDRC_DRAMTMG7_T_CKPDX_SHIFT                            0
#define DDRC_DRAMTMG7_T_CKPDX_MASK                             0x0000000FU

/*
* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and
    * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this
    * to the above value divided by 2 and round up to next integer value. Unit
    * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com
    * mands. Note: Ensure this is less than or equal to t_xs_x32.
*/
#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 
#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 
#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 
#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL                     0x03034405
#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT                      24
#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK                       0x7F000000U

/*
* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S
    * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th
    * is to the above value divided by 2 and round up to next integer value. U
    * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to
    * t_xs_x32.
*/
#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 
#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 
#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 
#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL                    0x03034405
#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT                     16
#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK                      0x007F0000U

/*
* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config
    * urations with MEMC_FREQ_RATIO=2, program this to the above value divided
    *  by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
    * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
*/
#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 
#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 
#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 
#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL                      0x03034405
#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT                       8
#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK                        0x00007F00U

/*
* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi
    * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide
    * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
    *  Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
*/
#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL 
#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT 
#undef DDRC_DRAMTMG8_T_XS_X32_MASK 
#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL                          0x03034405
#define DDRC_DRAMTMG8_T_XS_X32_SHIFT                           0
#define DDRC_DRAMTMG8_T_XS_X32_MASK                            0x0000007FU

/*
* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o
    * nly with MEMC_FREQ_RATIO=2
*/
#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 
#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 
#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 
#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL                  0x0004040D
#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT                   30
#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK                    0x40000000U

/*
* tCCD_S: This is the minimum time between two reads or two writes for dif
    * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m
    * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2
    * , program this to (tCCD_S/2) and round it up to the next integer value.
    * Present only in designs configured to support DDR4. Unit: clocks.
*/
#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL 
#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT 
#undef DDRC_DRAMTMG9_T_CCD_S_MASK 
#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL                           0x0004040D
#define DDRC_DRAMTMG9_T_CCD_S_SHIFT                            16
#define DDRC_DRAMTMG9_T_CCD_S_MASK                             0x00070000U

/*
* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif
    * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th
    * is to (tRRD_S/2) and round it up to the next integer value. Present only
    *  in designs configured to support DDR4. Unit: Clocks.
*/
#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL 
#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT 
#undef DDRC_DRAMTMG9_T_RRD_S_MASK 
#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL                           0x0004040D
#define DDRC_DRAMTMG9_T_RRD_S_SHIFT                            8
#define DDRC_DRAMTMG9_T_RRD_S_MASK                             0x00000F00U

/*
* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command
    *  for different bank group. Includes time for bus turnaround, recovery ti
    * mes, and all per-bank, per-rank, and global constraints. Present only in
    *  designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr
    * ite latency - PL = Parity latency - BL = burst length. This must match t
    * he value programmed in the BL bit of the mode register to the SDRAM - tW
    * TR_S = internal write to read command delay for different bank group. Th
    * is comes directly from the SDRAM specification. For configurations with
    * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation
    * by 2, and round it up to next integer.
*/
#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL 
#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT 
#undef DDRC_DRAMTMG9_WR2RD_S_MASK 
#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL                           0x0004040D
#define DDRC_DRAMTMG9_WR2RD_S_SHIFT                            0
#define DDRC_DRAMTMG9_WR2RD_S_MASK                             0x0000003FU

/*
* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL
    * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2
    * ) and round it up to the next integer value. Present only in designs con
    * figured to support DDR4. Unit: Multiples of 32 clocks.
*/
#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 
#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 
#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 
#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL                0x440C021C
#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT                 24
#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK                  0x7F000000U

/*
* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For
    * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2
    * )+1. Present only in designs configured to support DDR4. Unit: clocks.
*/
#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 
#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT 
#undef DDRC_DRAMTMG11_T_MPX_LH_MASK 
#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL                         0x440C021C
#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT                          16
#define DDRC_DRAMTMG11_T_MPX_LH_MASK                           0x001F0000U

/*
* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_
    * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int
    * eger value. Present only in designs configured to support DDR4. Unit: Cl
    * ocks.
*/
#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL 
#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT 
#undef DDRC_DRAMTMG11_T_MPX_S_MASK 
#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL                          0x440C021C
#define DDRC_DRAMTMG11_T_MPX_S_SHIFT                           8
#define DDRC_DRAMTMG11_T_MPX_S_MASK                            0x00000300U

/*
* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i
    * n designs configured to support DDR4. Unit: Clocks. For configurations w
    * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat
    * ion by 2, and round it up to next integer.
*/
#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL 
#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT 
#undef DDRC_DRAMTMG11_T_CKMPE_MASK 
#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL                          0x440C021C
#define DDRC_DRAMTMG11_T_CKMPE_SHIFT                           0
#define DDRC_DRAMTMG11_T_CKMPE_MASK                            0x0000001FU

/*
* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg
    * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr
    * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu
    * e.
*/
#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 
#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT 
#undef DDRC_DRAMTMG12_T_CMDCKE_MASK 
#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL                         0x00020610
#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT                          16
#define DDRC_DRAMTMG12_T_CMDCKE_MASK                           0x00030000U

/*
* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat
    * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u
    * p to next integer value.
*/
#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 
#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 
#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK 
#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL                        0x00020610
#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT                         8
#define DDRC_DRAMTMG12_T_CKEHCMD_MASK                          0x00000F00U

/*
* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.
    * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2)
    * and round it up to next integer value.
*/
#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 
#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 
#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK 
#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL                        0x00020610
#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT                         0
#define DDRC_DRAMTMG12_T_MRD_PDA_MASK                          0x0000001FU

/*
* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg
    * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration
    * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati
    * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre
    * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 
#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 
#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 
#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL                         0x02000040
#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT                          31
#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK                           0x80000000U

/*
* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres
    * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2
    * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio
    * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i
    * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present
    * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 
#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 
#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 
#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL                        0x02000040
#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT                         30
#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK                          0x40000000U

/*
* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC
    * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
    * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co
    * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share
    * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR
    * 3/LPDDR4 devices.
*/
#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 
#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 
#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 
#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL                  0x02000040
#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT                   29
#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK                    0x20000000U

/*
* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit.
    *  Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com
    * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4
    *  mode. This is only present for designs supporting DDR4 devices.
*/
#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 
#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 
#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 
#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL                      0x02000040
#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT                       28
#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK                        0x10000000U

/*
* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe
    * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St
    * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO
    * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int
    * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th
    * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t
    * o the next integer value. Unit: Clock cycles. This is only present for d
    * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 
#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 
#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 
#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL                       0x02000040
#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT                        16
#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK                         0x07FF0000U

/*
* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of
    *  NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command
    * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t
    * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy
    * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP
    * DDR3/LPDDR4 devices.
*/
#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 
#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 
#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 
#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL                      0x02000040
#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT                       0
#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK                        0x000003FFU

/*
* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati
    * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_
    * RATIO=2, program this to tZQReset/2 and round it up to the next integer
    * value. Unit: Clock cycles. This is only present for designs supporting L
    * PDDR2/LPDDR3/LPDDR4 devices.
*/
#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 
#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 
#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 
#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL                      0x02000100
#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT                       20
#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK                        0x3FF00000U

/*
* Average interval to wait between automatically issuing ZQCS (ZQ calibrat
    * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR
    * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles
    * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3
    * /LPDDR4 devices.
*/
#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 
#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 
#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 
#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL           0x02000100
#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT            0
#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK             0x000FFFFFU

/*
* Specifies the number of DFI clock cycles after an assertion or de-assert
    * ion of the DFI control signals that the control signals at the PHY-DRAM
    * interface reflect the assertion or de-assertion. If the DFI clock and th
    * e memory clock are not phase-aligned, this timing parameter should be ro
    * unded up to the next integer value. Note that if using RDIMM, it is nece
    * ssary to increment this parameter by RDIMM's extra cycle of latency in t
    * erms of DFI clock.
*/
#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 
#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 
#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 
#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL                   0x07020002
#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT                    24
#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK                     0x1F000000U

/*
* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
    * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
    * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
    *  - 1 in terms of SDR clock cycles Refer to PHY specification for correct
    *  value.
*/
#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 
#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 
#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 
#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL                 0x07020002
#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT                  23
#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK                   0x00800000U

/*
* Time from the assertion of a read command on the DFI interface to the as
    * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
    * ect value. This corresponds to the DFI parameter trddata_en. Note that,
    * depending on the PHY, if using RDIMM, it may be necessary to use the val
    * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
    * the extra cycle of latency through the RDIMM. Unit: Clocks
*/
#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 
#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 
#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 
#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL                    0x07020002
#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT                     16
#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK                      0x003F0000U

/*
* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
    * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
    *  in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
    * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
    *  clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
    * n for correct value.
*/
#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 
#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 
#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 
#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL                 0x07020002
#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT                  15
#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK                   0x00008000U

/*
* Specifies the number of clock cycles between when dfi_wrdata_en is asser
    * ted to when the associated write data is driven on the dfi_wrdata signal
    * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
    *  specification for correct value. Note, max supported value is 8. Unit:
    * Clocks
*/
#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 
#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 
#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 
#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL                    0x07020002
#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT                     8
#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK                      0x00003F00U

/*
* Write latency Number of clocks from the write command to write data enab
    * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
    * lat. Refer to PHY specification for correct value.Note that, depending o
    * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
    *  in the calculation of tphy_wrlat. This is to compensate for the extra c
    * ycle of latency through the RDIMM.
*/
#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 
#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 
#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 
#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL                     0x07020002
#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT                      0
#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK                       0x0000003FU

/*
* Specifies the number of DFI PHY clocks between when the dfi_cs signal is
    *  asserted and when the associated command is driven. This field is used
    * for CAL mode, should be set to '0' or the value which matches the CAL mo
    * de register setting in the DRAM. If the PHY can add the latency for CAL
    * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
*/
#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 
#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 
#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 
#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL                      0x00000404
#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT                       28
#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK                        0xF0000000U

/*
* Specifies the number of DFI PHY clocks between when the dfi_cs signal is
    *  asserted and when the associated dfi_parity_in signal is driven.
*/
#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 
#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 
#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 
#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL                    0x00000404
#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT                     24
#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK                      0x03000000U

/*
* Specifies the number of DFI clocks between when the dfi_wrdata_en signal
    *  is asserted and when the corresponding write data transfer is completed
    *  on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d
    * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set
    *  to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI
    *  2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va
    * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_
    * RATIO=2, divide PHY's value by 2 and round up to next integer. If using
    * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
*/
#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 
#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 
#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 
#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL                 0x00000404
#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT                  16
#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK                   0x001F0000U

/*
* Specifies the number of DFI clock cycles from the assertion of the dfi_d
    * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev
    * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock
    * and the memory clock are not phase aligned, this timing parameter should
    *  be rounded up to the next integer value.
*/
#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 
#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 
#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL             0x00000404
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT              8
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK               0x00000F00U

/*
* Specifies the number of DFI clock cycles from the de-assertion of the df
    * i_dram_clk_disable signal on the DFI until the first valid rising edge o
    * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the
    *  DFI clock and the memory clock are not phase aligned, this timing param
    * eter should be rounded up to the next integer value.
*/
#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 
#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 
#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL              0x00000404
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT               0
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK                0x0000000FU

/*
* Setting for DFI's tlp_resp time. Same value is used for both Power Down,
    *  Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s
    * pecification onwards, recommends using a fixed value of 7 always.
*/
#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 
#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 
#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 
#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL                     0x07000000
#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT                      24
#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK                       0x0F000000U

/*
* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente
    * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32
    * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5
    * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles -
    * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553
    * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T
    * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices
    * .
*/
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL                0x07000000
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT                 20
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK                  0x00F00000U

/*
* Enables DFI Low Power interface handshaking during Deep Power Down Entry
    * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup
    * porting mDDR or LPDDR2/LPDDR3 devices.
*/
#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 
#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 
#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 
#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL                    0x07000000
#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT                     16
#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK                      0x00010000U

/*
* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered
    * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc
    * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512
    * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9
    *  - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c
    * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
*/
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL                 0x07000000
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT                  12
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK                   0x0000F000U

/*
* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex
    * it. - 0 - Disabled - 1 - Enabled
*/
#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 
#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 
#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 
#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL                     0x07000000
#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT                      8
#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK                       0x00000100U

/*
* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered.
    * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle
    * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy
    * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 -
    *  8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc
    * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
*/
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 
#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL                 0x07000000
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT                  4
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK                   0x000000F0U

/*
* Enables DFI Low Power interface handshaking during Power Down Entry/Exit
    * . - 0 - Disabled - 1 - Enabled
*/
#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 
#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 
#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 
#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL                     0x07000000
#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT                      0
#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK                       0x00000001U

/*
* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is
    *  entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1
    * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x
    * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl
    * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC -
    *  65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi
    * ted This is only present for designs supporting DDR4 devices.
*/
#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 
#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 
#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 
#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL               0x00000000
#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT                4
#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK                 0x000000F0U

/*
* Enables DFI Low Power interface handshaking during Maximum Power Saving
    * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d
    * esigns supporting DDR4 devices.
*/
#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 
#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 
#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 
#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL                   0x00000000
#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT                    0
#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK                     0x00000001U

/*
* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
    * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc
    * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically.
*/
#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 
#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 
#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL                   0x00400003
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT                    31
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK                     0x80000000U

/*
* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
    *  following a self-refresh exit. The core must issue the dfi_ctrlupd_req
    * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct
    * rlupd_req after exiting self-refresh.
*/
#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 
#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 
#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL               0x00400003
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT                30
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK                 0x40000000U

/*
* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si
    * gnal can assert. Lowest value to assign to this variable is 0x40. Unit:
    * Clocks
*/
#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 
#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 
#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL                   0x00400003
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT                    16
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK                     0x03FF0000U

/*
* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si
    * gnal must be asserted. The uMCTL2 expects the PHY to respond within this
    *  time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup
    * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this
    * variable is 0x3. Unit: Clocks
*/
#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 
#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 
#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL                   0x00400003
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT                    0
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK                     0x000003FFU

/*
* This is the minimum amount of time between uMCTL2 initiated DFI update r
    * equests (which is executed whenever the uMCTL2 is idle). Set this number
    *  higher to reduce the frequency of update requests, which can have a sma
    * ll impact on the latency of the first read request when the uMCTL2 is id
    * le. Unit: 1024 clocks
*/
#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 
#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 
#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL   0x00000000
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT    16
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK     0x00FF0000U

/*
* This is the maximum amount of time between uMCTL2 initiated DFI update r
    * equests. This timer resets with each update request; when the timer expi
    * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd
    * _ackx is received. PHY can use this idle time to recalibrate the delay l
    * ines to the DLLs. The DFI controller update is also used to reset PHY FI
    * FO pointers in case of data capture errors. Updates are required to main
    * tain calibration over PVT, but frequent updates may impact performance.
    * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must
    *  be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl
    * ocks
*/
#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 
#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 
#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL   0x00000000
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT    0
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK     0x000000FFU

/*
* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal
    * s are active low - 1: Signals are active high
*/
#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 
#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 
#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 
#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL               0x00000001
#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT                2
#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK                 0x00000004U

/*
* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality.
    *  - 1 - PHY implements DBI functionality. Present only in designs configu
    * red to support DDR4 and LPDDR4.
*/
#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 
#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 
#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK 
#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL                       0x00000001
#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT                        1
#define DDRC_DFIMISC_PHY_DBI_MODE_MASK                         0x00000002U

/*
* PHY initialization complete enable signal. When asserted the dfi_init_co
    * mplete signal can be used to trigger SDRAM initialisation
*/
#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 
#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 
#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 
#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL               0x00000001
#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT                0
#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK                 0x00000001U

/*
* >Number of clocks between when a read command is sent on the DFI control
    *  interface and when the associated dfi_rddata_cs signal is asserted. Thi
    * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe
    * cification for correct value.
*/
#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 
#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 
#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 
#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL                   0x00000202
#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT                    8
#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK                     0x00003F00U

/*
* Number of clocks between when a write command is sent on the DFI control
    *  interface and when the associated dfi_wrdata_cs signal is asserted. Thi
    * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe
    * cification for correct value.
*/
#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 
#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 
#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 
#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL                   0x00000202
#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT                    0
#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK                     0x0000003FU

/*
* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D
    * BI is enabled. This signal must be set the same value as DRAM's mode reg
    * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b
    * e set to 0. - LPDDR4: MR3[6]
*/
#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL 
#undef DDRC_DBICTL_RD_DBI_EN_SHIFT 
#undef DDRC_DBICTL_RD_DBI_EN_MASK 
#define DDRC_DBICTL_RD_DBI_EN_DEFVAL                           0x00000001
#define DDRC_DBICTL_RD_DBI_EN_SHIFT                            2
#define DDRC_DBICTL_RD_DBI_EN_MASK                             0x00000004U

/*
* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ
    * e DBI is enabled. This signal must be set the same value as DRAM's mode
    * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus
    * t be set to 0. - LPDDR4: MR3[7]
*/
#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL 
#undef DDRC_DBICTL_WR_DBI_EN_SHIFT 
#undef DDRC_DBICTL_WR_DBI_EN_MASK 
#define DDRC_DBICTL_WR_DBI_EN_DEFVAL                           0x00000001
#define DDRC_DBICTL_WR_DBI_EN_SHIFT                            1
#define DDRC_DBICTL_WR_DBI_EN_MASK                             0x00000002U

/*
* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi
    * s signal must be set the same logical value as DRAM's mode register. - D
    * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th
    * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13
    * [5] which is opposite polarity from this signal
*/
#undef DDRC_DBICTL_DM_EN_DEFVAL 
#undef DDRC_DBICTL_DM_EN_SHIFT 
#undef DDRC_DBICTL_DM_EN_MASK 
#define DDRC_DBICTL_DM_EN_DEFVAL                               0x00000001
#define DDRC_DBICTL_DM_EN_SHIFT                                0
#define DDRC_DBICTL_DM_EN_MASK                                 0x00000001U

/*
* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t
    * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined
    *  by adding the internal base to the value of this field. If set to 31, r
    * ank address bit 0 is set to 0.
*/
#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL 
#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 
#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 
#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL                   
#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT                    0
#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK                     0x0000001FU

/*
* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t
    * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined
    * by adding the internal base to the value of this field. If set to 31, ba
    * nk address bit 2 is set to 0.
*/
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL                   0x00000000
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT                    16
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK                     0x001F0000U

/*
* Selects the HIF address bits used as bank address bit 1. Valid Range: 0
    * to 30 Internal Base: 3 The selected HIF address bit for each of the bank
    *  address bits is determined by adding the internal base to the value of
    * this field.
*/
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL                   0x00000000
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT                    8
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK                     0x00001F00U

/*
* Selects the HIF address bits used as bank address bit 0. Valid Range: 0
    * to 30 Internal Base: 2 The selected HIF address bit for each of the bank
    *  address bits is determined by adding the internal base to the value of
    * this field.
*/
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 
#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL                   0x00000000
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT                    0
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK                     0x0000001FU

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu
    * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit
    * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base
    * : 5 The selected HIF address bit is determined by adding the internal ba
    * se to the value of this field. If set to 15, this column address bit is
    * set to 0.
*/
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 
#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL                    0x00000000
#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT                     24
#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK                      0x0F000000U

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu
    * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit
    * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base:
    *  4 The selected HIF address bit is determined by adding the internal bas
    * e to the value of this field. If set to 15, this column address bit is s
    * et to 0.
*/
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 
#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL                    0x00000000
#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT                     16
#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK                      0x000F0000U

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu
    * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit
    * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s
    * elected HIF address bit is determined by adding the internal base to the
    *  value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1
    * 6, it is required to program this to 0, hence register does not exist in
    *  this case.
*/
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 
#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL                    0x00000000
#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT                     8
#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK                      0x00000F00U

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu
    * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit
    * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s
    * elected HIF address bit is determined by adding the internal base to the
    *  value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
    *  or 16, it is required to program this to 0.
*/
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 
#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 
#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL                    0x00000000
#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT                     0
#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK                      0x0000000FU

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu
    * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode:
    * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/
    * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
    * HIF address bit is determined by adding the internal base to the value o
    * f this field. If set to 15, this column address bit is set to 0. Note: P
    * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo
    * r indicating auto-precharge, and hence no source address bit can be mapp
    * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit
    * for auto-precharge in the CA bus and hence column bit 10 is used.
*/
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 
#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL                    0x00000000
#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT                     24
#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK                      0x0F000000U

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu
    * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit
    * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0
    *  to 7, and 15 Internal Base: 8 The selected HIF address bit is determine
    * d by adding the internal base to the value of this field. If set to 15,
    * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi
    * cation, column address bit 10 is reserved for indicating auto-precharge,
    *  and hence no source address bit can be mapped to column address bit 10.
    *  In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA
    *  bus and hence column bit 10 is used.
*/
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 
#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL                    0x00000000
#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT                     16
#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK                      0x000F0000U

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu
    * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit
    * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base:
    *  7 The selected HIF address bit is determined by adding the internal bas
    * e to the value of this field. If set to 15, this column address bit is s
    * et to 0.
*/
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 
#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL                    0x00000000
#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT                     8
#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK                      0x00000F00U

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu
    * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit
    * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base:
    *  6 The selected HIF address bit is determined by adding the internal bas
    * e to the value of this field. If set to 15, this column address bit is s
    * et to 0.
*/
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 
#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 
#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL                    0x00000000
#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT                     0
#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK                      0x0000000FU

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m
    * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un
    * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7,
    *  and 15 Internal Base: 11 The selected HIF address bit is determined by
    * adding the internal base to the value of this field. If set to 15, this
    * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio
    * n, column address bit 10 is reserved for indicating auto-precharge, and
    * hence no source address bit can be mapped to column address bit 10. In L
    * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus
    * and hence column bit 10 is used.
*/
#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 
#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 
#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 
#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL                   0x00000000
#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT                    8
#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK                     0x00000F00U

/*
* - Full bus width mode: Selects the HIF address bit used as column addres
    * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the
    * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)
    * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied
    *  to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
    *  address bit is determined by adding the internal base to the value of t
    * his field. If set to 15, this column address bit is set to 0. Note: Per
    * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i
    * ndicating auto-precharge, and hence no source address bit can be mapped
    * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
    *  auto-precharge in the CA bus and hence column bit 10 is used.
*/
#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 
#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 
#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 
#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL                   0x00000000
#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT                    0
#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK                     0x0000000FU

/*
* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t
    * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine
    * d by adding the internal base to the value of this field. If set to 15,
    * row address bit 11 is set to 0.
*/
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL                   0x00000000
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT                    24
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK                     0x0F000000U

/*
* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran
    * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row
    *  address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro
    * w address bit 10) The selected HIF address bit for each of the row addre
    * ss bits is determined by adding the internal base to the value of this f
    * ield. When value 15 is used the values of row address bits 2 to 10 are d
    * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
*/
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL                 0x00000000
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT                  16
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK                   0x000F0000U

/*
* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t
    * o 11 Internal Base: 7 The selected HIF address bit for each of the row a
    * ddress bits is determined by adding the internal base to the value of th
    * is field.
*/
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL                    0x00000000
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT                     8
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK                      0x00000F00U

/*
* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t
    * o 11 Internal Base: 6 The selected HIF address bit for each of the row a
    * ddress bits is determined by adding the internal base to the value of th
    * is field.
*/
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 
#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL                    0x00000000
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT                     0
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK                      0x0000000FU

/*
* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1
    *  - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]=
    * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use.
    *  All addresses are valid Present only in designs configured to support L
    * PDDR3.
*/
#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 
#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 
#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 
#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL                   0x00000000
#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT                    31
#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK                     0x80000000U

/*
* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t
    * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine
    * d by adding the internal base to the value of this field. If set to 15,
    * row address bit 15 is set to 0.
*/
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL                   0x00000000
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT                    24
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK                     0x0F000000U

/*
* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t
    * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine
    * d by adding the internal base to the value of this field. If set to 15,
    * row address bit 14 is set to 0.
*/
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL                   0x00000000
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT                    16
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK                     0x000F0000U

/*
* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t
    * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine
    * d by adding the internal base to the value of this field. If set to 15,
    * row address bit 13 is set to 0.
*/
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL                   0x00000000
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT                    8
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK                     0x00000F00U

/*
* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t
    * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine
    * d by adding the internal base to the value of this field. If set to 15,
    * row address bit 12 is set to 0.
*/
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 
#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL                   0x00000000
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT                    0
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK                     0x0000000FU

/*
* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t
    * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine
    * d by adding the internal base to the value of this field. If set to 15,
    * row address bit 17 is set to 0.
*/
#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 
#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 
#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL                   0x00000000
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT                    8
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK                     0x00000F00U

/*
* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t
    * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine
    * d by adding the internal base to the value of this field. If set to 15,
    * row address bit 16 is set to 0.
*/
#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 
#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 
#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL                   0x00000000
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT                    0
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK                     0x0000000FU

/*
* Selects the HIF address bits used as bank group address bit 1. Valid Ran
    * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea
    * ch of the bank group address bits is determined by adding the internal b
    * ase to the value of this field. If set to 31, bank group address bit 1 i
    * s set to 0.
*/
#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 
#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 
#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 
#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL                     0x00000000
#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT                      8
#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK                       0x00001F00U

/*
* Selects the HIF address bits used as bank group address bit 0. Valid Ran
    * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th
    * e bank group address bits is determined by adding the internal base to t
    * he value of this field.
*/
#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 
#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 
#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 
#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL                     0x00000000
#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT                      0
#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK                       0x0000001FU

/*
* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t
    * o 11 Internal Base: 11 The selected HIF address bit for each of the row
    * address bits is determined by adding the internal base to the value of t
    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
    * _10 is set to value 15.
*/
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL                    0x00000000
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT                     24
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK                      0x0F000000U

/*
* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t
    * o 11 Internal Base: 10 The selected HIF address bit for each of the row
    * address bits is determined by adding the internal base to the value of t
    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
    * _10 is set to value 15.
*/
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL                    0x00000000
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT                     16
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK                      0x000F0000U

/*
* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t
    * o 11 Internal Base: 9 The selected HIF address bit for each of the row a
    * ddress bits is determined by adding the internal base to the value of th
    * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
    * 10 is set to value 15.
*/
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL                    0x00000000
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT                     8
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK                      0x00000F00U

/*
* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t
    * o 11 Internal Base: 8 The selected HIF address bit for each of the row a
    * ddress bits is determined by adding the internal base to the value of th
    * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
    * 10 is set to value 15.
*/
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 
#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL                    0x00000000
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT                     0
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK                      0x0000000FU

/*
* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t
    * o 11 Internal Base: 15 The selected HIF address bit for each of the row
    * address bits is determined by adding the internal base to the value of t
    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
    * _10 is set to value 15.
*/
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL                   0x00000000
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT                    24
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK                     0x0F000000U

/*
* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t
    * o 11 Internal Base: 14 The selected HIF address bit for each of the row
    * address bits is determined by adding the internal base to the value of t
    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
    * _10 is set to value 15.
*/
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL                   0x00000000
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT                    16
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK                     0x000F0000U

/*
* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t
    * o 11 Internal Base: 13 The selected HIF address bit for each of the row
    * address bits is determined by adding the internal base to the value of t
    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
    * _10 is set to value 15.
*/
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL                   0x00000000
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT                    8
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK                     0x00000F00U

/*
* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t
    * o 11 Internal Base: 12 The selected HIF address bit for each of the row
    * address bits is determined by adding the internal base to the value of t
    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
    * _10 is set to value 15.
*/
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 
#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL                   0x00000000
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT                    0
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK                     0x0000000FU

/*
* Selects the HIF address bits used as row address bit 10. Valid Range: 0
    * to 11 Internal Base: 16 The selected HIF address bit for each of the row
    *  address bits is determined by adding the internal base to the value of
    * this field. This register field is used only when ADDRMAP5.addrmap_row_b
    * 2_10 is set to value 15.
*/
#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL 
#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 
#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 
#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL                  
#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT                   0
#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK                    0x0000000FU

/*
* Cycles to hold ODT for a write command. The minimum supported value is 2
    * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800
    * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D
    * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR
    * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (
    * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
*/
#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 
#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 
#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK 
#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL                         0x04000400
#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT                          24
#define DDRC_ODTCFG_WR_ODT_HOLD_MASK                           0x0F000000U

/*
* The delay, in clock cycles, from issuing a write command to setting ODT
    * values associated with that command. ODT setting must remain constant fo
    * r the entire time that DQS is driven by the uMCTL2. Recommended values:
    * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL +
    * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo
    * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust
    * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
*/
#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 
#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 
#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK 
#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL                        0x04000400
#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT                         16
#define DDRC_ODTCFG_WR_ODT_DELAY_MASK                          0x001F0000U

/*
* Cycles to hold ODT for a read command. The minimum supported value is 2.
    *  Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) -
    *  BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8
    * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p
    * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) +
    * RU(tODTon(max)/tCK)
*/
#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 
#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 
#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK 
#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL                         0x04000400
#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT                          8
#define DDRC_ODTCFG_RD_ODT_HOLD_MASK                           0x00000F00U

/*
* The delay, in clock cycles, from issuing a read command to setting ODT v
    * alues associated with that command. ODT setting must remain constant for
    *  the entire time that DQS is driven by the uMCTL2. Recommended values: D
    * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL
    * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C
    * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat
    * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
    * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre
    * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su
    * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R
    * U(tODTon(max)/tCK)
*/
#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 
#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 
#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK 
#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL                        0x04000400
#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT                         2
#define DDRC_ODTCFG_RD_ODT_DELAY_MASK                          0x0000007CU

/*
* Indicates which remote ODTs must be turned on during a read from rank 1.
    *  Each rank has a remote ODT (in the SDRAM) which can be turned on by set
    * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
    * s controlled by bit next to the LSB, etc. For each rank, set its bit to
    * 1 to enable its ODT. Present only in configurations that have 2 or more
    * ranks
*/
#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 
#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 
#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK 
#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL                        0x00002211
#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT                         12
#define DDRC_ODTMAP_RANK1_RD_ODT_MASK                          0x00003000U

/*
* Indicates which remote ODTs must be turned on during a write to rank 1.
    * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
    * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
    *  controlled by bit next to the LSB, etc. For each rank, set its bit to 1
    *  to enable its ODT. Present only in configurations that have 2 or more r
    * anks
*/
#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 
#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 
#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK 
#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL                        0x00002211
#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT                         8
#define DDRC_ODTMAP_RANK1_WR_ODT_MASK                          0x00000300U

/*
* Indicates which remote ODTs must be turned on during a read from rank 0.
    *  Each rank has a remote ODT (in the SDRAM) which can be turned on by set
    * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
    * s controlled by bit next to the LSB, etc. For each rank, set its bit to
    * 1 to enable its ODT.
*/
#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 
#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 
#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK 
#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL                        0x00002211
#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT                         4
#define DDRC_ODTMAP_RANK0_RD_ODT_MASK                          0x00000030U

/*
* Indicates which remote ODTs must be turned on during a write to rank 0.
    * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
    * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
    *  controlled by bit next to the LSB, etc. For each rank, set its bit to 1
    *  to enable its ODT.
*/
#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 
#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 
#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK 
#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL                        0x00002211
#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT                         0
#define DDRC_ODTMAP_RANK0_WR_ODT_MASK                          0x00000003U

/*
* When the preferred transaction store is empty for these many clock cycle
    * s, switch to the alternate transaction store if it is non-empty. The rea
    * d transaction store (both high and low priority) is the default preferre
    * d transaction store and the write transaction store is the alternative s
    * tore. When prefer write over read is set this is reversed. 0x0 is a lega
    * l value for this register. When set to 0x0, the transaction store switch
    * ing will happen immediately when the switching conditions become true. F
    * OR PERFORMANCE ONLY
*/
#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 
#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 
#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK 
#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL                        0x00002005
#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT                         24
#define DDRC_SCHED_RDWR_IDLE_GAP_MASK                          0x7F000000U

/*
* UNUSED
*/
#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 
#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 
#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 
#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL               0x00002005
#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT                16
#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK                 0x00FF0000U

/*
* Number of entries in the low priority transaction store is this value +
    * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent
    * ries available for the high priority transaction store. Setting this to
    * maximum value allocates all entries to low priority transaction store. S
    * etting this to 0 allocates 1 entry to low priority transaction store and
    *  the rest to high priority transaction store. Note: In ECC configuration
    * s, the numbers of write and low priority read credits issued is one less
    *  than in the non-ECC case. One entry each is reserved in the write and l
    * ow-priority read CAMs for storing the RMW requests arising out of single
    *  bit error correction RMW operation.
*/
#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 
#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 
#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK 
#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL                      0x00002005
#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT                       8
#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK                        0x00003F00U

/*
* If true, bank is kept open only while there are page hit transactions av
    * ailable in the CAM to that bank. The last read or write command in the C
    * AM with a bank and page hit will be executed with auto-precharge if SCHE
    * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos
    * e_timer is set to 0, explicit precharge (and not auto-precharge) may be
    * issued in some cases where there is a mode switch between Write and Read
    *  or between LPR and HPR. The Read and Write commands that are executed a
    * s part of the ECC scrub requests are also executed without auto-precharg
    * e. If false, the bank remains open until there is a need to close it (to
    *  open a different page, or for page timeout or refresh timeout) - also k
    * nown as open page policy. The open page policy can be overridden by sett
    * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre).
    * The pageclose feature provids a midway between Open and Close page polic
    * ies. FOR PERFORMANCE ONLY.
*/
#undef DDRC_SCHED_PAGECLOSE_DEFVAL 
#undef DDRC_SCHED_PAGECLOSE_SHIFT 
#undef DDRC_SCHED_PAGECLOSE_MASK 
#define DDRC_SCHED_PAGECLOSE_DEFVAL                            0x00002005
#define DDRC_SCHED_PAGECLOSE_SHIFT                             2
#define DDRC_SCHED_PAGECLOSE_MASK                              0x00000004U

/*
* If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
*/
#undef DDRC_SCHED_PREFER_WRITE_DEFVAL 
#undef DDRC_SCHED_PREFER_WRITE_SHIFT 
#undef DDRC_SCHED_PREFER_WRITE_MASK 
#define DDRC_SCHED_PREFER_WRITE_DEFVAL                         0x00002005
#define DDRC_SCHED_PREFER_WRITE_SHIFT                          1
#define DDRC_SCHED_PREFER_WRITE_MASK                           0x00000002U

/*
* Active low signal. When asserted ('0'), all incoming transactions are fo
    * rced to low priority. This implies that all High Priority Read (HPR) and
    *  Variable Priority Read commands (VPR) will be treated as Low Priority R
    * ead (LPR) commands. On the write side, all Variable Priority Write (VPW)
    *  commands will be treated as Normal Priority Write (NPW) commands. Forci
    * ng the incoming transactions to low priority implicitly turns off Bypass
    *  path for read commands. FOR PERFORMANCE ONLY.
*/
#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 
#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 
#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK 
#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL                      0x00002005
#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT                       0
#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK                        0x00000001U

/*
* Number of transactions that are serviced once the LPR queue goes critica
    * l is the smaller of: - (a) This number - (b) Number of transactions avai
    * lable. Unit: Transaction. FOR PERFORMANCE ONLY.
*/
#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 
#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 
#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 
#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL               0x0F00007F
#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT                24
#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK                 0xFF000000U

/*
* Number of clocks that the LPR queue can be starved before it goes critic
    * al. The minimum valid functional value for this register is 0x1. Program
    * ming it to 0x0 will disable the starvation functionality; during normal
    * operation, this function should not be disabled as it will cause excessi
    * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
*/
#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 
#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 
#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 
#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL                    0x0F00007F
#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT                     0
#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK                      0x0000FFFFU

/*
* Number of transactions that are serviced once the WR queue goes critical
    *  is the smaller of: - (a) This number - (b) Number of transactions avail
    * able. Unit: Transaction. FOR PERFORMANCE ONLY.
*/
#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 
#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 
#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 
#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL                  0x0F00007F
#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT                   24
#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK                    0xFF000000U

/*
* Number of clocks that the WR queue can be starved before it goes critica
    * l. The minimum valid functional value for this register is 0x1. Programm
    * ing it to 0x0 will disable the starvation functionality; during normal o
    * peration, this function should not be disabled as it will cause excessiv
    * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
*/
#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 
#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT 
#undef DDRC_PERFWR1_W_MAX_STARVE_MASK 
#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL                       0x0F00007F
#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT                        0
#define DDRC_PERFWR1_W_MAX_STARVE_MASK                         0x0000FFFFU

/*
* DQ nibble map for DQ bits [12-15] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL                 0x00000000
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT                  24
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK                   0xFF000000U

/*
* DQ nibble map for DQ bits [8-11] Present only in designs configured to s
    * upport DDR4.
*/
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL                  0x00000000
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT                   16
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK                    0x00FF0000U

/*
* DQ nibble map for DQ bits [4-7] Present only in designs configured to su
    * pport DDR4.
*/
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL                   0x00000000
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT                    8
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK                     0x0000FF00U

/*
* DQ nibble map for DQ bits [0-3] Present only in designs configured to su
    * pport DDR4.
*/
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 
#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL                   0x00000000
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT                    0
#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK                     0x000000FFU

/*
* DQ nibble map for DQ bits [28-31] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL                 0x00000000
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT                  24
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK                   0xFF000000U

/*
* DQ nibble map for DQ bits [24-27] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL                 0x00000000
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT                  16
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK                   0x00FF0000U

/*
* DQ nibble map for DQ bits [20-23] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL                 0x00000000
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT                  8
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK                   0x0000FF00U

/*
* DQ nibble map for DQ bits [16-19] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 
#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL                 0x00000000
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT                  0
#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK                   0x000000FFU

/*
* DQ nibble map for DQ bits [44-47] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL                 0x00000000
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT                  24
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK                   0xFF000000U

/*
* DQ nibble map for DQ bits [40-43] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL                 0x00000000
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT                  16
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK                   0x00FF0000U

/*
* DQ nibble map for DQ bits [36-39] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL                 0x00000000
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT                  8
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK                   0x0000FF00U

/*
* DQ nibble map for DQ bits [32-35] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 
#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL                 0x00000000
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT                  0
#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK                   0x000000FFU

/*
* DQ nibble map for DQ bits [60-63] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL                 0x00000000
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT                  24
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK                   0xFF000000U

/*
* DQ nibble map for DQ bits [56-59] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL                 0x00000000
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT                  16
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK                   0x00FF0000U

/*
* DQ nibble map for DQ bits [52-55] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL                 0x00000000
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT                  8
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK                   0x0000FF00U

/*
* DQ nibble map for DQ bits [48-51] Present only in designs configured to
    * support DDR4.
*/
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 
#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL                 0x00000000
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT                  0
#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK                   0x000000FFU

/*
* DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf
    * igured to support DDR4.
*/
#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 
#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 
#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 
#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL                0x00000000
#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT                 8
#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK                  0x0000FF00U

/*
* DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf
    * igured to support DDR4.
*/
#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 
#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 
#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 
#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL                0x00000000
#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT                 0
#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK                  0x000000FFU

/*
* All even ranks have the same DQ mapping controled by DQMAP0-4 register a
    * s rank 0. This register provides DQ swap function for all odd ranks to s
    * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b
    * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba
    * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs
    *  configured to support DDR4.
*/
#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL 
#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 
#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 
#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL                    
#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT                     0
#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK                      0x00000001U

/*
* When this is set to '0', auto-precharge is disabled for the flushed comm
    * and in a collision case. Collision cases are write followed by read to s
    * ame address, read followed by write to same address, or write followed b
    * y write to same address with DBG0.dis_wc bit = 1 (where same address com
    * parisons exclude the two address bits representing critical word). FOR D
    * EBUG ONLY.
*/
#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 
#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 
#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 
#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL                0x00000000
#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT                 4
#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK                  0x00000010U

/*
* When 1, disable write combine. FOR DEBUG ONLY
*/
#undef DDRC_DBG0_DIS_WC_DEFVAL 
#undef DDRC_DBG0_DIS_WC_SHIFT 
#undef DDRC_DBG0_DIS_WC_MASK 
#define DDRC_DBG0_DIS_WC_DEFVAL                                0x00000000
#define DDRC_DBG0_DIS_WC_SHIFT                                 0
#define DDRC_DBG0_DIS_WC_MASK                                  0x00000001U

/*
* Setting this register bit to 1 allows refresh and ZQCS commands to be tr
    * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD.
    * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore
    * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and
    *  ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor
    * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no
    *  function, and are ignored by the uMCTL2 logic. This register is static,
    *  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is
    * asserted (0).
*/
#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 
#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 
#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 
#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL                        0x00000000
#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT                         31
#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK                          0x80000000U

/*
* Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct
    * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit
    *  is automatically cleared. This operation must only be performed when DF
    * IUPD0.dis_auto_ctrlupd=1.
*/
#undef DDRC_DBGCMD_CTRLUPD_DEFVAL 
#undef DDRC_DBGCMD_CTRLUPD_SHIFT 
#undef DDRC_DBGCMD_CTRLUPD_MASK 
#define DDRC_DBGCMD_CTRLUPD_DEFVAL                             0x00000000
#define DDRC_DBGCMD_CTRLUPD_SHIFT                              5
#define DDRC_DBGCMD_CTRLUPD_MASK                               0x00000020U

/*
* Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (
    * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi
    * s request is stored in the uMCTL2, the bit is automatically cleared. Thi
    * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom
    * mended NOT to set this register bit if in Init operating mode. This regi
    * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown
    * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo
    * de.
*/
#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 
#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 
#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 
#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL                      0x00000000
#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT                       4
#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK                        0x00000010U

/*
* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
    * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be
    *  set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s
    * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
    * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
    * t or Deep power-down operating modes or Maximum Power Saving Mode.
*/
#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 
#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT 
#undef DDRC_DBGCMD_RANK1_REFRESH_MASK 
#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL                       0x00000000
#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT                        1
#define DDRC_DBGCMD_RANK1_REFRESH_MASK                         0x00000002U

/*
* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
    * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be
    *  set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s
    * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
    * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
    * t or Deep power-down operating modes or Maximum Power Saving Mode.
*/
#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 
#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT 
#undef DDRC_DBGCMD_RANK0_REFRESH_MASK 
#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL                       0x00000000
#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT                        0
#define DDRC_DBGCMD_RANK0_REFRESH_MASK                         0x00000001U

/*
* Enable quasi-dynamic register programming outside reset. Program registe
    * r to 0 to enable quasi-dynamic programming. Set back register to 1 once
    * programming is done.
*/
#undef DDRC_SWCTL_SW_DONE_DEFVAL 
#undef DDRC_SWCTL_SW_DONE_SHIFT 
#undef DDRC_SWCTL_SW_DONE_MASK 
#define DDRC_SWCTL_SW_DONE_DEFVAL                              
#define DDRC_SWCTL_SW_DONE_SHIFT                               0
#define DDRC_SWCTL_SW_DONE_MASK                                0x00000001U

/*
* Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand
    * s every AXI burst into multiple HIF commands, using the memory burst len
    * gth as a unit. If set to 1, then XPI will use half of the memory burst l
    * ength as a unit. This applies to both reads and writes. When MSTR.data_b
    * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i
    * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d
    * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd
    * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali
    * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT
    * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an
    * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST
    * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs
    * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR
    * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared
    * -AC is enabled
*/
#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL 
#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT 
#undef DDRC_PCCFG_BL_EXP_MODE_MASK 
#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL                          0x00000000
#define DDRC_PCCFG_BL_EXP_MODE_SHIFT                           8
#define DDRC_PCCFG_BL_EXP_MODE_MASK                            0x00000100U

/*
* Page match four limit. If set to 1, limits the number of consecutive sam
    * e page DDRC transactions that can be granted by the Port Arbiter to four
    *  when Page Match feature is enabled. If set to 0, there is no limit impo
    * sed on number of consecutive same page DDRC transactions.
*/
#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 
#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 
#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 
#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL                      0x00000000
#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT                       4
#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK                        0x00000010U

/*
* If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l
    * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw
    * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_
    * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a
    * t DDRC are driven to 1b'0.
*/
#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 
#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 
#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK 
#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL                       0x00000000
#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT                        0
#define DDRC_PCCFG_GO2CRITICAL_EN_MASK                         0x00000001U

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
    * bled and arurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
    * urgent signal can be asserted anytime and as long as required which is i
    * ndependent of address handshaking (it is not associated with any particu
    * lar command).
*/
#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 
#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the read channel of the port.
*/
#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 
#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL                   0x00000000
#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of read aging counters. These counters
    *  will be parallel loaded after reset, or after each grant to the corresp
    * onding port. The aging counters down-count every clock cycle where the p
    * ort is requesting but not granted. The higher significant 5-bits of the
    * read aging counter sets the priority of the read channel of a given port
    * . Port's priority will increase as the higher significant 5-bits of the
    * counter starts to decrease. When the aging counter becomes 0, the corres
    * ponding port channel will have the highest priority level (timeout condi
    * tion - Priority0). For multi-port configurations, the aging counters can
    * not be used to set port priorities when external dynamic priority inputs
    *  (arqos) are enabled (timeout is still applicable). For single port conf
    * igurations, the aging counters are only used when they timeout (become 0
    * ) to force read-write direction switching. In this case, external dynami
    * c priority input, arqos (for reads only) can still be used to set the DD
    * RC read priority (2 priority levels: low priority read - LPR, high prior
    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
    * s register field are tied internally to 2'b00.
*/
#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 
#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL                   0x00000000
#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK                     0x000003FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
    * bled and awurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
    * serted anytime and as long as required which is independent of address h
    * andshaking (it is not associated with any particular command).
*/
#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 
#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the write channel of the port.
*/
#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 
#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL                   0x00004000
#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of write aging counters. These counter
    * s will be parallel loaded after reset, or after each grant to the corres
    * ponding port. The aging counters down-count every clock cycle where the
    * port is requesting but not granted. The higher significant 5-bits of the
    *  write aging counter sets the initial priority of the write channel of a
    *  given port. Port's priority will increase as the higher significant 5-b
    * its of the counter starts to decrease. When the aging counter becomes 0,
    *  the corresponding port channel will have the highest priority level. Fo
    * r multi-port configurations, the aging counters cannot be used to set po
    * rt priorities when external dynamic priority inputs (awqos) are enabled
    * (timeout is still applicable). For single port configurations, the aging
    *  counters are only used when they timeout (become 0) to force read-write
    *  direction switching. Note: The two LSBs of this register field are tied
    *  internally to 2'b00.
*/
#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 
#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL                   0x00004000
#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK                     0x000003FFU

/*
* Enables port n.
*/
#undef DDRC_PCTRL_0_PORT_EN_DEFVAL 
#undef DDRC_PCTRL_0_PORT_EN_SHIFT 
#undef DDRC_PCTRL_0_PORT_EN_MASK 
#define DDRC_PCTRL_0_PORT_EN_DEFVAL                            
#define DDRC_PCTRL_0_PORT_EN_SHIFT                             0
#define DDRC_PCTRL_0_PORT_EN_MASK                              0x00000001U

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
    *  maps to the blue address queue. In this case, valid values are 0: LPR a
    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL                0x00000000
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT                 20
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK                  0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
    *  maps to the blue address queue. In this case, valid values are: 0: LPR
    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL                0x00000000
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT                 16
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK                  0x00030000U

/*
* Separation level1 indicating the end of region0 mapping; start of region
    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
    * lues are used directly as port priorities, where the higher the value co
    * rresponds to higher port priority. All of the map_level* registers must
    * be set to distinct values.
*/
#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 
#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 
#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 
#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT                  0
#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK                   0x0000000FU

/*
* Specifies the timeout value for transactions mapped to the red address q
    * ueue.
*/
#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 
#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 
#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT                16
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U

/*
* Specifies the timeout value for transactions mapped to the blue address
    * queue.
*/
#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 
#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 
#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT                0
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
    * bled and arurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
    * urgent signal can be asserted anytime and as long as required which is i
    * ndependent of address handshaking (it is not associated with any particu
    * lar command).
*/
#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 
#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the read channel of the port.
*/
#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 
#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL                   0x00000000
#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of read aging counters. These counters
    *  will be parallel loaded after reset, or after each grant to the corresp
    * onding port. The aging counters down-count every clock cycle where the p
    * ort is requesting but not granted. The higher significant 5-bits of the
    * read aging counter sets the priority of the read channel of a given port
    * . Port's priority will increase as the higher significant 5-bits of the
    * counter starts to decrease. When the aging counter becomes 0, the corres
    * ponding port channel will have the highest priority level (timeout condi
    * tion - Priority0). For multi-port configurations, the aging counters can
    * not be used to set port priorities when external dynamic priority inputs
    *  (arqos) are enabled (timeout is still applicable). For single port conf
    * igurations, the aging counters are only used when they timeout (become 0
    * ) to force read-write direction switching. In this case, external dynami
    * c priority input, arqos (for reads only) can still be used to set the DD
    * RC read priority (2 priority levels: low priority read - LPR, high prior
    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
    * s register field are tied internally to 2'b00.
*/
#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 
#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL                   0x00000000
#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK                     0x000003FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
    * bled and awurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
    * serted anytime and as long as required which is independent of address h
    * andshaking (it is not associated with any particular command).
*/
#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 
#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the write channel of the port.
*/
#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 
#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL                   0x00004000
#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of write aging counters. These counter
    * s will be parallel loaded after reset, or after each grant to the corres
    * ponding port. The aging counters down-count every clock cycle where the
    * port is requesting but not granted. The higher significant 5-bits of the
    *  write aging counter sets the initial priority of the write channel of a
    *  given port. Port's priority will increase as the higher significant 5-b
    * its of the counter starts to decrease. When the aging counter becomes 0,
    *  the corresponding port channel will have the highest priority level. Fo
    * r multi-port configurations, the aging counters cannot be used to set po
    * rt priorities when external dynamic priority inputs (awqos) are enabled
    * (timeout is still applicable). For single port configurations, the aging
    *  counters are only used when they timeout (become 0) to force read-write
    *  direction switching. Note: The two LSBs of this register field are tied
    *  internally to 2'b00.
*/
#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 
#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL                   0x00004000
#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK                     0x000003FFU

/*
* Enables port n.
*/
#undef DDRC_PCTRL_1_PORT_EN_DEFVAL 
#undef DDRC_PCTRL_1_PORT_EN_SHIFT 
#undef DDRC_PCTRL_1_PORT_EN_MASK 
#define DDRC_PCTRL_1_PORT_EN_DEFVAL                            
#define DDRC_PCTRL_1_PORT_EN_SHIFT                             0
#define DDRC_PCTRL_1_PORT_EN_MASK                              0x00000001U

/*
* This bitfield indicates the traffic class of region2. For dual address q
    * ueue configurations, region2 maps to the red address queue. Valid values
    *  are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
    *  = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
    * ased to LPR traffic.
*/
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL                0x02000E00
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT                 24
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK                  0x03000000U

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
    *  maps to the blue address queue. In this case, valid values are 0: LPR a
    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL                0x02000E00
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT                 20
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK                  0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
    *  maps to the blue address queue. In this case, valid values are: 0: LPR
    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL                0x02000E00
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT                 16
#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK                  0x00030000U

/*
* Separation level2 indicating the end of region1 mapping; start of region
    * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
    * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
    *  that for PA, arqos values are used directly as port priorities, where t
    * he higher the value corresponds to higher port priority. All of the map_
    * level* registers must be set to distinct values.
*/
#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 
#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL                 0x02000E00
#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT                  8
#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK                   0x00000F00U

/*
* Separation level1 indicating the end of region0 mapping; start of region
    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
    * lues are used directly as port priorities, where the higher the value co
    * rresponds to higher port priority. All of the map_level* registers must
    * be set to distinct values.
*/
#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 
#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 
#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL                 0x02000E00
#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT                  0
#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK                   0x0000000FU

/*
* Specifies the timeout value for transactions mapped to the red address q
    * ueue.
*/
#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 
#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 
#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 
#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT                16
#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U

/*
* Specifies the timeout value for transactions mapped to the blue address
    * queue.
*/
#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 
#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 
#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 
#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT                0
#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
    * bled and arurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
    * urgent signal can be asserted anytime and as long as required which is i
    * ndependent of address handshaking (it is not associated with any particu
    * lar command).
*/
#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 
#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the read channel of the port.
*/
#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 
#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL                   0x00000000
#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of read aging counters. These counters
    *  will be parallel loaded after reset, or after each grant to the corresp
    * onding port. The aging counters down-count every clock cycle where the p
    * ort is requesting but not granted. The higher significant 5-bits of the
    * read aging counter sets the priority of the read channel of a given port
    * . Port's priority will increase as the higher significant 5-bits of the
    * counter starts to decrease. When the aging counter becomes 0, the corres
    * ponding port channel will have the highest priority level (timeout condi
    * tion - Priority0). For multi-port configurations, the aging counters can
    * not be used to set port priorities when external dynamic priority inputs
    *  (arqos) are enabled (timeout is still applicable). For single port conf
    * igurations, the aging counters are only used when they timeout (become 0
    * ) to force read-write direction switching. In this case, external dynami
    * c priority input, arqos (for reads only) can still be used to set the DD
    * RC read priority (2 priority levels: low priority read - LPR, high prior
    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
    * s register field are tied internally to 2'b00.
*/
#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 
#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL                   0x00000000
#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK                     0x000003FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
    * bled and awurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
    * serted anytime and as long as required which is independent of address h
    * andshaking (it is not associated with any particular command).
*/
#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 
#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the write channel of the port.
*/
#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 
#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL                   0x00004000
#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of write aging counters. These counter
    * s will be parallel loaded after reset, or after each grant to the corres
    * ponding port. The aging counters down-count every clock cycle where the
    * port is requesting but not granted. The higher significant 5-bits of the
    *  write aging counter sets the initial priority of the write channel of a
    *  given port. Port's priority will increase as the higher significant 5-b
    * its of the counter starts to decrease. When the aging counter becomes 0,
    *  the corresponding port channel will have the highest priority level. Fo
    * r multi-port configurations, the aging counters cannot be used to set po
    * rt priorities when external dynamic priority inputs (awqos) are enabled
    * (timeout is still applicable). For single port configurations, the aging
    *  counters are only used when they timeout (become 0) to force read-write
    *  direction switching. Note: The two LSBs of this register field are tied
    *  internally to 2'b00.
*/
#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 
#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL                   0x00004000
#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK                     0x000003FFU

/*
* Enables port n.
*/
#undef DDRC_PCTRL_2_PORT_EN_DEFVAL 
#undef DDRC_PCTRL_2_PORT_EN_SHIFT 
#undef DDRC_PCTRL_2_PORT_EN_MASK 
#define DDRC_PCTRL_2_PORT_EN_DEFVAL                            
#define DDRC_PCTRL_2_PORT_EN_SHIFT                             0
#define DDRC_PCTRL_2_PORT_EN_MASK                              0x00000001U

/*
* This bitfield indicates the traffic class of region2. For dual address q
    * ueue configurations, region2 maps to the red address queue. Valid values
    *  are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
    *  = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
    * ased to LPR traffic.
*/
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL                0x02000E00
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT                 24
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK                  0x03000000U

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
    *  maps to the blue address queue. In this case, valid values are 0: LPR a
    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL                0x02000E00
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT                 20
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK                  0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
    *  maps to the blue address queue. In this case, valid values are: 0: LPR
    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL                0x02000E00
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT                 16
#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK                  0x00030000U

/*
* Separation level2 indicating the end of region1 mapping; start of region
    * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
    * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
    *  that for PA, arqos values are used directly as port priorities, where t
    * he higher the value corresponds to higher port priority. All of the map_
    * level* registers must be set to distinct values.
*/
#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 
#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL                 0x02000E00
#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT                  8
#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK                   0x00000F00U

/*
* Separation level1 indicating the end of region0 mapping; start of region
    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
    * lues are used directly as port priorities, where the higher the value co
    * rresponds to higher port priority. All of the map_level* registers must
    * be set to distinct values.
*/
#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 
#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 
#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL                 0x02000E00
#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT                  0
#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK                   0x0000000FU

/*
* Specifies the timeout value for transactions mapped to the red address q
    * ueue.
*/
#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 
#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 
#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 
#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT                16
#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U

/*
* Specifies the timeout value for transactions mapped to the blue address
    * queue.
*/
#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 
#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 
#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 
#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT                0
#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
    * bled and arurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
    * urgent signal can be asserted anytime and as long as required which is i
    * ndependent of address handshaking (it is not associated with any particu
    * lar command).
*/
#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 
#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the read channel of the port.
*/
#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 
#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL                   0x00000000
#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of read aging counters. These counters
    *  will be parallel loaded after reset, or after each grant to the corresp
    * onding port. The aging counters down-count every clock cycle where the p
    * ort is requesting but not granted. The higher significant 5-bits of the
    * read aging counter sets the priority of the read channel of a given port
    * . Port's priority will increase as the higher significant 5-bits of the
    * counter starts to decrease. When the aging counter becomes 0, the corres
    * ponding port channel will have the highest priority level (timeout condi
    * tion - Priority0). For multi-port configurations, the aging counters can
    * not be used to set port priorities when external dynamic priority inputs
    *  (arqos) are enabled (timeout is still applicable). For single port conf
    * igurations, the aging counters are only used when they timeout (become 0
    * ) to force read-write direction switching. In this case, external dynami
    * c priority input, arqos (for reads only) can still be used to set the DD
    * RC read priority (2 priority levels: low priority read - LPR, high prior
    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
    * s register field are tied internally to 2'b00.
*/
#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 
#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL                   0x00000000
#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK                     0x000003FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
    * bled and awurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
    * serted anytime and as long as required which is independent of address h
    * andshaking (it is not associated with any particular command).
*/
#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 
#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the write channel of the port.
*/
#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 
#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL                   0x00004000
#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of write aging counters. These counter
    * s will be parallel loaded after reset, or after each grant to the corres
    * ponding port. The aging counters down-count every clock cycle where the
    * port is requesting but not granted. The higher significant 5-bits of the
    *  write aging counter sets the initial priority of the write channel of a
    *  given port. Port's priority will increase as the higher significant 5-b
    * its of the counter starts to decrease. When the aging counter becomes 0,
    *  the corresponding port channel will have the highest priority level. Fo
    * r multi-port configurations, the aging counters cannot be used to set po
    * rt priorities when external dynamic priority inputs (awqos) are enabled
    * (timeout is still applicable). For single port configurations, the aging
    *  counters are only used when they timeout (become 0) to force read-write
    *  direction switching. Note: The two LSBs of this register field are tied
    *  internally to 2'b00.
*/
#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 
#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL                   0x00004000
#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK                     0x000003FFU

/*
* Enables port n.
*/
#undef DDRC_PCTRL_3_PORT_EN_DEFVAL 
#undef DDRC_PCTRL_3_PORT_EN_SHIFT 
#undef DDRC_PCTRL_3_PORT_EN_MASK 
#define DDRC_PCTRL_3_PORT_EN_DEFVAL                            
#define DDRC_PCTRL_3_PORT_EN_SHIFT                             0
#define DDRC_PCTRL_3_PORT_EN_MASK                              0x00000001U

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
    *  maps to the blue address queue. In this case, valid values are 0: LPR a
    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 
#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL                0x00000000
#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT                 20
#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK                  0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
    *  maps to the blue address queue. In this case, valid values are: 0: LPR
    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 
#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL                0x00000000
#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT                 16
#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK                  0x00030000U

/*
* Separation level1 indicating the end of region0 mapping; start of region
    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
    * lues are used directly as port priorities, where the higher the value co
    * rresponds to higher port priority. All of the map_level* registers must
    * be set to distinct values.
*/
#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 
#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 
#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 
#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT                  0
#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK                   0x0000000FU

/*
* Specifies the timeout value for transactions mapped to the red address q
    * ueue.
*/
#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 
#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 
#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 
#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT                16
#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U

/*
* Specifies the timeout value for transactions mapped to the blue address
    * queue.
*/
#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 
#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 
#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 
#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT                0
#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
    * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
    *  traffic.
*/
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 
#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL               0x00000000
#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT                20
#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK                 0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
    * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
    * traffic.
*/
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 
#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL               0x00000000
#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT                16
#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK                 0x00030000U

/*
* Separation level indicating the end of region0 mapping; start of region0
    *  is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
    * . Note that for PA, awqos values are used directly as port priorities, w
    * here the higher the value corresponds to higher port priority.
*/
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 
#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 
#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT                  0
#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK                   0x0000000FU

/*
* Specifies the timeout value for write transactions.
*/
#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL 
#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 
#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 
#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL               
#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT                0
#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
    * bled and arurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
    * urgent signal can be asserted anytime and as long as required which is i
    * ndependent of address handshaking (it is not associated with any particu
    * lar command).
*/
#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 
#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the read channel of the port.
*/
#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 
#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL                   0x00000000
#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of read aging counters. These counters
    *  will be parallel loaded after reset, or after each grant to the corresp
    * onding port. The aging counters down-count every clock cycle where the p
    * ort is requesting but not granted. The higher significant 5-bits of the
    * read aging counter sets the priority of the read channel of a given port
    * . Port's priority will increase as the higher significant 5-bits of the
    * counter starts to decrease. When the aging counter becomes 0, the corres
    * ponding port channel will have the highest priority level (timeout condi
    * tion - Priority0). For multi-port configurations, the aging counters can
    * not be used to set port priorities when external dynamic priority inputs
    *  (arqos) are enabled (timeout is still applicable). For single port conf
    * igurations, the aging counters are only used when they timeout (become 0
    * ) to force read-write direction switching. In this case, external dynami
    * c priority input, arqos (for reads only) can still be used to set the DD
    * RC read priority (2 priority levels: low priority read - LPR, high prior
    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
    * s register field are tied internally to 2'b00.
*/
#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 
#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL                   0x00000000
#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK                     0x000003FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
    * bled and awurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
    * serted anytime and as long as required which is independent of address h
    * andshaking (it is not associated with any particular command).
*/
#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 
#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the write channel of the port.
*/
#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 
#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL                   0x00004000
#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of write aging counters. These counter
    * s will be parallel loaded after reset, or after each grant to the corres
    * ponding port. The aging counters down-count every clock cycle where the
    * port is requesting but not granted. The higher significant 5-bits of the
    *  write aging counter sets the initial priority of the write channel of a
    *  given port. Port's priority will increase as the higher significant 5-b
    * its of the counter starts to decrease. When the aging counter becomes 0,
    *  the corresponding port channel will have the highest priority level. Fo
    * r multi-port configurations, the aging counters cannot be used to set po
    * rt priorities when external dynamic priority inputs (awqos) are enabled
    * (timeout is still applicable). For single port configurations, the aging
    *  counters are only used when they timeout (become 0) to force read-write
    *  direction switching. Note: The two LSBs of this register field are tied
    *  internally to 2'b00.
*/
#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 
#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL                   0x00004000
#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK                     0x000003FFU

/*
* Enables port n.
*/
#undef DDRC_PCTRL_4_PORT_EN_DEFVAL 
#undef DDRC_PCTRL_4_PORT_EN_SHIFT 
#undef DDRC_PCTRL_4_PORT_EN_MASK 
#define DDRC_PCTRL_4_PORT_EN_DEFVAL                            
#define DDRC_PCTRL_4_PORT_EN_SHIFT                             0
#define DDRC_PCTRL_4_PORT_EN_MASK                              0x00000001U

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
    *  maps to the blue address queue. In this case, valid values are 0: LPR a
    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 
#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL                0x00000000
#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT                 20
#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK                  0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
    *  maps to the blue address queue. In this case, valid values are: 0: LPR
    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 
#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL                0x00000000
#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT                 16
#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK                  0x00030000U

/*
* Separation level1 indicating the end of region0 mapping; start of region
    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
    * lues are used directly as port priorities, where the higher the value co
    * rresponds to higher port priority. All of the map_level* registers must
    * be set to distinct values.
*/
#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 
#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 
#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 
#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT                  0
#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK                   0x0000000FU

/*
* Specifies the timeout value for transactions mapped to the red address q
    * ueue.
*/
#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 
#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 
#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 
#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT                16
#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U

/*
* Specifies the timeout value for transactions mapped to the blue address
    * queue.
*/
#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 
#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 
#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 
#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT                0
#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
    * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
    *  traffic.
*/
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 
#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL               0x00000000
#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT                20
#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK                 0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
    * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
    * traffic.
*/
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 
#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL               0x00000000
#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT                16
#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK                 0x00030000U

/*
* Separation level indicating the end of region0 mapping; start of region0
    *  is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
    * . Note that for PA, awqos values are used directly as port priorities, w
    * here the higher the value corresponds to higher port priority.
*/
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 
#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 
#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT                  0
#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK                   0x0000000FU

/*
* Specifies the timeout value for write transactions.
*/
#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL 
#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 
#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 
#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL               
#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT                0
#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
    * bled and arurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
    * urgent signal can be asserted anytime and as long as required which is i
    * ndependent of address handshaking (it is not associated with any particu
    * lar command).
*/
#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 
#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the read channel of the port.
*/
#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 
#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL                   0x00000000
#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of read aging counters. These counters
    *  will be parallel loaded after reset, or after each grant to the corresp
    * onding port. The aging counters down-count every clock cycle where the p
    * ort is requesting but not granted. The higher significant 5-bits of the
    * read aging counter sets the priority of the read channel of a given port
    * . Port's priority will increase as the higher significant 5-bits of the
    * counter starts to decrease. When the aging counter becomes 0, the corres
    * ponding port channel will have the highest priority level (timeout condi
    * tion - Priority0). For multi-port configurations, the aging counters can
    * not be used to set port priorities when external dynamic priority inputs
    *  (arqos) are enabled (timeout is still applicable). For single port conf
    * igurations, the aging counters are only used when they timeout (become 0
    * ) to force read-write direction switching. In this case, external dynami
    * c priority input, arqos (for reads only) can still be used to set the DD
    * RC read priority (2 priority levels: low priority read - LPR, high prior
    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
    * s register field are tied internally to 2'b00.
*/
#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 
#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL                   0x00000000
#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK                     0x000003FFU

/*
* If set to 1, enables the Page Match feature. If enabled, once a requesti
    * ng port is granted, the port is continued to be granted if the following
    *  immediate commands are to the same memory page (same bank and same row)
    * . See also related PCCFG.pagematch_limit register.
*/
#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 
#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 
#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 
#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT                14
#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U

/*
* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
    * bled and awurgent is asserted by the master, that port becomes the highe
    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
    * serted anytime and as long as required which is independent of address h
    * andshaking (it is not associated with any particular command).
*/
#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 
#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 
#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 
#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT                   13
#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK                    0x00002000U

/*
* If set to 1, enables aging function for the write channel of the port.
*/
#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 
#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 
#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 
#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL                   0x00004000
#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT                    12
#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK                     0x00001000U

/*
* Determines the initial load value of write aging counters. These counter
    * s will be parallel loaded after reset, or after each grant to the corres
    * ponding port. The aging counters down-count every clock cycle where the
    * port is requesting but not granted. The higher significant 5-bits of the
    *  write aging counter sets the initial priority of the write channel of a
    *  given port. Port's priority will increase as the higher significant 5-b
    * its of the counter starts to decrease. When the aging counter becomes 0,
    *  the corresponding port channel will have the highest priority level. Fo
    * r multi-port configurations, the aging counters cannot be used to set po
    * rt priorities when external dynamic priority inputs (awqos) are enabled
    * (timeout is still applicable). For single port configurations, the aging
    *  counters are only used when they timeout (become 0) to force read-write
    *  direction switching. Note: The two LSBs of this register field are tied
    *  internally to 2'b00.
*/
#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 
#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 
#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 
#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL                   0x00004000
#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT                    0
#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK                     0x000003FFU

/*
* Enables port n.
*/
#undef DDRC_PCTRL_5_PORT_EN_DEFVAL 
#undef DDRC_PCTRL_5_PORT_EN_SHIFT 
#undef DDRC_PCTRL_5_PORT_EN_MASK 
#define DDRC_PCTRL_5_PORT_EN_DEFVAL                            
#define DDRC_PCTRL_5_PORT_EN_SHIFT                             0
#define DDRC_PCTRL_5_PORT_EN_MASK                              0x00000001U

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
    *  maps to the blue address queue. In this case, valid values are 0: LPR a
    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 
#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL                0x00000000
#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT                 20
#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK                  0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
    *  maps to the blue address queue. In this case, valid values are: 0: LPR
    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
    * traffic.
*/
#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 
#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL                0x00000000
#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT                 16
#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK                  0x00030000U

/*
* Separation level1 indicating the end of region0 mapping; start of region
    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
    * lues are used directly as port priorities, where the higher the value co
    * rresponds to higher port priority. All of the map_level* registers must
    * be set to distinct values.
*/
#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 
#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 
#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 
#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT                  0
#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK                   0x0000000FU

/*
* Specifies the timeout value for transactions mapped to the red address q
    * ueue.
*/
#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 
#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 
#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 
#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT                16
#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U

/*
* Specifies the timeout value for transactions mapped to the blue address
    * queue.
*/
#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 
#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 
#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 
#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT                0
#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU

/*
* This bitfield indicates the traffic class of region 1. Valid values are:
    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
    * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
    *  traffic.
*/
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 
#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL               0x00000000
#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT                20
#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK                 0x00300000U

/*
* This bitfield indicates the traffic class of region 0. Valid values are:
    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
    * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
    * traffic.
*/
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 
#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL               0x00000000
#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT                16
#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK                 0x00030000U

/*
* Separation level indicating the end of region0 mapping; start of region0
    *  is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
    * . Note that for PA, awqos values are used directly as port priorities, w
    * here the higher the value corresponds to higher port priority.
*/
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 
#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 
#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT                  0
#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK                   0x0000000FU

/*
* Specifies the timeout value for write transactions.
*/
#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL 
#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 
#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 
#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL               
#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT                0
#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU

/*
* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
    * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
    * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
*/
#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL 
#undef DDRC_SARBASE0_BASE_ADDR_SHIFT 
#undef DDRC_SARBASE0_BASE_ADDR_MASK 
#define DDRC_SARBASE0_BASE_ADDR_DEFVAL                         
#define DDRC_SARBASE0_BASE_ADDR_SHIFT                          0
#define DDRC_SARBASE0_BASE_ADDR_MASK                           0x000001FFU

/*
* Number of blocks for address region n. This register determines the tota
    * l size of the region in multiples of minimum block size as specified by
    * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
    * as number of blocks = nblocks + 1. For example, if register is programme
    * d to 0, region will have 1 block.
*/
#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL 
#undef DDRC_SARSIZE0_NBLOCKS_SHIFT 
#undef DDRC_SARSIZE0_NBLOCKS_MASK 
#define DDRC_SARSIZE0_NBLOCKS_DEFVAL                           
#define DDRC_SARSIZE0_NBLOCKS_SHIFT                            0
#define DDRC_SARSIZE0_NBLOCKS_MASK                             0x000000FFU

/*
* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
    * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
    * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
*/
#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL 
#undef DDRC_SARBASE1_BASE_ADDR_SHIFT 
#undef DDRC_SARBASE1_BASE_ADDR_MASK 
#define DDRC_SARBASE1_BASE_ADDR_DEFVAL                         
#define DDRC_SARBASE1_BASE_ADDR_SHIFT                          0
#define DDRC_SARBASE1_BASE_ADDR_MASK                           0x000001FFU

/*
* Number of blocks for address region n. This register determines the tota
    * l size of the region in multiples of minimum block size as specified by
    * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
    * as number of blocks = nblocks + 1. For example, if register is programme
    * d to 0, region will have 1 block.
*/
#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL 
#undef DDRC_SARSIZE1_NBLOCKS_SHIFT 
#undef DDRC_SARSIZE1_NBLOCKS_MASK 
#define DDRC_SARSIZE1_NBLOCKS_DEFVAL                           
#define DDRC_SARSIZE1_NBLOCKS_SHIFT                            0
#define DDRC_SARSIZE1_NBLOCKS_MASK                             0x000000FFU

/*
* Specifies the number of DFI clock cycles after an assertion or de-assert
    * ion of the DFI control signals that the control signals at the PHY-DRAM
    * interface reflect the assertion or de-assertion. If the DFI clock and th
    * e memory clock are not phase-aligned, this timing parameter should be ro
    * unded up to the next integer value. Note that if using RDIMM, it is nece
    * ssary to increment this parameter by RDIMM's extra cycle of latency in t
    * erms of DFI clock.
*/
#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 
#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 
#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 
#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL            0x07020002
#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT             24
#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK              0x1F000000U

/*
* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
    * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
    * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
    *  - 1 in terms of SDR clock cycles Refer to PHY specification for correct
    *  value.
*/
#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 
#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 
#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 
#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL          0x07020002
#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT           23
#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK            0x00800000U

/*
* Time from the assertion of a read command on the DFI interface to the as
    * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
    * ect value. This corresponds to the DFI parameter trddata_en. Note that,
    * depending on the PHY, if using RDIMM, it may be necessary to use the val
    * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
    * the extra cycle of latency through the RDIMM. Unit: Clocks
*/
#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 
#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 
#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 
#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL             0x07020002
#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT              16
#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK               0x003F0000U

/*
* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
    * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
    *  in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
    * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
    *  clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
    * n for correct value.
*/
#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 
#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 
#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 
#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL          0x07020002
#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT           15
#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK            0x00008000U

/*
* Specifies the number of clock cycles between when dfi_wrdata_en is asser
    * ted to when the associated write data is driven on the dfi_wrdata signal
    * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
    *  specification for correct value. Note, max supported value is 8. Unit:
    * Clocks
*/
#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 
#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 
#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL             0x07020002
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT              8
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK               0x00003F00U

/*
* Write latency Number of clocks from the write command to write data enab
    * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
    * lat. Refer to PHY specification for correct value.Note that, depending o
    * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
    *  in the calculation of tphy_wrlat. This is to compensate for the extra c
    * ycle of latency through the RDIMM.
*/
#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 
#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 
#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL              0x07020002
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT               0
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK                0x0000003FU

/*
* DDR block level reset inside of the DDR Sub System
*/
#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                    0x0000000F
#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                     3
#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                      0x00000008U

/*
* APM block level reset inside of the DDR Sub System
*/
#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 
#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 
#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK 
#define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL                    0x0000000F
#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT                     2
#define CRF_APB_RST_DDR_SS_APM_RESET_MASK                      0x00000004U

/*
* Address Copy
*/
#undef DDR_PHY_PGCR0_ADCP_DEFVAL 
#undef DDR_PHY_PGCR0_ADCP_SHIFT 
#undef DDR_PHY_PGCR0_ADCP_MASK 
#define DDR_PHY_PGCR0_ADCP_DEFVAL                              0x07001E00
#define DDR_PHY_PGCR0_ADCP_SHIFT                               31
#define DDR_PHY_PGCR0_ADCP_MASK                                0x80000000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 
#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 
#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK 
#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL                    0x07001E00
#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT                     27
#define DDR_PHY_PGCR0_RESERVED_30_27_MASK                      0x78000000U

/*
* PHY FIFO Reset
*/
#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL 
#undef DDR_PHY_PGCR0_PHYFRST_SHIFT 
#undef DDR_PHY_PGCR0_PHYFRST_MASK 
#define DDR_PHY_PGCR0_PHYFRST_DEFVAL                           0x07001E00
#define DDR_PHY_PGCR0_PHYFRST_SHIFT                            26
#define DDR_PHY_PGCR0_PHYFRST_MASK                             0x04000000U

/*
* Oscillator Mode Address/Command Delay Line Select
*/
#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL 
#undef DDR_PHY_PGCR0_OSCACDL_SHIFT 
#undef DDR_PHY_PGCR0_OSCACDL_MASK 
#define DDR_PHY_PGCR0_OSCACDL_DEFVAL                           0x07001E00
#define DDR_PHY_PGCR0_OSCACDL_SHIFT                            24
#define DDR_PHY_PGCR0_OSCACDL_MASK                             0x03000000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 
#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 
#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK 
#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL                    0x07001E00
#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT                     19
#define DDR_PHY_PGCR0_RESERVED_23_19_MASK                      0x00F80000U

/*
* Digital Test Output Select
*/
#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL 
#undef DDR_PHY_PGCR0_DTOSEL_SHIFT 
#undef DDR_PHY_PGCR0_DTOSEL_MASK 
#define DDR_PHY_PGCR0_DTOSEL_DEFVAL                            0x07001E00
#define DDR_PHY_PGCR0_DTOSEL_SHIFT                             14
#define DDR_PHY_PGCR0_DTOSEL_MASK                              0x0007C000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL 
#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT 
#undef DDR_PHY_PGCR0_RESERVED_13_MASK 
#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL                       0x07001E00
#define DDR_PHY_PGCR0_RESERVED_13_SHIFT                        13
#define DDR_PHY_PGCR0_RESERVED_13_MASK                         0x00002000U

/*
* Oscillator Mode Division
*/
#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL 
#undef DDR_PHY_PGCR0_OSCDIV_SHIFT 
#undef DDR_PHY_PGCR0_OSCDIV_MASK 
#define DDR_PHY_PGCR0_OSCDIV_DEFVAL                            0x07001E00
#define DDR_PHY_PGCR0_OSCDIV_SHIFT                             9
#define DDR_PHY_PGCR0_OSCDIV_MASK                              0x00001E00U

/*
* Oscillator Enable
*/
#undef DDR_PHY_PGCR0_OSCEN_DEFVAL 
#undef DDR_PHY_PGCR0_OSCEN_SHIFT 
#undef DDR_PHY_PGCR0_OSCEN_MASK 
#define DDR_PHY_PGCR0_OSCEN_DEFVAL                             0x07001E00
#define DDR_PHY_PGCR0_OSCEN_SHIFT                              8
#define DDR_PHY_PGCR0_OSCEN_MASK                               0x00000100U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 
#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 
#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK 
#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL                      0x07001E00
#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT                       0
#define DDR_PHY_PGCR0_RESERVED_7_0_MASK                        0x000000FFU

/*
* Clear Training Status Registers
*/
#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 
#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT 
#undef DDR_PHY_PGCR2_CLRTSTAT_MASK 
#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL                          0x00F12480
#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT                           31
#define DDR_PHY_PGCR2_CLRTSTAT_MASK                            0x80000000U

/*
* Clear Impedance Calibration
*/
#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL 
#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT 
#undef DDR_PHY_PGCR2_CLRZCAL_MASK 
#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL                           0x00F12480
#define DDR_PHY_PGCR2_CLRZCAL_SHIFT                            30
#define DDR_PHY_PGCR2_CLRZCAL_MASK                             0x40000000U

/*
* Clear Parity Error
*/
#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL 
#undef DDR_PHY_PGCR2_CLRPERR_SHIFT 
#undef DDR_PHY_PGCR2_CLRPERR_MASK 
#define DDR_PHY_PGCR2_CLRPERR_DEFVAL                           0x00F12480
#define DDR_PHY_PGCR2_CLRPERR_SHIFT                            29
#define DDR_PHY_PGCR2_CLRPERR_MASK                             0x20000000U

/*
* Initialization Complete Pin Configuration
*/
#undef DDR_PHY_PGCR2_ICPC_DEFVAL 
#undef DDR_PHY_PGCR2_ICPC_SHIFT 
#undef DDR_PHY_PGCR2_ICPC_MASK 
#define DDR_PHY_PGCR2_ICPC_DEFVAL                              0x00F12480
#define DDR_PHY_PGCR2_ICPC_SHIFT                               28
#define DDR_PHY_PGCR2_ICPC_MASK                                0x10000000U

/*
* Data Training PUB Mode Exit Timer
*/
#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 
#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT 
#undef DDR_PHY_PGCR2_DTPMXTMR_MASK 
#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL                          0x00F12480
#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT                           20
#define DDR_PHY_PGCR2_DTPMXTMR_MASK                            0x0FF00000U

/*
* Initialization Bypass
*/
#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 
#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT 
#undef DDR_PHY_PGCR2_INITFSMBYP_MASK 
#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL                        0x00F12480
#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT                         19
#define DDR_PHY_PGCR2_INITFSMBYP_MASK                          0x00080000U

/*
* PLL FSM Bypass
*/
#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 
#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 
#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK 
#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL                         0x00F12480
#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT                          18
#define DDR_PHY_PGCR2_PLLFSMBYP_MASK                           0x00040000U

/*
* Refresh Period
*/
#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL 
#undef DDR_PHY_PGCR2_TREFPRD_SHIFT 
#undef DDR_PHY_PGCR2_TREFPRD_MASK 
#define DDR_PHY_PGCR2_TREFPRD_DEFVAL                           0x00F12480
#define DDR_PHY_PGCR2_TREFPRD_SHIFT                            0
#define DDR_PHY_PGCR2_TREFPRD_MASK                             0x0003FFFFU

/*
* CKN Enable
*/
#undef DDR_PHY_PGCR3_CKNEN_DEFVAL 
#undef DDR_PHY_PGCR3_CKNEN_SHIFT 
#undef DDR_PHY_PGCR3_CKNEN_MASK 
#define DDR_PHY_PGCR3_CKNEN_DEFVAL                             0x55AA0080
#define DDR_PHY_PGCR3_CKNEN_SHIFT                              24
#define DDR_PHY_PGCR3_CKNEN_MASK                               0xFF000000U

/*
* CK Enable
*/
#undef DDR_PHY_PGCR3_CKEN_DEFVAL 
#undef DDR_PHY_PGCR3_CKEN_SHIFT 
#undef DDR_PHY_PGCR3_CKEN_MASK 
#define DDR_PHY_PGCR3_CKEN_DEFVAL                              0x55AA0080
#define DDR_PHY_PGCR3_CKEN_SHIFT                               16
#define DDR_PHY_PGCR3_CKEN_MASK                                0x00FF0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL 
#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT 
#undef DDR_PHY_PGCR3_RESERVED_15_MASK 
#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL                       0x55AA0080
#define DDR_PHY_PGCR3_RESERVED_15_SHIFT                        15
#define DDR_PHY_PGCR3_RESERVED_15_MASK                         0x00008000U

/*
* Enable Clock Gating for AC [0] ctl_rd_clk
*/
#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 
#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 
#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK 
#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL                       0x55AA0080
#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT                        13
#define DDR_PHY_PGCR3_GATEACRDCLK_MASK                         0x00006000U

/*
* Enable Clock Gating for AC [0] ddr_clk
*/
#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 
#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 
#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK 
#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL                      0x55AA0080
#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT                       11
#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK                        0x00001800U

/*
* Enable Clock Gating for AC [0] ctl_clk
*/
#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 
#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 
#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK 
#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL                      0x55AA0080
#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT                       9
#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK                        0x00000600U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL 
#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT 
#undef DDR_PHY_PGCR3_RESERVED_8_MASK 
#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL                        0x55AA0080
#define DDR_PHY_PGCR3_RESERVED_8_SHIFT                         8
#define DDR_PHY_PGCR3_RESERVED_8_MASK                          0x00000100U

/*
* Controls DDL Bypass Modes
*/
#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 
#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 
#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK 
#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL                        0x55AA0080
#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT                         6
#define DDR_PHY_PGCR3_DDLBYPMODE_MASK                          0x000000C0U

/*
* IO Loop-Back Select
*/
#undef DDR_PHY_PGCR3_IOLB_DEFVAL 
#undef DDR_PHY_PGCR3_IOLB_SHIFT 
#undef DDR_PHY_PGCR3_IOLB_MASK 
#define DDR_PHY_PGCR3_IOLB_DEFVAL                              0x55AA0080
#define DDR_PHY_PGCR3_IOLB_SHIFT                               5
#define DDR_PHY_PGCR3_IOLB_MASK                                0x00000020U

/*
* AC Receive FIFO Read Mode
*/
#undef DDR_PHY_PGCR3_RDMODE_DEFVAL 
#undef DDR_PHY_PGCR3_RDMODE_SHIFT 
#undef DDR_PHY_PGCR3_RDMODE_MASK 
#define DDR_PHY_PGCR3_RDMODE_DEFVAL                            0x55AA0080
#define DDR_PHY_PGCR3_RDMODE_SHIFT                             3
#define DDR_PHY_PGCR3_RDMODE_MASK                              0x00000018U

/*
* Read FIFO Reset Disable
*/
#undef DDR_PHY_PGCR3_DISRST_DEFVAL 
#undef DDR_PHY_PGCR3_DISRST_SHIFT 
#undef DDR_PHY_PGCR3_DISRST_MASK 
#define DDR_PHY_PGCR3_DISRST_DEFVAL                            0x55AA0080
#define DDR_PHY_PGCR3_DISRST_SHIFT                             2
#define DDR_PHY_PGCR3_DISRST_MASK                              0x00000004U

/*
* Clock Level when Clock Gating
*/
#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 
#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT 
#undef DDR_PHY_PGCR3_CLKLEVEL_MASK 
#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL                          0x55AA0080
#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT                           0
#define DDR_PHY_PGCR3_CLKLEVEL_MASK                            0x00000003U

/*
* Frequency B Ratio Term
*/
#undef DDR_PHY_PGCR5_FRQBT_DEFVAL 
#undef DDR_PHY_PGCR5_FRQBT_SHIFT 
#undef DDR_PHY_PGCR5_FRQBT_MASK 
#define DDR_PHY_PGCR5_FRQBT_DEFVAL                             0x01010000
#define DDR_PHY_PGCR5_FRQBT_SHIFT                              24
#define DDR_PHY_PGCR5_FRQBT_MASK                               0xFF000000U

/*
* Frequency A Ratio Term
*/
#undef DDR_PHY_PGCR5_FRQAT_DEFVAL 
#undef DDR_PHY_PGCR5_FRQAT_SHIFT 
#undef DDR_PHY_PGCR5_FRQAT_MASK 
#define DDR_PHY_PGCR5_FRQAT_DEFVAL                             0x01010000
#define DDR_PHY_PGCR5_FRQAT_SHIFT                              16
#define DDR_PHY_PGCR5_FRQAT_MASK                               0x00FF0000U

/*
* DFI Disconnect Time Period
*/
#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 
#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 
#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK 
#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL                       0x01010000
#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT                        8
#define DDR_PHY_PGCR5_DISCNPERIOD_MASK                         0x0000FF00U

/*
* Receiver bias core side control
*/
#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 
#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 
#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK 
#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL                       0x01010000
#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT                        4
#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK                         0x000000F0U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL 
#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT 
#undef DDR_PHY_PGCR5_RESERVED_3_MASK 
#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL                        0x01010000
#define DDR_PHY_PGCR5_RESERVED_3_SHIFT                         3
#define DDR_PHY_PGCR5_RESERVED_3_MASK                          0x00000008U

/*
* Internal VREF generator REFSEL ragne select
*/
#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 
#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 
#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK 
#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL                    0x01010000
#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT                     2
#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK                      0x00000004U

/*
* DDL Page Read Write select
*/
#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL 
#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT 
#undef DDR_PHY_PGCR5_DDLPGACT_MASK 
#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL                          0x01010000
#define DDR_PHY_PGCR5_DDLPGACT_SHIFT                           1
#define DDR_PHY_PGCR5_DDLPGACT_MASK                            0x00000002U

/*
* DDL Page Read Write select
*/
#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL 
#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT 
#undef DDR_PHY_PGCR5_DDLPGRW_MASK 
#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL                           0x01010000
#define DDR_PHY_PGCR5_DDLPGRW_SHIFT                            0
#define DDR_PHY_PGCR5_DDLPGRW_MASK                             0x00000001U

/*
* PLL Power-Down Time
*/
#undef DDR_PHY_PTR0_TPLLPD_DEFVAL 
#undef DDR_PHY_PTR0_TPLLPD_SHIFT 
#undef DDR_PHY_PTR0_TPLLPD_MASK 
#define DDR_PHY_PTR0_TPLLPD_DEFVAL                             0x42C21590
#define DDR_PHY_PTR0_TPLLPD_SHIFT                              21
#define DDR_PHY_PTR0_TPLLPD_MASK                               0xFFE00000U

/*
* PLL Gear Shift Time
*/
#undef DDR_PHY_PTR0_TPLLGS_DEFVAL 
#undef DDR_PHY_PTR0_TPLLGS_SHIFT 
#undef DDR_PHY_PTR0_TPLLGS_MASK 
#define DDR_PHY_PTR0_TPLLGS_DEFVAL                             0x42C21590
#define DDR_PHY_PTR0_TPLLGS_SHIFT                              6
#define DDR_PHY_PTR0_TPLLGS_MASK                               0x001FFFC0U

/*
* PHY Reset Time
*/
#undef DDR_PHY_PTR0_TPHYRST_DEFVAL 
#undef DDR_PHY_PTR0_TPHYRST_SHIFT 
#undef DDR_PHY_PTR0_TPHYRST_MASK 
#define DDR_PHY_PTR0_TPHYRST_DEFVAL                            0x42C21590
#define DDR_PHY_PTR0_TPHYRST_SHIFT                             0
#define DDR_PHY_PTR0_TPHYRST_MASK                              0x0000003FU

/*
* PLL Lock Time
*/
#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL 
#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT 
#undef DDR_PHY_PTR1_TPLLLOCK_MASK 
#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL                           0xD05612C0
#define DDR_PHY_PTR1_TPLLLOCK_SHIFT                            16
#define DDR_PHY_PTR1_TPLLLOCK_MASK                             0xFFFF0000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 
#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT 
#undef DDR_PHY_PTR1_RESERVED_15_13_MASK 
#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL                     0xD05612C0
#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT                      13
#define DDR_PHY_PTR1_RESERVED_15_13_MASK                       0x0000E000U

/*
* PLL Reset Time
*/
#undef DDR_PHY_PTR1_TPLLRST_DEFVAL 
#undef DDR_PHY_PTR1_TPLLRST_SHIFT 
#undef DDR_PHY_PTR1_TPLLRST_MASK 
#define DDR_PHY_PTR1_TPLLRST_DEFVAL                            0xD05612C0
#define DDR_PHY_PTR1_TPLLRST_SHIFT                             0
#define DDR_PHY_PTR1_TPLLRST_MASK                              0x00001FFFU

/*
* PLL Bypass
*/
#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL 
#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT 
#undef DDR_PHY_PLLCR0_PLLBYP_MASK 
#define DDR_PHY_PLLCR0_PLLBYP_DEFVAL                           0x001C0000
#define DDR_PHY_PLLCR0_PLLBYP_SHIFT                            31
#define DDR_PHY_PLLCR0_PLLBYP_MASK                             0x80000000U

/*
* PLL Reset
*/
#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL 
#undef DDR_PHY_PLLCR0_PLLRST_SHIFT 
#undef DDR_PHY_PLLCR0_PLLRST_MASK 
#define DDR_PHY_PLLCR0_PLLRST_DEFVAL                           0x001C0000
#define DDR_PHY_PLLCR0_PLLRST_SHIFT                            30
#define DDR_PHY_PLLCR0_PLLRST_MASK                             0x40000000U

/*
* PLL Power Down
*/
#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL 
#undef DDR_PHY_PLLCR0_PLLPD_SHIFT 
#undef DDR_PHY_PLLCR0_PLLPD_MASK 
#define DDR_PHY_PLLCR0_PLLPD_DEFVAL                            0x001C0000
#define DDR_PHY_PLLCR0_PLLPD_SHIFT                             29
#define DDR_PHY_PLLCR0_PLLPD_MASK                              0x20000000U

/*
* Reference Stop Mode
*/
#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL 
#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT 
#undef DDR_PHY_PLLCR0_RSTOPM_MASK 
#define DDR_PHY_PLLCR0_RSTOPM_DEFVAL                           0x001C0000
#define DDR_PHY_PLLCR0_RSTOPM_SHIFT                            28
#define DDR_PHY_PLLCR0_RSTOPM_MASK                             0x10000000U

/*
* PLL Frequency Select
*/
#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL 
#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT 
#undef DDR_PHY_PLLCR0_FRQSEL_MASK 
#define DDR_PHY_PLLCR0_FRQSEL_DEFVAL                           0x001C0000
#define DDR_PHY_PLLCR0_FRQSEL_SHIFT                            24
#define DDR_PHY_PLLCR0_FRQSEL_MASK                             0x0F000000U

/*
* Relock Mode
*/
#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL 
#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT 
#undef DDR_PHY_PLLCR0_RLOCKM_MASK 
#define DDR_PHY_PLLCR0_RLOCKM_DEFVAL                           0x001C0000
#define DDR_PHY_PLLCR0_RLOCKM_SHIFT                            23
#define DDR_PHY_PLLCR0_RLOCKM_MASK                             0x00800000U

/*
* Charge Pump Proportional Current Control
*/
#undef DDR_PHY_PLLCR0_CPPC_DEFVAL 
#undef DDR_PHY_PLLCR0_CPPC_SHIFT 
#undef DDR_PHY_PLLCR0_CPPC_MASK 
#define DDR_PHY_PLLCR0_CPPC_DEFVAL                             0x001C0000
#define DDR_PHY_PLLCR0_CPPC_SHIFT                              17
#define DDR_PHY_PLLCR0_CPPC_MASK                               0x007E0000U

/*
* Charge Pump Integrating Current Control
*/
#undef DDR_PHY_PLLCR0_CPIC_DEFVAL 
#undef DDR_PHY_PLLCR0_CPIC_SHIFT 
#undef DDR_PHY_PLLCR0_CPIC_MASK 
#define DDR_PHY_PLLCR0_CPIC_DEFVAL                             0x001C0000
#define DDR_PHY_PLLCR0_CPIC_SHIFT                              13
#define DDR_PHY_PLLCR0_CPIC_MASK                               0x0001E000U

/*
* Gear Shift
*/
#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL 
#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT 
#undef DDR_PHY_PLLCR0_GSHIFT_MASK 
#define DDR_PHY_PLLCR0_GSHIFT_DEFVAL                           0x001C0000
#define DDR_PHY_PLLCR0_GSHIFT_SHIFT                            12
#define DDR_PHY_PLLCR0_GSHIFT_MASK                             0x00001000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 
#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 
#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK 
#define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL                    0x001C0000
#define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT                     9
#define DDR_PHY_PLLCR0_RESERVED_11_9_MASK                      0x00000E00U

/*
* Analog Test Enable
*/
#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL 
#undef DDR_PHY_PLLCR0_ATOEN_SHIFT 
#undef DDR_PHY_PLLCR0_ATOEN_MASK 
#define DDR_PHY_PLLCR0_ATOEN_DEFVAL                            0x001C0000
#define DDR_PHY_PLLCR0_ATOEN_SHIFT                             8
#define DDR_PHY_PLLCR0_ATOEN_MASK                              0x00000100U

/*
* Analog Test Control
*/
#undef DDR_PHY_PLLCR0_ATC_DEFVAL 
#undef DDR_PHY_PLLCR0_ATC_SHIFT 
#undef DDR_PHY_PLLCR0_ATC_MASK 
#define DDR_PHY_PLLCR0_ATC_DEFVAL                              0x001C0000
#define DDR_PHY_PLLCR0_ATC_SHIFT                               4
#define DDR_PHY_PLLCR0_ATC_MASK                                0x000000F0U

/*
* Digital Test Control
*/
#undef DDR_PHY_PLLCR0_DTC_DEFVAL 
#undef DDR_PHY_PLLCR0_DTC_SHIFT 
#undef DDR_PHY_PLLCR0_DTC_MASK 
#define DDR_PHY_PLLCR0_DTC_DEFVAL                              0x001C0000
#define DDR_PHY_PLLCR0_DTC_SHIFT                               0
#define DDR_PHY_PLLCR0_DTC_MASK                                0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 
#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 
#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK 
#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL                    0x02A04101
#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT                     28
#define DDR_PHY_DSGCR_RESERVED_31_28_MASK                      0xF0000000U

/*
* When RDBI enabled, this bit is used to select RDBI CL calculation, if it
    *  is 1b1, calculation will use RDBICL, otherwise use default calculation.
*/
#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 
#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT 
#undef DDR_PHY_DSGCR_RDBICLSEL_MASK 
#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL                         0x02A04101
#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT                          27
#define DDR_PHY_DSGCR_RDBICLSEL_MASK                           0x08000000U

/*
* When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v
    * alue.
*/
#undef DDR_PHY_DSGCR_RDBICL_DEFVAL 
#undef DDR_PHY_DSGCR_RDBICL_SHIFT 
#undef DDR_PHY_DSGCR_RDBICL_MASK 
#define DDR_PHY_DSGCR_RDBICL_DEFVAL                            0x02A04101
#define DDR_PHY_DSGCR_RDBICL_SHIFT                             24
#define DDR_PHY_DSGCR_RDBICL_MASK                              0x07000000U

/*
* PHY Impedance Update Enable
*/
#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL 
#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT 
#undef DDR_PHY_DSGCR_PHYZUEN_MASK 
#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL                           0x02A04101
#define DDR_PHY_DSGCR_PHYZUEN_SHIFT                            23
#define DDR_PHY_DSGCR_PHYZUEN_MASK                             0x00800000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL 
#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT 
#undef DDR_PHY_DSGCR_RESERVED_22_MASK 
#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL                       0x02A04101
#define DDR_PHY_DSGCR_RESERVED_22_SHIFT                        22
#define DDR_PHY_DSGCR_RESERVED_22_MASK                         0x00400000U

/*
* SDRAM Reset Output Enable
*/
#undef DDR_PHY_DSGCR_RSTOE_DEFVAL 
#undef DDR_PHY_DSGCR_RSTOE_SHIFT 
#undef DDR_PHY_DSGCR_RSTOE_MASK 
#define DDR_PHY_DSGCR_RSTOE_DEFVAL                             0x02A04101
#define DDR_PHY_DSGCR_RSTOE_SHIFT                              21
#define DDR_PHY_DSGCR_RSTOE_MASK                               0x00200000U

/*
* Single Data Rate Mode
*/
#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL 
#undef DDR_PHY_DSGCR_SDRMODE_SHIFT 
#undef DDR_PHY_DSGCR_SDRMODE_MASK 
#define DDR_PHY_DSGCR_SDRMODE_DEFVAL                           0x02A04101
#define DDR_PHY_DSGCR_SDRMODE_SHIFT                            19
#define DDR_PHY_DSGCR_SDRMODE_MASK                             0x00180000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL 
#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT 
#undef DDR_PHY_DSGCR_RESERVED_18_MASK 
#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL                       0x02A04101
#define DDR_PHY_DSGCR_RESERVED_18_SHIFT                        18
#define DDR_PHY_DSGCR_RESERVED_18_MASK                         0x00040000U

/*
* ATO Analog Test Enable
*/
#undef DDR_PHY_DSGCR_ATOAE_DEFVAL 
#undef DDR_PHY_DSGCR_ATOAE_SHIFT 
#undef DDR_PHY_DSGCR_ATOAE_MASK 
#define DDR_PHY_DSGCR_ATOAE_DEFVAL                             0x02A04101
#define DDR_PHY_DSGCR_ATOAE_SHIFT                              17
#define DDR_PHY_DSGCR_ATOAE_MASK                               0x00020000U

/*
* DTO Output Enable
*/
#undef DDR_PHY_DSGCR_DTOOE_DEFVAL 
#undef DDR_PHY_DSGCR_DTOOE_SHIFT 
#undef DDR_PHY_DSGCR_DTOOE_MASK 
#define DDR_PHY_DSGCR_DTOOE_DEFVAL                             0x02A04101
#define DDR_PHY_DSGCR_DTOOE_SHIFT                              16
#define DDR_PHY_DSGCR_DTOOE_MASK                               0x00010000U

/*
* DTO I/O Mode
*/
#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL 
#undef DDR_PHY_DSGCR_DTOIOM_SHIFT 
#undef DDR_PHY_DSGCR_DTOIOM_MASK 
#define DDR_PHY_DSGCR_DTOIOM_DEFVAL                            0x02A04101
#define DDR_PHY_DSGCR_DTOIOM_SHIFT                             15
#define DDR_PHY_DSGCR_DTOIOM_MASK                              0x00008000U

/*
* DTO Power Down Receiver
*/
#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL 
#undef DDR_PHY_DSGCR_DTOPDR_SHIFT 
#undef DDR_PHY_DSGCR_DTOPDR_MASK 
#define DDR_PHY_DSGCR_DTOPDR_DEFVAL                            0x02A04101
#define DDR_PHY_DSGCR_DTOPDR_SHIFT                             14
#define DDR_PHY_DSGCR_DTOPDR_MASK                              0x00004000U

/*
* Reserved. Return zeroes on reads
*/
#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL 
#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT 
#undef DDR_PHY_DSGCR_RESERVED_13_MASK 
#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL                       0x02A04101
#define DDR_PHY_DSGCR_RESERVED_13_SHIFT                        13
#define DDR_PHY_DSGCR_RESERVED_13_MASK                         0x00002000U

/*
* DTO On-Die Termination
*/
#undef DDR_PHY_DSGCR_DTOODT_DEFVAL 
#undef DDR_PHY_DSGCR_DTOODT_SHIFT 
#undef DDR_PHY_DSGCR_DTOODT_MASK 
#define DDR_PHY_DSGCR_DTOODT_DEFVAL                            0x02A04101
#define DDR_PHY_DSGCR_DTOODT_SHIFT                             12
#define DDR_PHY_DSGCR_DTOODT_MASK                              0x00001000U

/*
* PHY Update Acknowledge Delay
*/
#undef DDR_PHY_DSGCR_PUAD_DEFVAL 
#undef DDR_PHY_DSGCR_PUAD_SHIFT 
#undef DDR_PHY_DSGCR_PUAD_MASK 
#define DDR_PHY_DSGCR_PUAD_DEFVAL                              0x02A04101
#define DDR_PHY_DSGCR_PUAD_SHIFT                               6
#define DDR_PHY_DSGCR_PUAD_MASK                                0x00000FC0U

/*
* Controller Update Acknowledge Enable
*/
#undef DDR_PHY_DSGCR_CUAEN_DEFVAL 
#undef DDR_PHY_DSGCR_CUAEN_SHIFT 
#undef DDR_PHY_DSGCR_CUAEN_MASK 
#define DDR_PHY_DSGCR_CUAEN_DEFVAL                             0x02A04101
#define DDR_PHY_DSGCR_CUAEN_SHIFT                              5
#define DDR_PHY_DSGCR_CUAEN_MASK                               0x00000020U

/*
* Reserved. Return zeroes on reads
*/
#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 
#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 
#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK 
#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL                      0x02A04101
#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT                       3
#define DDR_PHY_DSGCR_RESERVED_4_3_MASK                        0x00000018U

/*
* Controller Impedance Update Enable
*/
#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL 
#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT 
#undef DDR_PHY_DSGCR_CTLZUEN_MASK 
#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL                           0x02A04101
#define DDR_PHY_DSGCR_CTLZUEN_SHIFT                            2
#define DDR_PHY_DSGCR_CTLZUEN_MASK                             0x00000004U

/*
* Reserved. Return zeroes on reads
*/
#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL 
#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT 
#undef DDR_PHY_DSGCR_RESERVED_1_MASK 
#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL                        0x02A04101
#define DDR_PHY_DSGCR_RESERVED_1_SHIFT                         1
#define DDR_PHY_DSGCR_RESERVED_1_MASK                          0x00000002U

/*
* PHY Update Request Enable
*/
#undef DDR_PHY_DSGCR_PUREN_DEFVAL 
#undef DDR_PHY_DSGCR_PUREN_SHIFT 
#undef DDR_PHY_DSGCR_PUREN_MASK 
#define DDR_PHY_DSGCR_PUREN_DEFVAL                             0x02A04101
#define DDR_PHY_DSGCR_PUREN_SHIFT                              0
#define DDR_PHY_DSGCR_PUREN_MASK                               0x00000001U

/*
* General Purpose Register 0
*/
#undef DDR_PHY_GPR0_GPR0_DEFVAL 
#undef DDR_PHY_GPR0_GPR0_SHIFT 
#undef DDR_PHY_GPR0_GPR0_MASK 
#define DDR_PHY_GPR0_GPR0_DEFVAL                               
#define DDR_PHY_GPR0_GPR0_SHIFT                                0
#define DDR_PHY_GPR0_GPR0_MASK                                 0xFFFFFFFFU

/*
* DDR4 Gear Down Timing.
*/
#undef DDR_PHY_DCR_GEARDN_DEFVAL 
#undef DDR_PHY_DCR_GEARDN_SHIFT 
#undef DDR_PHY_DCR_GEARDN_MASK 
#define DDR_PHY_DCR_GEARDN_DEFVAL                              0x0000040D
#define DDR_PHY_DCR_GEARDN_SHIFT                               31
#define DDR_PHY_DCR_GEARDN_MASK                                0x80000000U

/*
* Un-used Bank Group
*/
#undef DDR_PHY_DCR_UBG_DEFVAL 
#undef DDR_PHY_DCR_UBG_SHIFT 
#undef DDR_PHY_DCR_UBG_MASK 
#define DDR_PHY_DCR_UBG_DEFVAL                                 0x0000040D
#define DDR_PHY_DCR_UBG_SHIFT                                  30
#define DDR_PHY_DCR_UBG_MASK                                   0x40000000U

/*
* Un-buffered DIMM Address Mirroring
*/
#undef DDR_PHY_DCR_UDIMM_DEFVAL 
#undef DDR_PHY_DCR_UDIMM_SHIFT 
#undef DDR_PHY_DCR_UDIMM_MASK 
#define DDR_PHY_DCR_UDIMM_DEFVAL                               0x0000040D
#define DDR_PHY_DCR_UDIMM_SHIFT                                29
#define DDR_PHY_DCR_UDIMM_MASK                                 0x20000000U

/*
* DDR 2T Timing
*/
#undef DDR_PHY_DCR_DDR2T_DEFVAL 
#undef DDR_PHY_DCR_DDR2T_SHIFT 
#undef DDR_PHY_DCR_DDR2T_MASK 
#define DDR_PHY_DCR_DDR2T_DEFVAL                               0x0000040D
#define DDR_PHY_DCR_DDR2T_SHIFT                                28
#define DDR_PHY_DCR_DDR2T_MASK                                 0x10000000U

/*
* No Simultaneous Rank Access
*/
#undef DDR_PHY_DCR_NOSRA_DEFVAL 
#undef DDR_PHY_DCR_NOSRA_SHIFT 
#undef DDR_PHY_DCR_NOSRA_MASK 
#define DDR_PHY_DCR_NOSRA_DEFVAL                               0x0000040D
#define DDR_PHY_DCR_NOSRA_SHIFT                                27
#define DDR_PHY_DCR_NOSRA_MASK                                 0x08000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL 
#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT 
#undef DDR_PHY_DCR_RESERVED_26_18_MASK 
#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL                      0x0000040D
#define DDR_PHY_DCR_RESERVED_26_18_SHIFT                       18
#define DDR_PHY_DCR_RESERVED_26_18_MASK                        0x07FC0000U

/*
* Byte Mask
*/
#undef DDR_PHY_DCR_BYTEMASK_DEFVAL 
#undef DDR_PHY_DCR_BYTEMASK_SHIFT 
#undef DDR_PHY_DCR_BYTEMASK_MASK 
#define DDR_PHY_DCR_BYTEMASK_DEFVAL                            0x0000040D
#define DDR_PHY_DCR_BYTEMASK_SHIFT                             10
#define DDR_PHY_DCR_BYTEMASK_MASK                              0x0003FC00U

/*
* DDR Type
*/
#undef DDR_PHY_DCR_DDRTYPE_DEFVAL 
#undef DDR_PHY_DCR_DDRTYPE_SHIFT 
#undef DDR_PHY_DCR_DDRTYPE_MASK 
#define DDR_PHY_DCR_DDRTYPE_DEFVAL                             0x0000040D
#define DDR_PHY_DCR_DDRTYPE_SHIFT                              8
#define DDR_PHY_DCR_DDRTYPE_MASK                               0x00000300U

/*
* Multi-Purpose Register (MPR) DQ (DDR3 Only)
*/
#undef DDR_PHY_DCR_MPRDQ_DEFVAL 
#undef DDR_PHY_DCR_MPRDQ_SHIFT 
#undef DDR_PHY_DCR_MPRDQ_MASK 
#define DDR_PHY_DCR_MPRDQ_DEFVAL                               0x0000040D
#define DDR_PHY_DCR_MPRDQ_SHIFT                                7
#define DDR_PHY_DCR_MPRDQ_MASK                                 0x00000080U

/*
* Primary DQ (DDR3 Only)
*/
#undef DDR_PHY_DCR_PDQ_DEFVAL 
#undef DDR_PHY_DCR_PDQ_SHIFT 
#undef DDR_PHY_DCR_PDQ_MASK 
#define DDR_PHY_DCR_PDQ_DEFVAL                                 0x0000040D
#define DDR_PHY_DCR_PDQ_SHIFT                                  4
#define DDR_PHY_DCR_PDQ_MASK                                   0x00000070U

/*
* DDR 8-Bank
*/
#undef DDR_PHY_DCR_DDR8BNK_DEFVAL 
#undef DDR_PHY_DCR_DDR8BNK_SHIFT 
#undef DDR_PHY_DCR_DDR8BNK_MASK 
#define DDR_PHY_DCR_DDR8BNK_DEFVAL                             0x0000040D
#define DDR_PHY_DCR_DDR8BNK_SHIFT                              3
#define DDR_PHY_DCR_DDR8BNK_MASK                               0x00000008U

/*
* DDR Mode
*/
#undef DDR_PHY_DCR_DDRMD_DEFVAL 
#undef DDR_PHY_DCR_DDRMD_SHIFT 
#undef DDR_PHY_DCR_DDRMD_MASK 
#define DDR_PHY_DCR_DDRMD_DEFVAL                               0x0000040D
#define DDR_PHY_DCR_DDRMD_SHIFT                                0
#define DDR_PHY_DCR_DDRMD_MASK                                 0x00000007U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK 
#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL                    0x105A2D08
#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT                     29
#define DDR_PHY_DTPR0_RESERVED_31_29_MASK                      0xE0000000U

/*
* Activate to activate command delay (different banks)
*/
#undef DDR_PHY_DTPR0_TRRD_DEFVAL 
#undef DDR_PHY_DTPR0_TRRD_SHIFT 
#undef DDR_PHY_DTPR0_TRRD_MASK 
#define DDR_PHY_DTPR0_TRRD_DEFVAL                              0x105A2D08
#define DDR_PHY_DTPR0_TRRD_SHIFT                               24
#define DDR_PHY_DTPR0_TRRD_MASK                                0x1F000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL 
#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT 
#undef DDR_PHY_DTPR0_RESERVED_23_MASK 
#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL                       0x105A2D08
#define DDR_PHY_DTPR0_RESERVED_23_SHIFT                        23
#define DDR_PHY_DTPR0_RESERVED_23_MASK                         0x00800000U

/*
* Activate to precharge command delay
*/
#undef DDR_PHY_DTPR0_TRAS_DEFVAL 
#undef DDR_PHY_DTPR0_TRAS_SHIFT 
#undef DDR_PHY_DTPR0_TRAS_MASK 
#define DDR_PHY_DTPR0_TRAS_DEFVAL                              0x105A2D08
#define DDR_PHY_DTPR0_TRAS_SHIFT                               16
#define DDR_PHY_DTPR0_TRAS_MASK                                0x007F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL 
#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT 
#undef DDR_PHY_DTPR0_RESERVED_15_MASK 
#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL                       0x105A2D08
#define DDR_PHY_DTPR0_RESERVED_15_SHIFT                        15
#define DDR_PHY_DTPR0_RESERVED_15_MASK                         0x00008000U

/*
* Precharge command period
*/
#undef DDR_PHY_DTPR0_TRP_DEFVAL 
#undef DDR_PHY_DTPR0_TRP_SHIFT 
#undef DDR_PHY_DTPR0_TRP_MASK 
#define DDR_PHY_DTPR0_TRP_DEFVAL                               0x105A2D08
#define DDR_PHY_DTPR0_TRP_SHIFT                                8
#define DDR_PHY_DTPR0_TRP_MASK                                 0x00007F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 
#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 
#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK 
#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL                      0x105A2D08
#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT                       5
#define DDR_PHY_DTPR0_RESERVED_7_5_MASK                        0x000000E0U

/*
* Internal read to precharge command delay
*/
#undef DDR_PHY_DTPR0_TRTP_DEFVAL 
#undef DDR_PHY_DTPR0_TRTP_SHIFT 
#undef DDR_PHY_DTPR0_TRTP_MASK 
#define DDR_PHY_DTPR0_TRTP_DEFVAL                              0x105A2D08
#define DDR_PHY_DTPR0_TRTP_SHIFT                               0
#define DDR_PHY_DTPR0_TRTP_MASK                                0x0000001FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL 
#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT 
#undef DDR_PHY_DTPR1_RESERVED_31_MASK 
#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL                       0x5656041E
#define DDR_PHY_DTPR1_RESERVED_31_SHIFT                        31
#define DDR_PHY_DTPR1_RESERVED_31_MASK                         0x80000000U

/*
* Minimum delay from when write leveling mode is programmed to the first D
    * QS/DQS# rising edge.
*/
#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL 
#undef DDR_PHY_DTPR1_TWLMRD_SHIFT 
#undef DDR_PHY_DTPR1_TWLMRD_MASK 
#define DDR_PHY_DTPR1_TWLMRD_DEFVAL                            0x5656041E
#define DDR_PHY_DTPR1_TWLMRD_SHIFT                             24
#define DDR_PHY_DTPR1_TWLMRD_MASK                              0x7F000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL 
#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT 
#undef DDR_PHY_DTPR1_RESERVED_23_MASK 
#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL                       0x5656041E
#define DDR_PHY_DTPR1_RESERVED_23_SHIFT                        23
#define DDR_PHY_DTPR1_RESERVED_23_MASK                         0x00800000U

/*
* 4-bank activate period
*/
#undef DDR_PHY_DTPR1_TFAW_DEFVAL 
#undef DDR_PHY_DTPR1_TFAW_SHIFT 
#undef DDR_PHY_DTPR1_TFAW_MASK 
#define DDR_PHY_DTPR1_TFAW_DEFVAL                              0x5656041E
#define DDR_PHY_DTPR1_TFAW_SHIFT                               16
#define DDR_PHY_DTPR1_TFAW_MASK                                0x007F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 
#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 
#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK 
#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL                    0x5656041E
#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT                     11
#define DDR_PHY_DTPR1_RESERVED_15_11_MASK                      0x0000F800U

/*
* Load mode update delay (DDR4 and DDR3 only)
*/
#undef DDR_PHY_DTPR1_TMOD_DEFVAL 
#undef DDR_PHY_DTPR1_TMOD_SHIFT 
#undef DDR_PHY_DTPR1_TMOD_MASK 
#define DDR_PHY_DTPR1_TMOD_DEFVAL                              0x5656041E
#define DDR_PHY_DTPR1_TMOD_SHIFT                               8
#define DDR_PHY_DTPR1_TMOD_MASK                                0x00000700U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 
#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 
#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK 
#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL                      0x5656041E
#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT                       5
#define DDR_PHY_DTPR1_RESERVED_7_5_MASK                        0x000000E0U

/*
* Load mode cycle time
*/
#undef DDR_PHY_DTPR1_TMRD_DEFVAL 
#undef DDR_PHY_DTPR1_TMRD_SHIFT 
#undef DDR_PHY_DTPR1_TMRD_MASK 
#define DDR_PHY_DTPR1_TMRD_DEFVAL                              0x5656041E
#define DDR_PHY_DTPR1_TMRD_SHIFT                               0
#define DDR_PHY_DTPR1_TMRD_MASK                                0x0000001FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK 
#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL                    0x000B01D0
#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT                     29
#define DDR_PHY_DTPR2_RESERVED_31_29_MASK                      0xE0000000U

/*
* Read to Write command delay. Valid values are
*/
#undef DDR_PHY_DTPR2_TRTW_DEFVAL 
#undef DDR_PHY_DTPR2_TRTW_SHIFT 
#undef DDR_PHY_DTPR2_TRTW_MASK 
#define DDR_PHY_DTPR2_TRTW_DEFVAL                              0x000B01D0
#define DDR_PHY_DTPR2_TRTW_SHIFT                               28
#define DDR_PHY_DTPR2_TRTW_MASK                                0x10000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 
#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 
#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK 
#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL                    0x000B01D0
#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT                     25
#define DDR_PHY_DTPR2_RESERVED_27_25_MASK                      0x0E000000U

/*
* Read to ODT delay (DDR3 only)
*/
#undef DDR_PHY_DTPR2_TRTODT_DEFVAL 
#undef DDR_PHY_DTPR2_TRTODT_SHIFT 
#undef DDR_PHY_DTPR2_TRTODT_MASK 
#define DDR_PHY_DTPR2_TRTODT_DEFVAL                            0x000B01D0
#define DDR_PHY_DTPR2_TRTODT_SHIFT                             24
#define DDR_PHY_DTPR2_TRTODT_MASK                              0x01000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 
#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 
#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK 
#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL                    0x000B01D0
#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT                     20
#define DDR_PHY_DTPR2_RESERVED_23_20_MASK                      0x00F00000U

/*
* CKE minimum pulse width
*/
#undef DDR_PHY_DTPR2_TCKE_DEFVAL 
#undef DDR_PHY_DTPR2_TCKE_SHIFT 
#undef DDR_PHY_DTPR2_TCKE_MASK 
#define DDR_PHY_DTPR2_TCKE_DEFVAL                              0x000B01D0
#define DDR_PHY_DTPR2_TCKE_SHIFT                               16
#define DDR_PHY_DTPR2_TCKE_MASK                                0x000F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 
#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 
#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK 
#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL                    0x000B01D0
#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT                     10
#define DDR_PHY_DTPR2_RESERVED_15_10_MASK                      0x0000FC00U

/*
* Self refresh exit delay
*/
#undef DDR_PHY_DTPR2_TXS_DEFVAL 
#undef DDR_PHY_DTPR2_TXS_SHIFT 
#undef DDR_PHY_DTPR2_TXS_MASK 
#define DDR_PHY_DTPR2_TXS_DEFVAL                               0x000B01D0
#define DDR_PHY_DTPR2_TXS_SHIFT                                0
#define DDR_PHY_DTPR2_TXS_MASK                                 0x000003FFU

/*
* ODT turn-off delay extension
*/
#undef DDR_PHY_DTPR3_TOFDX_DEFVAL 
#undef DDR_PHY_DTPR3_TOFDX_SHIFT 
#undef DDR_PHY_DTPR3_TOFDX_MASK 
#define DDR_PHY_DTPR3_TOFDX_DEFVAL                             0x02000804
#define DDR_PHY_DTPR3_TOFDX_SHIFT                              29
#define DDR_PHY_DTPR3_TOFDX_MASK                               0xE0000000U

/*
* Read to read and write to write command delay
*/
#undef DDR_PHY_DTPR3_TCCD_DEFVAL 
#undef DDR_PHY_DTPR3_TCCD_SHIFT 
#undef DDR_PHY_DTPR3_TCCD_MASK 
#define DDR_PHY_DTPR3_TCCD_DEFVAL                              0x02000804
#define DDR_PHY_DTPR3_TCCD_SHIFT                               26
#define DDR_PHY_DTPR3_TCCD_MASK                                0x1C000000U

/*
* DLL locking time
*/
#undef DDR_PHY_DTPR3_TDLLK_DEFVAL 
#undef DDR_PHY_DTPR3_TDLLK_SHIFT 
#undef DDR_PHY_DTPR3_TDLLK_MASK 
#define DDR_PHY_DTPR3_TDLLK_DEFVAL                             0x02000804
#define DDR_PHY_DTPR3_TDLLK_SHIFT                              16
#define DDR_PHY_DTPR3_TDLLK_MASK                               0x03FF0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 
#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 
#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK 
#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL                    0x02000804
#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT                     12
#define DDR_PHY_DTPR3_RESERVED_15_12_MASK                      0x0000F000U

/*
* Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
*/
#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 
#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 
#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK 
#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL                         0x02000804
#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT                          8
#define DDR_PHY_DTPR3_TDQSCKMAX_MASK                           0x00000F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 
#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 
#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK 
#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL                      0x02000804
#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT                       3
#define DDR_PHY_DTPR3_RESERVED_7_3_MASK                        0x000000F8U

/*
* DQS output access time from CK/CK# (LPDDR2/3 only)
*/
#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL 
#undef DDR_PHY_DTPR3_TDQSCK_SHIFT 
#undef DDR_PHY_DTPR3_TDQSCK_MASK 
#define DDR_PHY_DTPR3_TDQSCK_DEFVAL                            0x02000804
#define DDR_PHY_DTPR3_TDQSCK_SHIFT                             0
#define DDR_PHY_DTPR3_TDQSCK_MASK                              0x00000007U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK 
#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL                    0x01C02B10
#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT                     30
#define DDR_PHY_DTPR4_RESERVED_31_30_MASK                      0xC0000000U

/*
* ODT turn-on/turn-off delays (DDR2 only)
*/
#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 
#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 
#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK 
#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL                       0x01C02B10
#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT                        28
#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK                         0x30000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 
#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 
#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK 
#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL                    0x01C02B10
#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT                     26
#define DDR_PHY_DTPR4_RESERVED_27_26_MASK                      0x0C000000U

/*
* Refresh-to-Refresh
*/
#undef DDR_PHY_DTPR4_TRFC_DEFVAL 
#undef DDR_PHY_DTPR4_TRFC_SHIFT 
#undef DDR_PHY_DTPR4_TRFC_MASK 
#define DDR_PHY_DTPR4_TRFC_DEFVAL                              0x01C02B10
#define DDR_PHY_DTPR4_TRFC_SHIFT                               16
#define DDR_PHY_DTPR4_TRFC_MASK                                0x03FF0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK 
#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL                    0x01C02B10
#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT                     14
#define DDR_PHY_DTPR4_RESERVED_15_14_MASK                      0x0000C000U

/*
* Write leveling output delay
*/
#undef DDR_PHY_DTPR4_TWLO_DEFVAL 
#undef DDR_PHY_DTPR4_TWLO_SHIFT 
#undef DDR_PHY_DTPR4_TWLO_MASK 
#define DDR_PHY_DTPR4_TWLO_DEFVAL                              0x01C02B10
#define DDR_PHY_DTPR4_TWLO_SHIFT                               8
#define DDR_PHY_DTPR4_TWLO_MASK                                0x00003F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 
#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 
#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK 
#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL                      0x01C02B10
#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT                       5
#define DDR_PHY_DTPR4_RESERVED_7_5_MASK                        0x000000E0U

/*
* Power down exit delay
*/
#undef DDR_PHY_DTPR4_TXP_DEFVAL 
#undef DDR_PHY_DTPR4_TXP_SHIFT 
#undef DDR_PHY_DTPR4_TXP_MASK 
#define DDR_PHY_DTPR4_TXP_DEFVAL                               0x01C02B10
#define DDR_PHY_DTPR4_TXP_SHIFT                                0
#define DDR_PHY_DTPR4_TXP_MASK                                 0x0000001FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 
#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 
#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK 
#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL                    0x00872716
#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT                     24
#define DDR_PHY_DTPR5_RESERVED_31_24_MASK                      0xFF000000U

/*
* Activate to activate command delay (same bank)
*/
#undef DDR_PHY_DTPR5_TRC_DEFVAL 
#undef DDR_PHY_DTPR5_TRC_SHIFT 
#undef DDR_PHY_DTPR5_TRC_MASK 
#define DDR_PHY_DTPR5_TRC_DEFVAL                               0x00872716
#define DDR_PHY_DTPR5_TRC_SHIFT                                16
#define DDR_PHY_DTPR5_TRC_MASK                                 0x00FF0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DTPR5_RESERVED_15_MASK 
#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL                       0x00872716
#define DDR_PHY_DTPR5_RESERVED_15_SHIFT                        15
#define DDR_PHY_DTPR5_RESERVED_15_MASK                         0x00008000U

/*
* Activate to read or write delay
*/
#undef DDR_PHY_DTPR5_TRCD_DEFVAL 
#undef DDR_PHY_DTPR5_TRCD_SHIFT 
#undef DDR_PHY_DTPR5_TRCD_MASK 
#define DDR_PHY_DTPR5_TRCD_DEFVAL                              0x00872716
#define DDR_PHY_DTPR5_TRCD_SHIFT                               8
#define DDR_PHY_DTPR5_TRCD_MASK                                0x00007F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 
#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 
#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK 
#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL                      0x00872716
#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT                       5
#define DDR_PHY_DTPR5_RESERVED_7_5_MASK                        0x000000E0U

/*
* Internal write to read command delay
*/
#undef DDR_PHY_DTPR5_TWTR_DEFVAL 
#undef DDR_PHY_DTPR5_TWTR_SHIFT 
#undef DDR_PHY_DTPR5_TWTR_MASK 
#define DDR_PHY_DTPR5_TWTR_DEFVAL                              0x00872716
#define DDR_PHY_DTPR5_TWTR_SHIFT                               0
#define DDR_PHY_DTPR5_TWTR_MASK                                0x0000001FU

/*
* PUB Write Latency Enable
*/
#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL 
#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT 
#undef DDR_PHY_DTPR6_PUBWLEN_MASK 
#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL                           0x00000505
#define DDR_PHY_DTPR6_PUBWLEN_SHIFT                            31
#define DDR_PHY_DTPR6_PUBWLEN_MASK                             0x80000000U

/*
* PUB Read Latency Enable
*/
#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL 
#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT 
#undef DDR_PHY_DTPR6_PUBRLEN_MASK 
#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL                           0x00000505
#define DDR_PHY_DTPR6_PUBRLEN_SHIFT                            30
#define DDR_PHY_DTPR6_PUBRLEN_MASK                             0x40000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 
#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 
#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK 
#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL                    0x00000505
#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT                     14
#define DDR_PHY_DTPR6_RESERVED_29_14_MASK                      0x3FFFC000U

/*
* Write Latency
*/
#undef DDR_PHY_DTPR6_PUBWL_DEFVAL 
#undef DDR_PHY_DTPR6_PUBWL_SHIFT 
#undef DDR_PHY_DTPR6_PUBWL_MASK 
#define DDR_PHY_DTPR6_PUBWL_DEFVAL                             0x00000505
#define DDR_PHY_DTPR6_PUBWL_SHIFT                              8
#define DDR_PHY_DTPR6_PUBWL_MASK                               0x00003F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK 
#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL                      0x00000505
#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT                       6
#define DDR_PHY_DTPR6_RESERVED_7_6_MASK                        0x000000C0U

/*
* Read Latency
*/
#undef DDR_PHY_DTPR6_PUBRL_DEFVAL 
#undef DDR_PHY_DTPR6_PUBRL_SHIFT 
#undef DDR_PHY_DTPR6_PUBRL_MASK 
#define DDR_PHY_DTPR6_PUBRL_DEFVAL                             0x00000505
#define DDR_PHY_DTPR6_PUBRL_SHIFT                              0
#define DDR_PHY_DTPR6_PUBRL_MASK                               0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 
#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL                   0x08400020
#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT                    31
#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK                     0x80000000U

/*
* RDMIMM Quad CS Enable
*/
#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 
#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK 
#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL                         0x08400020
#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT                          30
#define DDR_PHY_RDIMMGCR0_QCSEN_MASK                           0x40000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 
#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL                0x08400020
#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT                 28
#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK                  0x30000000U

/*
* RDIMM Outputs I/O Mode
*/
#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 
#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL                      0x08400020
#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT                       27
#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK                        0x08000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 
#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL                0x08400020
#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT                 24
#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK                  0x07000000U

/*
* ERROUT# Output Enable
*/
#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 
#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 
#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL                      0x08400020
#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT                       23
#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK                        0x00800000U

/*
* ERROUT# I/O Mode
*/
#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 
#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 
#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL                     0x08400020
#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT                      22
#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK                       0x00400000U

/*
* ERROUT# Power Down Receiver
*/
#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 
#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 
#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL                     0x08400020
#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT                      21
#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK                       0x00200000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 
#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL                   0x08400020
#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT                    20
#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK                     0x00100000U

/*
* ERROUT# On-Die Termination
*/
#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 
#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 
#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL                     0x08400020
#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT                      19
#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK                       0x00080000U

/*
* Load Reduced DIMM
*/
#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 
#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK 
#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL                        0x08400020
#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT                         18
#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK                          0x00040000U

/*
* PAR_IN I/O Mode
*/
#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 
#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK 
#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL                      0x08400020
#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT                       17
#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK                        0x00020000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 
#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL                 0x08400020
#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT                  8
#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK                   0x0001FF00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 
#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL                 0x08400020
#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT                  6
#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK                   0x000000C0U

/*
* Rank Mirror Enable.
*/
#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 
#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL                      0x08400020
#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT                       4
#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK                        0x00000030U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 
#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL                    0x08400020
#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT                     3
#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK                      0x00000008U

/*
* Stop on Parity Error
*/
#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 
#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK 
#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL                        0x08400020
#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT                         2
#define DDR_PHY_RDIMMGCR0_SOPERR_MASK                          0x00000004U

/*
* Parity Error No Registering
*/
#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 
#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 
#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL                      0x08400020
#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT                       1
#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK                        0x00000002U

/*
* Registered DIMM
*/
#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 
#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 
#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK 
#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL                         0x08400020
#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT                          0
#define DDR_PHY_RDIMMGCR0_RDIMM_MASK                           0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 
#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 
#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL                0x00000C80
#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT                 29
#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK                  0xE0000000U

/*
* Address [17] B-side Inversion Disable
*/
#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT 
#undef DDR_PHY_RDIMMGCR1_A17BID_MASK 
#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL                        0x00000C80
#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT                         28
#define DDR_PHY_RDIMMGCR1_A17BID_MASK                          0x10000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 
#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 
#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL                   0x00000C80
#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT                    27
#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK                     0x08000000U

/*
* Command word to command word programming delay
*/
#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 
#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 
#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL                     0x00000C80
#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT                      24
#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK                       0x07000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 
#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 
#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL                   0x00000C80
#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT                    23
#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK                     0x00800000U

/*
* Command word to command word programming delay
*/
#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 
#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 
#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL                      0x00000C80
#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT                       20
#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK                        0x00700000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 
#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 
#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL                   0x00000C80
#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT                    19
#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK                     0x00080000U

/*
* Command word to command word programming delay
*/
#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 
#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK 
#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL                        0x00000C80
#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT                         16
#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK                          0x00070000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 
#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 
#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL                0x00000C80
#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT                 14
#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK                  0x0000C000U

/*
* Stabilization time
*/
#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 
#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 
#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 
#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL                       0x00000C80
#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT                        0
#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK                         0x00003FFFU

/*
* DDR4/DDR3 Control Word 7
*/
#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL 
#undef DDR_PHY_RDIMMCR0_RC7_SHIFT 
#undef DDR_PHY_RDIMMCR0_RC7_MASK 
#define DDR_PHY_RDIMMCR0_RC7_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR0_RC7_SHIFT                             28
#define DDR_PHY_RDIMMCR0_RC7_MASK                              0xF0000000U

/*
* DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
*/
#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL 
#undef DDR_PHY_RDIMMCR0_RC6_SHIFT 
#undef DDR_PHY_RDIMMCR0_RC6_MASK 
#define DDR_PHY_RDIMMCR0_RC6_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR0_RC6_SHIFT                             24
#define DDR_PHY_RDIMMCR0_RC6_MASK                              0x0F000000U

/*
* DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
*/
#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL 
#undef DDR_PHY_RDIMMCR0_RC5_SHIFT 
#undef DDR_PHY_RDIMMCR0_RC5_MASK 
#define DDR_PHY_RDIMMCR0_RC5_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR0_RC5_SHIFT                             20
#define DDR_PHY_RDIMMCR0_RC5_MASK                              0x00F00000U

/*
* DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control
    * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont
    * rol Word)
*/
#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL 
#undef DDR_PHY_RDIMMCR0_RC4_SHIFT 
#undef DDR_PHY_RDIMMCR0_RC4_MASK 
#define DDR_PHY_RDIMMCR0_RC4_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR0_RC4_SHIFT                             16
#define DDR_PHY_RDIMMCR0_RC4_MASK                              0x000F0000U

/*
* DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo
    * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri
    * cs Control Word)
*/
#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL 
#undef DDR_PHY_RDIMMCR0_RC3_SHIFT 
#undef DDR_PHY_RDIMMCR0_RC3_MASK 
#define DDR_PHY_RDIMMCR0_RC3_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR0_RC3_SHIFT                             12
#define DDR_PHY_RDIMMCR0_RC3_MASK                              0x0000F000U

/*
* DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2
    * (Timing Control Word)
*/
#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL 
#undef DDR_PHY_RDIMMCR0_RC2_SHIFT 
#undef DDR_PHY_RDIMMCR0_RC2_MASK 
#define DDR_PHY_RDIMMCR0_RC2_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR0_RC2_SHIFT                             8
#define DDR_PHY_RDIMMCR0_RC2_MASK                              0x00000F00U

/*
* DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
*/
#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL 
#undef DDR_PHY_RDIMMCR0_RC1_SHIFT 
#undef DDR_PHY_RDIMMCR0_RC1_MASK 
#define DDR_PHY_RDIMMCR0_RC1_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR0_RC1_SHIFT                             4
#define DDR_PHY_RDIMMCR0_RC1_MASK                              0x000000F0U

/*
* DDR4/DDR3 Control Word 0 (Global Features Control Word)
*/
#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL 
#undef DDR_PHY_RDIMMCR0_RC0_SHIFT 
#undef DDR_PHY_RDIMMCR0_RC0_MASK 
#define DDR_PHY_RDIMMCR0_RC0_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR0_RC0_SHIFT                             0
#define DDR_PHY_RDIMMCR0_RC0_MASK                              0x0000000FU

/*
* Control Word 15
*/
#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL 
#undef DDR_PHY_RDIMMCR1_RC15_SHIFT 
#undef DDR_PHY_RDIMMCR1_RC15_MASK 
#define DDR_PHY_RDIMMCR1_RC15_DEFVAL                           0x00000000
#define DDR_PHY_RDIMMCR1_RC15_SHIFT                            28
#define DDR_PHY_RDIMMCR1_RC15_MASK                             0xF0000000U

/*
* DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
*/
#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL 
#undef DDR_PHY_RDIMMCR1_RC14_SHIFT 
#undef DDR_PHY_RDIMMCR1_RC14_MASK 
#define DDR_PHY_RDIMMCR1_RC14_DEFVAL                           0x00000000
#define DDR_PHY_RDIMMCR1_RC14_SHIFT                            24
#define DDR_PHY_RDIMMCR1_RC14_MASK                             0x0F000000U

/*
* DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
*/
#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL 
#undef DDR_PHY_RDIMMCR1_RC13_SHIFT 
#undef DDR_PHY_RDIMMCR1_RC13_MASK 
#define DDR_PHY_RDIMMCR1_RC13_DEFVAL                           0x00000000
#define DDR_PHY_RDIMMCR1_RC13_SHIFT                            20
#define DDR_PHY_RDIMMCR1_RC13_MASK                             0x00F00000U

/*
* DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
*/
#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL 
#undef DDR_PHY_RDIMMCR1_RC12_SHIFT 
#undef DDR_PHY_RDIMMCR1_RC12_MASK 
#define DDR_PHY_RDIMMCR1_RC12_DEFVAL                           0x00000000
#define DDR_PHY_RDIMMCR1_RC12_SHIFT                            16
#define DDR_PHY_RDIMMCR1_RC12_MASK                             0x000F0000U

/*
* DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo
    * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word)
*/
#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL 
#undef DDR_PHY_RDIMMCR1_RC11_SHIFT 
#undef DDR_PHY_RDIMMCR1_RC11_MASK 
#define DDR_PHY_RDIMMCR1_RC11_DEFVAL                           0x00000000
#define DDR_PHY_RDIMMCR1_RC11_SHIFT                            12
#define DDR_PHY_RDIMMCR1_RC11_MASK                             0x0000F000U

/*
* DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
*/
#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL 
#undef DDR_PHY_RDIMMCR1_RC10_SHIFT 
#undef DDR_PHY_RDIMMCR1_RC10_MASK 
#define DDR_PHY_RDIMMCR1_RC10_DEFVAL                           0x00000000
#define DDR_PHY_RDIMMCR1_RC10_SHIFT                            8
#define DDR_PHY_RDIMMCR1_RC10_MASK                             0x00000F00U

/*
* DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
*/
#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL 
#undef DDR_PHY_RDIMMCR1_RC9_SHIFT 
#undef DDR_PHY_RDIMMCR1_RC9_MASK 
#define DDR_PHY_RDIMMCR1_RC9_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR1_RC9_SHIFT                             4
#define DDR_PHY_RDIMMCR1_RC9_MASK                              0x000000F0U

/*
* DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con
    * trol Word 8 (Additional Input Bus Termination Setting Control Word)
*/
#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL 
#undef DDR_PHY_RDIMMCR1_RC8_SHIFT 
#undef DDR_PHY_RDIMMCR1_RC8_MASK 
#define DDR_PHY_RDIMMCR1_RC8_DEFVAL                            0x00000000
#define DDR_PHY_RDIMMCR1_RC8_SHIFT                             0
#define DDR_PHY_RDIMMCR1_RC8_MASK                              0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR0_RESERVED_31_8_MASK 
#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL                       0x00000052
#define DDR_PHY_MR0_RESERVED_31_8_SHIFT                        8
#define DDR_PHY_MR0_RESERVED_31_8_MASK                         0xFFFFFF00U

/*
* CA Terminating Rank
*/
#undef DDR_PHY_MR0_CATR_DEFVAL 
#undef DDR_PHY_MR0_CATR_SHIFT 
#undef DDR_PHY_MR0_CATR_MASK 
#define DDR_PHY_MR0_CATR_DEFVAL                                0x00000052
#define DDR_PHY_MR0_CATR_SHIFT                                 7
#define DDR_PHY_MR0_CATR_MASK                                  0x00000080U

/*
* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
    * be programmed to 0x0.
*/
#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL 
#undef DDR_PHY_MR0_RSVD_6_5_SHIFT 
#undef DDR_PHY_MR0_RSVD_6_5_MASK 
#define DDR_PHY_MR0_RSVD_6_5_DEFVAL                            0x00000052
#define DDR_PHY_MR0_RSVD_6_5_SHIFT                             5
#define DDR_PHY_MR0_RSVD_6_5_MASK                              0x00000060U

/*
* Built-in Self-Test for RZQ
*/
#undef DDR_PHY_MR0_RZQI_DEFVAL 
#undef DDR_PHY_MR0_RZQI_SHIFT 
#undef DDR_PHY_MR0_RZQI_MASK 
#define DDR_PHY_MR0_RZQI_DEFVAL                                0x00000052
#define DDR_PHY_MR0_RZQI_SHIFT                                 3
#define DDR_PHY_MR0_RZQI_MASK                                  0x00000018U

/*
* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
    * be programmed to 0x0.
*/
#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL 
#undef DDR_PHY_MR0_RSVD_2_0_SHIFT 
#undef DDR_PHY_MR0_RSVD_2_0_MASK 
#define DDR_PHY_MR0_RSVD_2_0_DEFVAL                            0x00000052
#define DDR_PHY_MR0_RSVD_2_0_SHIFT                             0
#define DDR_PHY_MR0_RSVD_2_0_MASK                              0x00000007U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR1_RESERVED_31_8_MASK 
#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL                       0x00000004
#define DDR_PHY_MR1_RESERVED_31_8_SHIFT                        8
#define DDR_PHY_MR1_RESERVED_31_8_MASK                         0xFFFFFF00U

/*
* Read Postamble Length
*/
#undef DDR_PHY_MR1_RDPST_DEFVAL 
#undef DDR_PHY_MR1_RDPST_SHIFT 
#undef DDR_PHY_MR1_RDPST_MASK 
#define DDR_PHY_MR1_RDPST_DEFVAL                               0x00000004
#define DDR_PHY_MR1_RDPST_SHIFT                                7
#define DDR_PHY_MR1_RDPST_MASK                                 0x00000080U

/*
* Write-recovery for auto-precharge command
*/
#undef DDR_PHY_MR1_NWR_DEFVAL 
#undef DDR_PHY_MR1_NWR_SHIFT 
#undef DDR_PHY_MR1_NWR_MASK 
#define DDR_PHY_MR1_NWR_DEFVAL                                 0x00000004
#define DDR_PHY_MR1_NWR_SHIFT                                  4
#define DDR_PHY_MR1_NWR_MASK                                   0x00000070U

/*
* Read Preamble Length
*/
#undef DDR_PHY_MR1_RDPRE_DEFVAL 
#undef DDR_PHY_MR1_RDPRE_SHIFT 
#undef DDR_PHY_MR1_RDPRE_MASK 
#define DDR_PHY_MR1_RDPRE_DEFVAL                               0x00000004
#define DDR_PHY_MR1_RDPRE_SHIFT                                3
#define DDR_PHY_MR1_RDPRE_MASK                                 0x00000008U

/*
* Write Preamble Length
*/
#undef DDR_PHY_MR1_WRPRE_DEFVAL 
#undef DDR_PHY_MR1_WRPRE_SHIFT 
#undef DDR_PHY_MR1_WRPRE_MASK 
#define DDR_PHY_MR1_WRPRE_DEFVAL                               0x00000004
#define DDR_PHY_MR1_WRPRE_SHIFT                                2
#define DDR_PHY_MR1_WRPRE_MASK                                 0x00000004U

/*
* Burst Length
*/
#undef DDR_PHY_MR1_BL_DEFVAL 
#undef DDR_PHY_MR1_BL_SHIFT 
#undef DDR_PHY_MR1_BL_MASK 
#define DDR_PHY_MR1_BL_DEFVAL                                  0x00000004
#define DDR_PHY_MR1_BL_SHIFT                                   0
#define DDR_PHY_MR1_BL_MASK                                    0x00000003U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR2_RESERVED_31_8_MASK 
#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL                       0x00000000
#define DDR_PHY_MR2_RESERVED_31_8_SHIFT                        8
#define DDR_PHY_MR2_RESERVED_31_8_MASK                         0xFFFFFF00U

/*
* Write Leveling
*/
#undef DDR_PHY_MR2_WRL_DEFVAL 
#undef DDR_PHY_MR2_WRL_SHIFT 
#undef DDR_PHY_MR2_WRL_MASK 
#define DDR_PHY_MR2_WRL_DEFVAL                                 0x00000000
#define DDR_PHY_MR2_WRL_SHIFT                                  7
#define DDR_PHY_MR2_WRL_MASK                                   0x00000080U

/*
* Write Latency Set
*/
#undef DDR_PHY_MR2_WLS_DEFVAL 
#undef DDR_PHY_MR2_WLS_SHIFT 
#undef DDR_PHY_MR2_WLS_MASK 
#define DDR_PHY_MR2_WLS_DEFVAL                                 0x00000000
#define DDR_PHY_MR2_WLS_SHIFT                                  6
#define DDR_PHY_MR2_WLS_MASK                                   0x00000040U

/*
* Write Latency
*/
#undef DDR_PHY_MR2_WL_DEFVAL 
#undef DDR_PHY_MR2_WL_SHIFT 
#undef DDR_PHY_MR2_WL_MASK 
#define DDR_PHY_MR2_WL_DEFVAL                                  0x00000000
#define DDR_PHY_MR2_WL_SHIFT                                   3
#define DDR_PHY_MR2_WL_MASK                                    0x00000038U

/*
* Read Latency
*/
#undef DDR_PHY_MR2_RL_DEFVAL 
#undef DDR_PHY_MR2_RL_SHIFT 
#undef DDR_PHY_MR2_RL_MASK 
#define DDR_PHY_MR2_RL_DEFVAL                                  0x00000000
#define DDR_PHY_MR2_RL_SHIFT                                   0
#define DDR_PHY_MR2_RL_MASK                                    0x00000007U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR3_RESERVED_31_8_MASK 
#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL                       0x00000031
#define DDR_PHY_MR3_RESERVED_31_8_SHIFT                        8
#define DDR_PHY_MR3_RESERVED_31_8_MASK                         0xFFFFFF00U

/*
* DBI-Write Enable
*/
#undef DDR_PHY_MR3_DBIWR_DEFVAL 
#undef DDR_PHY_MR3_DBIWR_SHIFT 
#undef DDR_PHY_MR3_DBIWR_MASK 
#define DDR_PHY_MR3_DBIWR_DEFVAL                               0x00000031
#define DDR_PHY_MR3_DBIWR_SHIFT                                7
#define DDR_PHY_MR3_DBIWR_MASK                                 0x00000080U

/*
* DBI-Read Enable
*/
#undef DDR_PHY_MR3_DBIRD_DEFVAL 
#undef DDR_PHY_MR3_DBIRD_SHIFT 
#undef DDR_PHY_MR3_DBIRD_MASK 
#define DDR_PHY_MR3_DBIRD_DEFVAL                               0x00000031
#define DDR_PHY_MR3_DBIRD_SHIFT                                6
#define DDR_PHY_MR3_DBIRD_MASK                                 0x00000040U

/*
* Pull-down Drive Strength
*/
#undef DDR_PHY_MR3_PDDS_DEFVAL 
#undef DDR_PHY_MR3_PDDS_SHIFT 
#undef DDR_PHY_MR3_PDDS_MASK 
#define DDR_PHY_MR3_PDDS_DEFVAL                                0x00000031
#define DDR_PHY_MR3_PDDS_SHIFT                                 3
#define DDR_PHY_MR3_PDDS_MASK                                  0x00000038U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR3_RSVD_DEFVAL 
#undef DDR_PHY_MR3_RSVD_SHIFT 
#undef DDR_PHY_MR3_RSVD_MASK 
#define DDR_PHY_MR3_RSVD_DEFVAL                                0x00000031
#define DDR_PHY_MR3_RSVD_SHIFT                                 2
#define DDR_PHY_MR3_RSVD_MASK                                  0x00000004U

/*
* Write Postamble Length
*/
#undef DDR_PHY_MR3_WRPST_DEFVAL 
#undef DDR_PHY_MR3_WRPST_SHIFT 
#undef DDR_PHY_MR3_WRPST_MASK 
#define DDR_PHY_MR3_WRPST_DEFVAL                               0x00000031
#define DDR_PHY_MR3_WRPST_SHIFT                                1
#define DDR_PHY_MR3_WRPST_MASK                                 0x00000002U

/*
* Pull-up Calibration Point
*/
#undef DDR_PHY_MR3_PUCAL_DEFVAL 
#undef DDR_PHY_MR3_PUCAL_SHIFT 
#undef DDR_PHY_MR3_PUCAL_MASK 
#define DDR_PHY_MR3_PUCAL_DEFVAL                               0x00000031
#define DDR_PHY_MR3_PUCAL_SHIFT                                0
#define DDR_PHY_MR3_PUCAL_MASK                                 0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL 
#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT 
#undef DDR_PHY_MR4_RESERVED_31_16_MASK 
#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL                      0x00000000
#define DDR_PHY_MR4_RESERVED_31_16_SHIFT                       16
#define DDR_PHY_MR4_RESERVED_31_16_MASK                        0xFFFF0000U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL 
#undef DDR_PHY_MR4_RSVD_15_13_SHIFT 
#undef DDR_PHY_MR4_RSVD_15_13_MASK 
#define DDR_PHY_MR4_RSVD_15_13_DEFVAL                          0x00000000
#define DDR_PHY_MR4_RSVD_15_13_SHIFT                           13
#define DDR_PHY_MR4_RSVD_15_13_MASK                            0x0000E000U

/*
* Write Preamble
*/
#undef DDR_PHY_MR4_WRP_DEFVAL 
#undef DDR_PHY_MR4_WRP_SHIFT 
#undef DDR_PHY_MR4_WRP_MASK 
#define DDR_PHY_MR4_WRP_DEFVAL                                 0x00000000
#define DDR_PHY_MR4_WRP_SHIFT                                  12
#define DDR_PHY_MR4_WRP_MASK                                   0x00001000U

/*
* Read Preamble
*/
#undef DDR_PHY_MR4_RDP_DEFVAL 
#undef DDR_PHY_MR4_RDP_SHIFT 
#undef DDR_PHY_MR4_RDP_MASK 
#define DDR_PHY_MR4_RDP_DEFVAL                                 0x00000000
#define DDR_PHY_MR4_RDP_SHIFT                                  11
#define DDR_PHY_MR4_RDP_MASK                                   0x00000800U

/*
* Read Preamble Training Mode
*/
#undef DDR_PHY_MR4_RPTM_DEFVAL 
#undef DDR_PHY_MR4_RPTM_SHIFT 
#undef DDR_PHY_MR4_RPTM_MASK 
#define DDR_PHY_MR4_RPTM_DEFVAL                                0x00000000
#define DDR_PHY_MR4_RPTM_SHIFT                                 10
#define DDR_PHY_MR4_RPTM_MASK                                  0x00000400U

/*
* Self Refresh Abort
*/
#undef DDR_PHY_MR4_SRA_DEFVAL 
#undef DDR_PHY_MR4_SRA_SHIFT 
#undef DDR_PHY_MR4_SRA_MASK 
#define DDR_PHY_MR4_SRA_DEFVAL                                 0x00000000
#define DDR_PHY_MR4_SRA_SHIFT                                  9
#define DDR_PHY_MR4_SRA_MASK                                   0x00000200U

/*
* CS to Command Latency Mode
*/
#undef DDR_PHY_MR4_CS2CMDL_DEFVAL 
#undef DDR_PHY_MR4_CS2CMDL_SHIFT 
#undef DDR_PHY_MR4_CS2CMDL_MASK 
#define DDR_PHY_MR4_CS2CMDL_DEFVAL                             0x00000000
#define DDR_PHY_MR4_CS2CMDL_SHIFT                              6
#define DDR_PHY_MR4_CS2CMDL_MASK                               0x000001C0U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR4_RSVD1_DEFVAL 
#undef DDR_PHY_MR4_RSVD1_SHIFT 
#undef DDR_PHY_MR4_RSVD1_MASK 
#define DDR_PHY_MR4_RSVD1_DEFVAL                               0x00000000
#define DDR_PHY_MR4_RSVD1_SHIFT                                5
#define DDR_PHY_MR4_RSVD1_MASK                                 0x00000020U

/*
* Internal VREF Monitor
*/
#undef DDR_PHY_MR4_IVM_DEFVAL 
#undef DDR_PHY_MR4_IVM_SHIFT 
#undef DDR_PHY_MR4_IVM_MASK 
#define DDR_PHY_MR4_IVM_DEFVAL                                 0x00000000
#define DDR_PHY_MR4_IVM_SHIFT                                  4
#define DDR_PHY_MR4_IVM_MASK                                   0x00000010U

/*
* Temperature Controlled Refresh Mode
*/
#undef DDR_PHY_MR4_TCRM_DEFVAL 
#undef DDR_PHY_MR4_TCRM_SHIFT 
#undef DDR_PHY_MR4_TCRM_MASK 
#define DDR_PHY_MR4_TCRM_DEFVAL                                0x00000000
#define DDR_PHY_MR4_TCRM_SHIFT                                 3
#define DDR_PHY_MR4_TCRM_MASK                                  0x00000008U

/*
* Temperature Controlled Refresh Range
*/
#undef DDR_PHY_MR4_TCRR_DEFVAL 
#undef DDR_PHY_MR4_TCRR_SHIFT 
#undef DDR_PHY_MR4_TCRR_MASK 
#define DDR_PHY_MR4_TCRR_DEFVAL                                0x00000000
#define DDR_PHY_MR4_TCRR_SHIFT                                 2
#define DDR_PHY_MR4_TCRR_MASK                                  0x00000004U

/*
* Maximum Power Down Mode
*/
#undef DDR_PHY_MR4_MPDM_DEFVAL 
#undef DDR_PHY_MR4_MPDM_SHIFT 
#undef DDR_PHY_MR4_MPDM_MASK 
#define DDR_PHY_MR4_MPDM_DEFVAL                                0x00000000
#define DDR_PHY_MR4_MPDM_SHIFT                                 1
#define DDR_PHY_MR4_MPDM_MASK                                  0x00000002U

/*
* This is a JEDEC reserved bit and is recommended by JEDEC to be programme
    * d to 0x0.
*/
#undef DDR_PHY_MR4_RSVD_0_DEFVAL 
#undef DDR_PHY_MR4_RSVD_0_SHIFT 
#undef DDR_PHY_MR4_RSVD_0_MASK 
#define DDR_PHY_MR4_RSVD_0_DEFVAL                              0x00000000
#define DDR_PHY_MR4_RSVD_0_SHIFT                               0
#define DDR_PHY_MR4_RSVD_0_MASK                                0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL 
#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT 
#undef DDR_PHY_MR5_RESERVED_31_16_MASK 
#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL                      0x00000000
#define DDR_PHY_MR5_RESERVED_31_16_SHIFT                       16
#define DDR_PHY_MR5_RESERVED_31_16_MASK                        0xFFFF0000U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR5_RSVD_DEFVAL 
#undef DDR_PHY_MR5_RSVD_SHIFT 
#undef DDR_PHY_MR5_RSVD_MASK 
#define DDR_PHY_MR5_RSVD_DEFVAL                                0x00000000
#define DDR_PHY_MR5_RSVD_SHIFT                                 13
#define DDR_PHY_MR5_RSVD_MASK                                  0x0000E000U

/*
* Read DBI
*/
#undef DDR_PHY_MR5_RDBI_DEFVAL 
#undef DDR_PHY_MR5_RDBI_SHIFT 
#undef DDR_PHY_MR5_RDBI_MASK 
#define DDR_PHY_MR5_RDBI_DEFVAL                                0x00000000
#define DDR_PHY_MR5_RDBI_SHIFT                                 12
#define DDR_PHY_MR5_RDBI_MASK                                  0x00001000U

/*
* Write DBI
*/
#undef DDR_PHY_MR5_WDBI_DEFVAL 
#undef DDR_PHY_MR5_WDBI_SHIFT 
#undef DDR_PHY_MR5_WDBI_MASK 
#define DDR_PHY_MR5_WDBI_DEFVAL                                0x00000000
#define DDR_PHY_MR5_WDBI_SHIFT                                 11
#define DDR_PHY_MR5_WDBI_MASK                                  0x00000800U

/*
* Data Mask
*/
#undef DDR_PHY_MR5_DM_DEFVAL 
#undef DDR_PHY_MR5_DM_SHIFT 
#undef DDR_PHY_MR5_DM_MASK 
#define DDR_PHY_MR5_DM_DEFVAL                                  0x00000000
#define DDR_PHY_MR5_DM_SHIFT                                   10
#define DDR_PHY_MR5_DM_MASK                                    0x00000400U

/*
* CA Parity Persistent Error
*/
#undef DDR_PHY_MR5_CAPPE_DEFVAL 
#undef DDR_PHY_MR5_CAPPE_SHIFT 
#undef DDR_PHY_MR5_CAPPE_MASK 
#define DDR_PHY_MR5_CAPPE_DEFVAL                               0x00000000
#define DDR_PHY_MR5_CAPPE_SHIFT                                9
#define DDR_PHY_MR5_CAPPE_MASK                                 0x00000200U

/*
* RTT_PARK
*/
#undef DDR_PHY_MR5_RTTPARK_DEFVAL 
#undef DDR_PHY_MR5_RTTPARK_SHIFT 
#undef DDR_PHY_MR5_RTTPARK_MASK 
#define DDR_PHY_MR5_RTTPARK_DEFVAL                             0x00000000
#define DDR_PHY_MR5_RTTPARK_SHIFT                              6
#define DDR_PHY_MR5_RTTPARK_MASK                               0x000001C0U

/*
* ODT Input Buffer during Power Down mode
*/
#undef DDR_PHY_MR5_ODTIBPD_DEFVAL 
#undef DDR_PHY_MR5_ODTIBPD_SHIFT 
#undef DDR_PHY_MR5_ODTIBPD_MASK 
#define DDR_PHY_MR5_ODTIBPD_DEFVAL                             0x00000000
#define DDR_PHY_MR5_ODTIBPD_SHIFT                              5
#define DDR_PHY_MR5_ODTIBPD_MASK                               0x00000020U

/*
* C/A Parity Error Status
*/
#undef DDR_PHY_MR5_CAPES_DEFVAL 
#undef DDR_PHY_MR5_CAPES_SHIFT 
#undef DDR_PHY_MR5_CAPES_MASK 
#define DDR_PHY_MR5_CAPES_DEFVAL                               0x00000000
#define DDR_PHY_MR5_CAPES_SHIFT                                4
#define DDR_PHY_MR5_CAPES_MASK                                 0x00000010U

/*
* CRC Error Clear
*/
#undef DDR_PHY_MR5_CRCEC_DEFVAL 
#undef DDR_PHY_MR5_CRCEC_SHIFT 
#undef DDR_PHY_MR5_CRCEC_MASK 
#define DDR_PHY_MR5_CRCEC_DEFVAL                               0x00000000
#define DDR_PHY_MR5_CRCEC_SHIFT                                3
#define DDR_PHY_MR5_CRCEC_MASK                                 0x00000008U

/*
* C/A Parity Latency Mode
*/
#undef DDR_PHY_MR5_CAPM_DEFVAL 
#undef DDR_PHY_MR5_CAPM_SHIFT 
#undef DDR_PHY_MR5_CAPM_MASK 
#define DDR_PHY_MR5_CAPM_DEFVAL                                0x00000000
#define DDR_PHY_MR5_CAPM_SHIFT                                 0
#define DDR_PHY_MR5_CAPM_MASK                                  0x00000007U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL 
#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT 
#undef DDR_PHY_MR6_RESERVED_31_16_MASK 
#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL                      0x00000000
#define DDR_PHY_MR6_RESERVED_31_16_SHIFT                       16
#define DDR_PHY_MR6_RESERVED_31_16_MASK                        0xFFFF0000U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL 
#undef DDR_PHY_MR6_RSVD_15_13_SHIFT 
#undef DDR_PHY_MR6_RSVD_15_13_MASK 
#define DDR_PHY_MR6_RSVD_15_13_DEFVAL                          0x00000000
#define DDR_PHY_MR6_RSVD_15_13_SHIFT                           13
#define DDR_PHY_MR6_RSVD_15_13_MASK                            0x0000E000U

/*
* CAS_n to CAS_n command delay for same bank group (tCCD_L)
*/
#undef DDR_PHY_MR6_TCCDL_DEFVAL 
#undef DDR_PHY_MR6_TCCDL_SHIFT 
#undef DDR_PHY_MR6_TCCDL_MASK 
#define DDR_PHY_MR6_TCCDL_DEFVAL                               0x00000000
#define DDR_PHY_MR6_TCCDL_SHIFT                                10
#define DDR_PHY_MR6_TCCDL_MASK                                 0x00001C00U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL 
#undef DDR_PHY_MR6_RSVD_9_8_SHIFT 
#undef DDR_PHY_MR6_RSVD_9_8_MASK 
#define DDR_PHY_MR6_RSVD_9_8_DEFVAL                            0x00000000
#define DDR_PHY_MR6_RSVD_9_8_SHIFT                             8
#define DDR_PHY_MR6_RSVD_9_8_MASK                              0x00000300U

/*
* VrefDQ Training Enable
*/
#undef DDR_PHY_MR6_VDDQTEN_DEFVAL 
#undef DDR_PHY_MR6_VDDQTEN_SHIFT 
#undef DDR_PHY_MR6_VDDQTEN_MASK 
#define DDR_PHY_MR6_VDDQTEN_DEFVAL                             0x00000000
#define DDR_PHY_MR6_VDDQTEN_SHIFT                              7
#define DDR_PHY_MR6_VDDQTEN_MASK                               0x00000080U

/*
* VrefDQ Training Range
*/
#undef DDR_PHY_MR6_VDQTRG_DEFVAL 
#undef DDR_PHY_MR6_VDQTRG_SHIFT 
#undef DDR_PHY_MR6_VDQTRG_MASK 
#define DDR_PHY_MR6_VDQTRG_DEFVAL                              0x00000000
#define DDR_PHY_MR6_VDQTRG_SHIFT                               6
#define DDR_PHY_MR6_VDQTRG_MASK                                0x00000040U

/*
* VrefDQ Training Values
*/
#undef DDR_PHY_MR6_VDQTVAL_DEFVAL 
#undef DDR_PHY_MR6_VDQTVAL_SHIFT 
#undef DDR_PHY_MR6_VDQTVAL_MASK 
#define DDR_PHY_MR6_VDQTVAL_DEFVAL                             0x00000000
#define DDR_PHY_MR6_VDQTVAL_SHIFT                              0
#define DDR_PHY_MR6_VDQTVAL_MASK                               0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR11_RESERVED_31_8_MASK 
#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL                      0x00000000
#define DDR_PHY_MR11_RESERVED_31_8_SHIFT                       8
#define DDR_PHY_MR11_RESERVED_31_8_MASK                        0xFFFFFF00U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR11_RSVD_DEFVAL 
#undef DDR_PHY_MR11_RSVD_SHIFT 
#undef DDR_PHY_MR11_RSVD_MASK 
#define DDR_PHY_MR11_RSVD_DEFVAL                               0x00000000
#define DDR_PHY_MR11_RSVD_SHIFT                                3
#define DDR_PHY_MR11_RSVD_MASK                                 0x000000F8U

/*
* Power Down Control
*/
#undef DDR_PHY_MR11_PDCTL_DEFVAL 
#undef DDR_PHY_MR11_PDCTL_SHIFT 
#undef DDR_PHY_MR11_PDCTL_MASK 
#define DDR_PHY_MR11_PDCTL_DEFVAL                              0x00000000
#define DDR_PHY_MR11_PDCTL_SHIFT                               2
#define DDR_PHY_MR11_PDCTL_MASK                                0x00000004U

/*
* DQ Bus Receiver On-Die-Termination
*/
#undef DDR_PHY_MR11_DQODT_DEFVAL 
#undef DDR_PHY_MR11_DQODT_SHIFT 
#undef DDR_PHY_MR11_DQODT_MASK 
#define DDR_PHY_MR11_DQODT_DEFVAL                              0x00000000
#define DDR_PHY_MR11_DQODT_SHIFT                               0
#define DDR_PHY_MR11_DQODT_MASK                                0x00000003U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR12_RESERVED_31_8_MASK 
#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL                      0x0000004D
#define DDR_PHY_MR12_RESERVED_31_8_SHIFT                       8
#define DDR_PHY_MR12_RESERVED_31_8_MASK                        0xFFFFFF00U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR12_RSVD_DEFVAL 
#undef DDR_PHY_MR12_RSVD_SHIFT 
#undef DDR_PHY_MR12_RSVD_MASK 
#define DDR_PHY_MR12_RSVD_DEFVAL                               0x0000004D
#define DDR_PHY_MR12_RSVD_SHIFT                                7
#define DDR_PHY_MR12_RSVD_MASK                                 0x00000080U

/*
* VREF_CA Range Select.
*/
#undef DDR_PHY_MR12_VR_CA_DEFVAL 
#undef DDR_PHY_MR12_VR_CA_SHIFT 
#undef DDR_PHY_MR12_VR_CA_MASK 
#define DDR_PHY_MR12_VR_CA_DEFVAL                              0x0000004D
#define DDR_PHY_MR12_VR_CA_SHIFT                               6
#define DDR_PHY_MR12_VR_CA_MASK                                0x00000040U

/*
* Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
*/
#undef DDR_PHY_MR12_VREF_CA_DEFVAL 
#undef DDR_PHY_MR12_VREF_CA_SHIFT 
#undef DDR_PHY_MR12_VREF_CA_MASK 
#define DDR_PHY_MR12_VREF_CA_DEFVAL                            0x0000004D
#define DDR_PHY_MR12_VREF_CA_SHIFT                             0
#define DDR_PHY_MR12_VREF_CA_MASK                              0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR13_RESERVED_31_8_MASK 
#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL                      0x00000000
#define DDR_PHY_MR13_RESERVED_31_8_SHIFT                       8
#define DDR_PHY_MR13_RESERVED_31_8_MASK                        0xFFFFFF00U

/*
* Frequency Set Point Operation Mode
*/
#undef DDR_PHY_MR13_FSPOP_DEFVAL 
#undef DDR_PHY_MR13_FSPOP_SHIFT 
#undef DDR_PHY_MR13_FSPOP_MASK 
#define DDR_PHY_MR13_FSPOP_DEFVAL                              0x00000000
#define DDR_PHY_MR13_FSPOP_SHIFT                               7
#define DDR_PHY_MR13_FSPOP_MASK                                0x00000080U

/*
* Frequency Set Point Write Enable
*/
#undef DDR_PHY_MR13_FSPWR_DEFVAL 
#undef DDR_PHY_MR13_FSPWR_SHIFT 
#undef DDR_PHY_MR13_FSPWR_MASK 
#define DDR_PHY_MR13_FSPWR_DEFVAL                              0x00000000
#define DDR_PHY_MR13_FSPWR_SHIFT                               6
#define DDR_PHY_MR13_FSPWR_MASK                                0x00000040U

/*
* Data Mask Enable
*/
#undef DDR_PHY_MR13_DMD_DEFVAL 
#undef DDR_PHY_MR13_DMD_SHIFT 
#undef DDR_PHY_MR13_DMD_MASK 
#define DDR_PHY_MR13_DMD_DEFVAL                                0x00000000
#define DDR_PHY_MR13_DMD_SHIFT                                 5
#define DDR_PHY_MR13_DMD_MASK                                  0x00000020U

/*
* Refresh Rate Option
*/
#undef DDR_PHY_MR13_RRO_DEFVAL 
#undef DDR_PHY_MR13_RRO_SHIFT 
#undef DDR_PHY_MR13_RRO_MASK 
#define DDR_PHY_MR13_RRO_DEFVAL                                0x00000000
#define DDR_PHY_MR13_RRO_SHIFT                                 4
#define DDR_PHY_MR13_RRO_MASK                                  0x00000010U

/*
* VREF Current Generator
*/
#undef DDR_PHY_MR13_VRCG_DEFVAL 
#undef DDR_PHY_MR13_VRCG_SHIFT 
#undef DDR_PHY_MR13_VRCG_MASK 
#define DDR_PHY_MR13_VRCG_DEFVAL                               0x00000000
#define DDR_PHY_MR13_VRCG_SHIFT                                3
#define DDR_PHY_MR13_VRCG_MASK                                 0x00000008U

/*
* VREF Output
*/
#undef DDR_PHY_MR13_VRO_DEFVAL 
#undef DDR_PHY_MR13_VRO_SHIFT 
#undef DDR_PHY_MR13_VRO_MASK 
#define DDR_PHY_MR13_VRO_DEFVAL                                0x00000000
#define DDR_PHY_MR13_VRO_SHIFT                                 2
#define DDR_PHY_MR13_VRO_MASK                                  0x00000004U

/*
* Read Preamble Training Mode
*/
#undef DDR_PHY_MR13_RPT_DEFVAL 
#undef DDR_PHY_MR13_RPT_SHIFT 
#undef DDR_PHY_MR13_RPT_MASK 
#define DDR_PHY_MR13_RPT_DEFVAL                                0x00000000
#define DDR_PHY_MR13_RPT_SHIFT                                 1
#define DDR_PHY_MR13_RPT_MASK                                  0x00000002U

/*
* Command Bus Training
*/
#undef DDR_PHY_MR13_CBT_DEFVAL 
#undef DDR_PHY_MR13_CBT_SHIFT 
#undef DDR_PHY_MR13_CBT_MASK 
#define DDR_PHY_MR13_CBT_DEFVAL                                0x00000000
#define DDR_PHY_MR13_CBT_SHIFT                                 0
#define DDR_PHY_MR13_CBT_MASK                                  0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR14_RESERVED_31_8_MASK 
#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL                      0x0000004D
#define DDR_PHY_MR14_RESERVED_31_8_SHIFT                       8
#define DDR_PHY_MR14_RESERVED_31_8_MASK                        0xFFFFFF00U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR14_RSVD_DEFVAL 
#undef DDR_PHY_MR14_RSVD_SHIFT 
#undef DDR_PHY_MR14_RSVD_MASK 
#define DDR_PHY_MR14_RSVD_DEFVAL                               0x0000004D
#define DDR_PHY_MR14_RSVD_SHIFT                                7
#define DDR_PHY_MR14_RSVD_MASK                                 0x00000080U

/*
* VREFDQ Range Selects.
*/
#undef DDR_PHY_MR14_VR_DQ_DEFVAL 
#undef DDR_PHY_MR14_VR_DQ_SHIFT 
#undef DDR_PHY_MR14_VR_DQ_MASK 
#define DDR_PHY_MR14_VR_DQ_DEFVAL                              0x0000004D
#define DDR_PHY_MR14_VR_DQ_SHIFT                               6
#define DDR_PHY_MR14_VR_DQ_MASK                                0x00000040U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR14_VREF_DQ_DEFVAL 
#undef DDR_PHY_MR14_VREF_DQ_SHIFT 
#undef DDR_PHY_MR14_VREF_DQ_MASK 
#define DDR_PHY_MR14_VREF_DQ_DEFVAL                            0x0000004D
#define DDR_PHY_MR14_VREF_DQ_SHIFT                             0
#define DDR_PHY_MR14_VREF_DQ_MASK                              0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL 
#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT 
#undef DDR_PHY_MR22_RESERVED_31_8_MASK 
#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL                      0x00000000
#define DDR_PHY_MR22_RESERVED_31_8_SHIFT                       8
#define DDR_PHY_MR22_RESERVED_31_8_MASK                        0xFFFFFF00U

/*
* These are JEDEC reserved bits and are recommended by JEDEC to be program
    * med to 0x0.
*/
#undef DDR_PHY_MR22_RSVD_DEFVAL 
#undef DDR_PHY_MR22_RSVD_SHIFT 
#undef DDR_PHY_MR22_RSVD_MASK 
#define DDR_PHY_MR22_RSVD_DEFVAL                               0x00000000
#define DDR_PHY_MR22_RSVD_SHIFT                                6
#define DDR_PHY_MR22_RSVD_MASK                                 0x000000C0U

/*
* CA ODT termination disable.
*/
#undef DDR_PHY_MR22_ODTD_CA_DEFVAL 
#undef DDR_PHY_MR22_ODTD_CA_SHIFT 
#undef DDR_PHY_MR22_ODTD_CA_MASK 
#define DDR_PHY_MR22_ODTD_CA_DEFVAL                            0x00000000
#define DDR_PHY_MR22_ODTD_CA_SHIFT                             5
#define DDR_PHY_MR22_ODTD_CA_MASK                              0x00000020U

/*
* ODT CS override.
*/
#undef DDR_PHY_MR22_ODTE_CS_DEFVAL 
#undef DDR_PHY_MR22_ODTE_CS_SHIFT 
#undef DDR_PHY_MR22_ODTE_CS_MASK 
#define DDR_PHY_MR22_ODTE_CS_DEFVAL                            0x00000000
#define DDR_PHY_MR22_ODTE_CS_SHIFT                             4
#define DDR_PHY_MR22_ODTE_CS_MASK                              0x00000010U

/*
* ODT CK override.
*/
#undef DDR_PHY_MR22_ODTE_CK_DEFVAL 
#undef DDR_PHY_MR22_ODTE_CK_SHIFT 
#undef DDR_PHY_MR22_ODTE_CK_MASK 
#define DDR_PHY_MR22_ODTE_CK_DEFVAL                            0x00000000
#define DDR_PHY_MR22_ODTE_CK_SHIFT                             3
#define DDR_PHY_MR22_ODTE_CK_MASK                              0x00000008U

/*
* Controller ODT value for VOH calibration.
*/
#undef DDR_PHY_MR22_CODT_DEFVAL 
#undef DDR_PHY_MR22_CODT_SHIFT 
#undef DDR_PHY_MR22_CODT_MASK 
#define DDR_PHY_MR22_CODT_DEFVAL                               0x00000000
#define DDR_PHY_MR22_CODT_SHIFT                                0
#define DDR_PHY_MR22_CODT_MASK                                 0x00000007U

/*
* Refresh During Training
*/
#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL 
#undef DDR_PHY_DTCR0_RFSHDT_SHIFT 
#undef DDR_PHY_DTCR0_RFSHDT_MASK 
#define DDR_PHY_DTCR0_RFSHDT_DEFVAL                            0x800091C7
#define DDR_PHY_DTCR0_RFSHDT_SHIFT                             28
#define DDR_PHY_DTCR0_RFSHDT_MASK                              0xF0000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 
#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 
#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK 
#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL                    0x800091C7
#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT                     26
#define DDR_PHY_DTCR0_RESERVED_27_26_MASK                      0x0C000000U

/*
* Data Training Debug Rank Select
*/
#undef DDR_PHY_DTCR0_DTDRS_DEFVAL 
#undef DDR_PHY_DTCR0_DTDRS_SHIFT 
#undef DDR_PHY_DTCR0_DTDRS_MASK 
#define DDR_PHY_DTCR0_DTDRS_DEFVAL                             0x800091C7
#define DDR_PHY_DTCR0_DTDRS_SHIFT                              24
#define DDR_PHY_DTCR0_DTDRS_MASK                               0x03000000U

/*
* Data Training with Early/Extended Gate
*/
#undef DDR_PHY_DTCR0_DTEXG_DEFVAL 
#undef DDR_PHY_DTCR0_DTEXG_SHIFT 
#undef DDR_PHY_DTCR0_DTEXG_MASK 
#define DDR_PHY_DTCR0_DTEXG_DEFVAL                             0x800091C7
#define DDR_PHY_DTCR0_DTEXG_SHIFT                              23
#define DDR_PHY_DTCR0_DTEXG_MASK                               0x00800000U

/*
* Data Training Extended Write DQS
*/
#undef DDR_PHY_DTCR0_DTEXD_DEFVAL 
#undef DDR_PHY_DTCR0_DTEXD_SHIFT 
#undef DDR_PHY_DTCR0_DTEXD_MASK 
#define DDR_PHY_DTCR0_DTEXD_DEFVAL                             0x800091C7
#define DDR_PHY_DTCR0_DTEXD_SHIFT                              22
#define DDR_PHY_DTCR0_DTEXD_MASK                               0x00400000U

/*
* Data Training Debug Step
*/
#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL 
#undef DDR_PHY_DTCR0_DTDSTP_SHIFT 
#undef DDR_PHY_DTCR0_DTDSTP_MASK 
#define DDR_PHY_DTCR0_DTDSTP_DEFVAL                            0x800091C7
#define DDR_PHY_DTCR0_DTDSTP_SHIFT                             21
#define DDR_PHY_DTCR0_DTDSTP_MASK                              0x00200000U

/*
* Data Training Debug Enable
*/
#undef DDR_PHY_DTCR0_DTDEN_DEFVAL 
#undef DDR_PHY_DTCR0_DTDEN_SHIFT 
#undef DDR_PHY_DTCR0_DTDEN_MASK 
#define DDR_PHY_DTCR0_DTDEN_DEFVAL                             0x800091C7
#define DDR_PHY_DTCR0_DTDEN_SHIFT                              20
#define DDR_PHY_DTCR0_DTDEN_MASK                               0x00100000U

/*
* Data Training Debug Byte Select
*/
#undef DDR_PHY_DTCR0_DTDBS_DEFVAL 
#undef DDR_PHY_DTCR0_DTDBS_SHIFT 
#undef DDR_PHY_DTCR0_DTDBS_MASK 
#define DDR_PHY_DTCR0_DTDBS_DEFVAL                             0x800091C7
#define DDR_PHY_DTCR0_DTDBS_SHIFT                              16
#define DDR_PHY_DTCR0_DTDBS_MASK                               0x000F0000U

/*
* Data Training read DBI deskewing configuration
*/
#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL 
#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT 
#undef DDR_PHY_DTCR0_DTRDBITR_MASK 
#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL                          0x800091C7
#define DDR_PHY_DTCR0_DTRDBITR_SHIFT                           14
#define DDR_PHY_DTCR0_DTRDBITR_MASK                            0x0000C000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL 
#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT 
#undef DDR_PHY_DTCR0_RESERVED_13_MASK 
#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL                       0x800091C7
#define DDR_PHY_DTCR0_RESERVED_13_SHIFT                        13
#define DDR_PHY_DTCR0_RESERVED_13_MASK                         0x00002000U

/*
* Data Training Write Bit Deskew Data Mask
*/
#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL 
#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT 
#undef DDR_PHY_DTCR0_DTWBDDM_MASK 
#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL                           0x800091C7
#define DDR_PHY_DTCR0_DTWBDDM_SHIFT                            12
#define DDR_PHY_DTCR0_DTWBDDM_MASK                             0x00001000U

/*
* Refreshes Issued During Entry to Training
*/
#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL 
#undef DDR_PHY_DTCR0_RFSHEN_SHIFT 
#undef DDR_PHY_DTCR0_RFSHEN_MASK 
#define DDR_PHY_DTCR0_RFSHEN_DEFVAL                            0x800091C7
#define DDR_PHY_DTCR0_RFSHEN_SHIFT                             8
#define DDR_PHY_DTCR0_RFSHEN_MASK                              0x00000F00U

/*
* Data Training Compare Data
*/
#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL 
#undef DDR_PHY_DTCR0_DTCMPD_SHIFT 
#undef DDR_PHY_DTCR0_DTCMPD_MASK 
#define DDR_PHY_DTCR0_DTCMPD_DEFVAL                            0x800091C7
#define DDR_PHY_DTCR0_DTCMPD_SHIFT                             7
#define DDR_PHY_DTCR0_DTCMPD_MASK                              0x00000080U

/*
* Data Training Using MPR
*/
#undef DDR_PHY_DTCR0_DTMPR_DEFVAL 
#undef DDR_PHY_DTCR0_DTMPR_SHIFT 
#undef DDR_PHY_DTCR0_DTMPR_MASK 
#define DDR_PHY_DTCR0_DTMPR_DEFVAL                             0x800091C7
#define DDR_PHY_DTCR0_DTMPR_SHIFT                              6
#define DDR_PHY_DTCR0_DTMPR_MASK                               0x00000040U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 
#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 
#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK 
#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL                      0x800091C7
#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT                       4
#define DDR_PHY_DTCR0_RESERVED_5_4_MASK                        0x00000030U

/*
* Data Training Repeat Number
*/
#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL 
#undef DDR_PHY_DTCR0_DTRPTN_SHIFT 
#undef DDR_PHY_DTCR0_DTRPTN_MASK 
#define DDR_PHY_DTCR0_DTRPTN_DEFVAL                            0x800091C7
#define DDR_PHY_DTCR0_DTRPTN_SHIFT                             0
#define DDR_PHY_DTCR0_DTRPTN_MASK                              0x0000000FU

/*
* Rank Enable.
*/
#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 
#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 
#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK 
#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL                       0x00030237
#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT                        18
#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK                         0xFFFC0000U

/*
* Rank Enable.
*/
#undef DDR_PHY_DTCR1_RANKEN_DEFVAL 
#undef DDR_PHY_DTCR1_RANKEN_SHIFT 
#undef DDR_PHY_DTCR1_RANKEN_MASK 
#define DDR_PHY_DTCR1_RANKEN_DEFVAL                            0x00030237
#define DDR_PHY_DTCR1_RANKEN_SHIFT                             16
#define DDR_PHY_DTCR1_RANKEN_MASK                              0x00030000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK 
#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL                    0x00030237
#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT                     14
#define DDR_PHY_DTCR1_RESERVED_15_14_MASK                      0x0000C000U

/*
* Data Training Rank
*/
#undef DDR_PHY_DTCR1_DTRANK_DEFVAL 
#undef DDR_PHY_DTCR1_DTRANK_SHIFT 
#undef DDR_PHY_DTCR1_DTRANK_MASK 
#define DDR_PHY_DTCR1_DTRANK_DEFVAL                            0x00030237
#define DDR_PHY_DTCR1_DTRANK_SHIFT                             12
#define DDR_PHY_DTCR1_DTRANK_MASK                              0x00003000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL 
#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT 
#undef DDR_PHY_DTCR1_RESERVED_11_MASK 
#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL                       0x00030237
#define DDR_PHY_DTCR1_RESERVED_11_SHIFT                        11
#define DDR_PHY_DTCR1_RESERVED_11_MASK                         0x00000800U

/*
* Read Leveling Gate Sampling Difference
*/
#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 
#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 
#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK 
#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL                        0x00030237
#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT                         8
#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK                          0x00000700U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL 
#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT 
#undef DDR_PHY_DTCR1_RESERVED_7_MASK 
#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL                        0x00030237
#define DDR_PHY_DTCR1_RESERVED_7_SHIFT                         7
#define DDR_PHY_DTCR1_RESERVED_7_MASK                          0x00000080U

/*
* Read Leveling Gate Shift
*/
#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL 
#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT 
#undef DDR_PHY_DTCR1_RDLVLGS_MASK 
#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL                           0x00030237
#define DDR_PHY_DTCR1_RDLVLGS_SHIFT                            4
#define DDR_PHY_DTCR1_RDLVLGS_MASK                             0x00000070U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL 
#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT 
#undef DDR_PHY_DTCR1_RESERVED_3_MASK 
#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL                        0x00030237
#define DDR_PHY_DTCR1_RESERVED_3_SHIFT                         3
#define DDR_PHY_DTCR1_RESERVED_3_MASK                          0x00000008U

/*
* Read Preamble Training enable
*/
#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 
#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 
#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 
#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL                       0x00030237
#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT                        2
#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK                         0x00000004U

/*
* Read Leveling Enable
*/
#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL 
#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT 
#undef DDR_PHY_DTCR1_RDLVLEN_MASK 
#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL                           0x00030237
#define DDR_PHY_DTCR1_RDLVLEN_SHIFT                            1
#define DDR_PHY_DTCR1_RDLVLEN_MASK                             0x00000002U

/*
* Basic Gate Training Enable
*/
#undef DDR_PHY_DTCR1_BSTEN_DEFVAL 
#undef DDR_PHY_DTCR1_BSTEN_SHIFT 
#undef DDR_PHY_DTCR1_BSTEN_MASK 
#define DDR_PHY_DTCR1_BSTEN_DEFVAL                             0x00030237
#define DDR_PHY_DTCR1_BSTEN_SHIFT                              0
#define DDR_PHY_DTCR1_BSTEN_MASK                               0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 
#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT 
#undef DDR_PHY_CATR0_RESERVED_31_21_MASK 
#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL                    0x00141054
#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT                     21
#define DDR_PHY_CATR0_RESERVED_31_21_MASK                      0xFFE00000U

/*
* Minimum time (in terms of number of dram clocks) between two consectuve
    * CA calibration command
*/
#undef DDR_PHY_CATR0_CACD_DEFVAL 
#undef DDR_PHY_CATR0_CACD_SHIFT 
#undef DDR_PHY_CATR0_CACD_MASK 
#define DDR_PHY_CATR0_CACD_DEFVAL                              0x00141054
#define DDR_PHY_CATR0_CACD_SHIFT                               16
#define DDR_PHY_CATR0_CACD_MASK                                0x001F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 
#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT 
#undef DDR_PHY_CATR0_RESERVED_15_13_MASK 
#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL                    0x00141054
#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT                     13
#define DDR_PHY_CATR0_RESERVED_15_13_MASK                      0x0000E000U

/*
* Minimum time (in terms of number of dram clocks) PUB should wait before
    * sampling the CA response after Calibration command has been sent to the
    * memory
*/
#undef DDR_PHY_CATR0_CAADR_DEFVAL 
#undef DDR_PHY_CATR0_CAADR_SHIFT 
#undef DDR_PHY_CATR0_CAADR_MASK 
#define DDR_PHY_CATR0_CAADR_DEFVAL                             0x00141054
#define DDR_PHY_CATR0_CAADR_SHIFT                              8
#define DDR_PHY_CATR0_CAADR_MASK                               0x00001F00U

/*
* CA_1 Response Byte Lane 1
*/
#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL 
#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT 
#undef DDR_PHY_CATR0_CA1BYTE1_MASK 
#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL                          0x00141054
#define DDR_PHY_CATR0_CA1BYTE1_SHIFT                           4
#define DDR_PHY_CATR0_CA1BYTE1_MASK                            0x000000F0U

/*
* CA_1 Response Byte Lane 0
*/
#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL 
#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT 
#undef DDR_PHY_CATR0_CA1BYTE0_MASK 
#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL                          0x00141054
#define DDR_PHY_CATR0_CA1BYTE0_SHIFT                           0
#define DDR_PHY_CATR0_CA1BYTE0_MASK                            0x0000000FU

/*
* Number of delay taps by which the DQS gate LCDL will be updated when DQS
    *  drift is detected
*/
#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT 
#undef DDR_PHY_DQSDR0_DFTDLY_MASK 
#define DDR_PHY_DQSDR0_DFTDLY_DEFVAL                           0x00088000
#define DDR_PHY_DQSDR0_DFTDLY_SHIFT                            28
#define DDR_PHY_DQSDR0_DFTDLY_MASK                             0xF0000000U

/*
* Drift Impedance Update
*/
#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT 
#undef DDR_PHY_DQSDR0_DFTZQUP_MASK 
#define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL                          0x00088000
#define DDR_PHY_DQSDR0_DFTZQUP_SHIFT                           27
#define DDR_PHY_DQSDR0_DFTZQUP_MASK                            0x08000000U

/*
* Drift DDL Update
*/
#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 
#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK 
#define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL                         0x00088000
#define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT                          26
#define DDR_PHY_DQSDR0_DFTDDLUP_MASK                           0x04000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 
#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 
#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK 
#define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL                   0x00088000
#define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT                    22
#define DDR_PHY_DQSDR0_RESERVED_25_22_MASK                     0x03C00000U

/*
* Drift Read Spacing
*/
#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 
#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK 
#define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL                         0x00088000
#define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT                          20
#define DDR_PHY_DQSDR0_DFTRDSPC_MASK                           0x00300000U

/*
* Drift Back-to-Back Reads
*/
#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 
#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK 
#define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL                         0x00088000
#define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT                          16
#define DDR_PHY_DQSDR0_DFTB2BRD_MASK                           0x000F0000U

/*
* Drift Idle Reads
*/
#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 
#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK 
#define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL                         0x00088000
#define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT                          12
#define DDR_PHY_DQSDR0_DFTIDLRD_MASK                           0x0000F000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 
#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 
#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK 
#define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL                    0x00088000
#define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT                     8
#define DDR_PHY_DQSDR0_RESERVED_11_8_MASK                      0x00000F00U

/*
* Gate Pulse Enable
*/
#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 
#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK 
#define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL                        0x00088000
#define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT                         4
#define DDR_PHY_DQSDR0_DFTGPULSE_MASK                          0x000000F0U

/*
* DQS Drift Update Mode
*/
#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 
#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK 
#define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL                        0x00088000
#define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT                         2
#define DDR_PHY_DQSDR0_DFTUPMODE_MASK                          0x0000000CU

/*
* DQS Drift Detection Mode
*/
#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 
#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK 
#define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL                        0x00088000
#define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT                         1
#define DDR_PHY_DQSDR0_DFTDTMODE_MASK                          0x00000002U

/*
* DQS Drift Detection Enable
*/
#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 
#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT 
#undef DDR_PHY_DQSDR0_DFTDTEN_MASK 
#define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL                          0x00088000
#define DDR_PHY_DQSDR0_DFTDTEN_SHIFT                           0
#define DDR_PHY_DQSDR0_DFTDTEN_MASK                            0x00000001U

/*
* LFSR seed for pseudo-random BIST patterns
*/
#undef DDR_PHY_BISTLSR_SEED_DEFVAL 
#undef DDR_PHY_BISTLSR_SEED_SHIFT 
#undef DDR_PHY_BISTLSR_SEED_MASK 
#define DDR_PHY_BISTLSR_SEED_DEFVAL                            
#define DDR_PHY_BISTLSR_SEED_SHIFT                             0
#define DDR_PHY_BISTLSR_SEED_MASK                              0xFFFFFFFFU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 
#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 
#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK 
#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL                   0x00000005
#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT                    16
#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK                     0xFFFF0000U

/*
* Reserved. Return zeros on reads.
*/
#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 
#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 
#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 
#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL                   0x00000005
#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT                    4
#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK                     0x0000FFF0U

/*
* SDRAM On-die Termination Output Enable (OE) Mode Selection.
*/
#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 
#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 
#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK 
#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL                        0x00000005
#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT                         0
#define DDR_PHY_RIOCR5_ODTOEMODE_MASK                          0x0000000FU

/*
* Address/Command Slew Rate (D3F I/O Only)
*/
#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL 
#undef DDR_PHY_ACIOCR0_ACSR_SHIFT 
#undef DDR_PHY_ACIOCR0_ACSR_MASK 
#define DDR_PHY_ACIOCR0_ACSR_DEFVAL                            0x30000000
#define DDR_PHY_ACIOCR0_ACSR_SHIFT                             30
#define DDR_PHY_ACIOCR0_ACSR_MASK                              0xC0000000U

/*
* SDRAM Reset I/O Mode
*/
#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 
#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT 
#undef DDR_PHY_ACIOCR0_RSTIOM_MASK 
#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL                          0x30000000
#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT                           29
#define DDR_PHY_ACIOCR0_RSTIOM_MASK                            0x20000000U

/*
* SDRAM Reset Power Down Receiver
*/
#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 
#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT 
#undef DDR_PHY_ACIOCR0_RSTPDR_MASK 
#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL                          0x30000000
#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT                           28
#define DDR_PHY_ACIOCR0_RSTPDR_MASK                            0x10000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 
#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 
#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK 
#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL                     0x30000000
#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT                      27
#define DDR_PHY_ACIOCR0_RESERVED_27_MASK                       0x08000000U

/*
* SDRAM Reset On-Die Termination
*/
#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL 
#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT 
#undef DDR_PHY_ACIOCR0_RSTODT_MASK 
#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL                          0x30000000
#define DDR_PHY_ACIOCR0_RSTODT_SHIFT                           26
#define DDR_PHY_ACIOCR0_RSTODT_MASK                            0x04000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 
#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 
#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 
#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL                  0x30000000
#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT                   10
#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK                    0x03FFFC00U

/*
* CK Duty Cycle Correction
*/
#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL 
#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT 
#undef DDR_PHY_ACIOCR0_CKDCC_MASK 
#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL                           0x30000000
#define DDR_PHY_ACIOCR0_CKDCC_SHIFT                            6
#define DDR_PHY_ACIOCR0_CKDCC_MASK                             0x000003C0U

/*
* AC Power Down Receiver Mode
*/
#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 
#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 
#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK 
#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL                       0x30000000
#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT                        4
#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK                         0x00000030U

/*
* AC On-die Termination Mode
*/
#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 
#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 
#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK 
#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL                       0x30000000
#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT                        2
#define DDR_PHY_ACIOCR0_ACODTMODE_MASK                         0x0000000CU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 
#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 
#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK 
#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL                      0x30000000
#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT                       1
#define DDR_PHY_ACIOCR0_RESERVED_1_MASK                        0x00000002U

/*
* Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
*/
#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 
#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 
#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 
#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL                    0x30000000
#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT                     0
#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK                      0x00000001U

/*
* Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL
    * slice
*/
#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 
#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 
#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 
#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL                   0x00000000
#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT                    31
#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK                     0x80000000U

/*
* Clock gating for Output Enable D slices [0]
*/
#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 
#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 
#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 
#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL                    0x00000000
#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT                     30
#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK                      0x40000000U

/*
* Clock gating for Power Down Receiver D slices [0]
*/
#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 
#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 
#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 
#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL                   0x00000000
#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT                    29
#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK                     0x20000000U

/*
* Clock gating for Termination Enable D slices [0]
*/
#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 
#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 
#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 
#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL                    0x00000000
#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT                     28
#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK                      0x10000000U

/*
* Clock gating for CK# D slices [1:0]
*/
#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 
#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 
#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 
#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL                     0x00000000
#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT                      26
#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK                       0x0C000000U

/*
* Clock gating for CK D slices [1:0]
*/
#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 
#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 
#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 
#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL                      0x00000000
#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT                       24
#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK                        0x03000000U

/*
* Clock gating for AC D slices [23:0]
*/
#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 
#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 
#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 
#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL                      0x00000000
#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT                       0
#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK                        0x00FFFFFFU

/*
* SDRAM Parity Output Enable (OE) Mode Selection
*/
#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 
#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 
#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK 
#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL                       0x00000005
#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT                        30
#define DDR_PHY_ACIOCR3_PAROEMODE_MASK                         0xC0000000U

/*
* SDRAM Bank Group Output Enable (OE) Mode Selection
*/
#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 
#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 
#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK 
#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL                        0x00000005
#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT                         26
#define DDR_PHY_ACIOCR3_BGOEMODE_MASK                          0x3C000000U

/*
* SDRAM Bank Address Output Enable (OE) Mode Selection
*/
#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 
#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 
#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK 
#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL                        0x00000005
#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT                         22
#define DDR_PHY_ACIOCR3_BAOEMODE_MASK                          0x03C00000U

/*
* SDRAM A[17] Output Enable (OE) Mode Selection
*/
#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 
#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 
#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK 
#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL                       0x00000005
#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT                        20
#define DDR_PHY_ACIOCR3_A17OEMODE_MASK                         0x00300000U

/*
* SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
*/
#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 
#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 
#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK 
#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL                       0x00000005
#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT                        18
#define DDR_PHY_ACIOCR3_A16OEMODE_MASK                         0x000C0000U

/*
* SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
*/
#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 
#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 
#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK 
#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL                       0x00000005
#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT                        16
#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK                         0x00030000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 
#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 
#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 
#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL                   0x00000005
#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT                    8
#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK                     0x0000FF00U

/*
* Reserved. Return zeros on reads.
*/
#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 
#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 
#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 
#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL                   0x00000005
#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT                    4
#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK                     0x000000F0U

/*
* SDRAM CK Output Enable (OE) Mode Selection.
*/
#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 
#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 
#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK 
#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL                        0x00000005
#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT                         0
#define DDR_PHY_ACIOCR3_CKOEMODE_MASK                          0x0000000FU

/*
* Clock gating for AC LB slices and loopback read valid slices
*/
#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 
#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 
#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK 
#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL                       0x00000000
#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT                        31
#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK                         0x80000000U

/*
* Clock gating for Output Enable D slices [1]
*/
#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 
#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 
#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 
#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL                    0x00000000
#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT                     30
#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK                      0x40000000U

/*
* Clock gating for Power Down Receiver D slices [1]
*/
#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 
#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 
#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 
#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL                   0x00000000
#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT                    29
#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK                     0x20000000U

/*
* Clock gating for Termination Enable D slices [1]
*/
#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 
#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 
#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 
#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL                    0x00000000
#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT                     28
#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK                      0x10000000U

/*
* Clock gating for CK# D slices [3:2]
*/
#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 
#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 
#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 
#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL                     0x00000000
#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT                      26
#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK                       0x0C000000U

/*
* Clock gating for CK D slices [3:2]
*/
#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 
#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 
#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 
#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL                      0x00000000
#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT                       24
#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK                        0x03000000U

/*
* Clock gating for AC D slices [47:24]
*/
#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 
#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 
#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 
#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL                      0x00000000
#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT                       0
#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK                        0x00FFFFFFU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 
#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK 
#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL                   0x0F000000
#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT                    29
#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK                     0xE0000000U

/*
* Address/command lane VREF Pad Enable
*/
#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 
#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT 
#undef DDR_PHY_IOVCR0_ACREFPEN_MASK 
#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL                         0x0F000000
#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT                          28
#define DDR_PHY_IOVCR0_ACREFPEN_MASK                           0x10000000U

/*
* Address/command lane Internal VREF Enable
*/
#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 
#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT 
#undef DDR_PHY_IOVCR0_ACREFEEN_MASK 
#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL                         0x0F000000
#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT                          26
#define DDR_PHY_IOVCR0_ACREFEEN_MASK                           0x0C000000U

/*
* Address/command lane Single-End VREF Enable
*/
#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 
#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT 
#undef DDR_PHY_IOVCR0_ACREFSEN_MASK 
#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL                         0x0F000000
#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT                          25
#define DDR_PHY_IOVCR0_ACREFSEN_MASK                           0x02000000U

/*
* Address/command lane Internal VREF Enable
*/
#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 
#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT 
#undef DDR_PHY_IOVCR0_ACREFIEN_MASK 
#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL                         0x0F000000
#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT                          24
#define DDR_PHY_IOVCR0_ACREFIEN_MASK                           0x01000000U

/*
* External VREF generato REFSEL range select
*/
#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 
#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 
#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 
#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL                   0x0F000000
#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT                    23
#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK                     0x00800000U

/*
* Address/command lane External VREF Select
*/
#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 
#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT 
#undef DDR_PHY_IOVCR0_ACREFESEL_MASK 
#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL                        0x0F000000
#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT                         16
#define DDR_PHY_IOVCR0_ACREFESEL_MASK                          0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 
#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 
#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 
#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL                   0x0F000000
#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT                    15
#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK                     0x00008000U

/*
* Address/command lane Single-End VREF Select
*/
#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 
#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 
#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK 
#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL                        0x0F000000
#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT                         8
#define DDR_PHY_IOVCR0_ACREFSSEL_MASK                          0x00007F00U

/*
* Internal VREF generator REFSEL ragne select
*/
#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 
#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 
#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 
#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL                  0x0F000000
#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT                   7
#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK                    0x00000080U

/*
* REFSEL Control for internal AC IOs
*/
#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 
#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 
#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK 
#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL                       0x0F000000
#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT                        0
#define DDR_PHY_IOVCR0_ACVREFISEL_MASK                         0x0000007FU

/*
* Number of ctl_clk required to meet (> 150ns) timing requirements during
    * DRAM DQ VREF training
*/
#undef DDR_PHY_VTCR0_TVREF_DEFVAL 
#undef DDR_PHY_VTCR0_TVREF_SHIFT 
#undef DDR_PHY_VTCR0_TVREF_MASK 
#define DDR_PHY_VTCR0_TVREF_DEFVAL                             0x70032019
#define DDR_PHY_VTCR0_TVREF_SHIFT                              29
#define DDR_PHY_VTCR0_TVREF_MASK                               0xE0000000U

/*
* DRM DQ VREF training Enable
*/
#undef DDR_PHY_VTCR0_DVEN_DEFVAL 
#undef DDR_PHY_VTCR0_DVEN_SHIFT 
#undef DDR_PHY_VTCR0_DVEN_MASK 
#define DDR_PHY_VTCR0_DVEN_DEFVAL                              0x70032019
#define DDR_PHY_VTCR0_DVEN_SHIFT                               28
#define DDR_PHY_VTCR0_DVEN_MASK                                0x10000000U

/*
* Per Device Addressability Enable
*/
#undef DDR_PHY_VTCR0_PDAEN_DEFVAL 
#undef DDR_PHY_VTCR0_PDAEN_SHIFT 
#undef DDR_PHY_VTCR0_PDAEN_MASK 
#define DDR_PHY_VTCR0_PDAEN_DEFVAL                             0x70032019
#define DDR_PHY_VTCR0_PDAEN_SHIFT                              27
#define DDR_PHY_VTCR0_PDAEN_MASK                               0x08000000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL 
#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT 
#undef DDR_PHY_VTCR0_RESERVED_26_MASK 
#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL                       0x70032019
#define DDR_PHY_VTCR0_RESERVED_26_SHIFT                        26
#define DDR_PHY_VTCR0_RESERVED_26_MASK                         0x04000000U

/*
* VREF Word Count
*/
#undef DDR_PHY_VTCR0_VWCR_DEFVAL 
#undef DDR_PHY_VTCR0_VWCR_SHIFT 
#undef DDR_PHY_VTCR0_VWCR_MASK 
#define DDR_PHY_VTCR0_VWCR_DEFVAL                              0x70032019
#define DDR_PHY_VTCR0_VWCR_SHIFT                               22
#define DDR_PHY_VTCR0_VWCR_MASK                                0x03C00000U

/*
* DRAM DQ VREF step size used during DRAM VREF training
*/
#undef DDR_PHY_VTCR0_DVSS_DEFVAL 
#undef DDR_PHY_VTCR0_DVSS_SHIFT 
#undef DDR_PHY_VTCR0_DVSS_MASK 
#define DDR_PHY_VTCR0_DVSS_DEFVAL                              0x70032019
#define DDR_PHY_VTCR0_DVSS_SHIFT                               18
#define DDR_PHY_VTCR0_DVSS_MASK                                0x003C0000U

/*
* Maximum VREF limit value used during DRAM VREF training
*/
#undef DDR_PHY_VTCR0_DVMAX_DEFVAL 
#undef DDR_PHY_VTCR0_DVMAX_SHIFT 
#undef DDR_PHY_VTCR0_DVMAX_MASK 
#define DDR_PHY_VTCR0_DVMAX_DEFVAL                             0x70032019
#define DDR_PHY_VTCR0_DVMAX_SHIFT                              12
#define DDR_PHY_VTCR0_DVMAX_MASK                               0x0003F000U

/*
* Minimum VREF limit value used during DRAM VREF training
*/
#undef DDR_PHY_VTCR0_DVMIN_DEFVAL 
#undef DDR_PHY_VTCR0_DVMIN_SHIFT 
#undef DDR_PHY_VTCR0_DVMIN_MASK 
#define DDR_PHY_VTCR0_DVMIN_DEFVAL                             0x70032019
#define DDR_PHY_VTCR0_DVMIN_SHIFT                              6
#define DDR_PHY_VTCR0_DVMIN_MASK                               0x00000FC0U

/*
* Initial DRAM DQ VREF value used during DRAM VREF training
*/
#undef DDR_PHY_VTCR0_DVINIT_DEFVAL 
#undef DDR_PHY_VTCR0_DVINIT_SHIFT 
#undef DDR_PHY_VTCR0_DVINIT_MASK 
#define DDR_PHY_VTCR0_DVINIT_DEFVAL                            0x70032019
#define DDR_PHY_VTCR0_DVINIT_SHIFT                             0
#define DDR_PHY_VTCR0_DVINIT_MASK                              0x0000003FU

/*
* Host VREF step size used during VREF training. The register value of N i
    * ndicates step size of (N+1)
*/
#undef DDR_PHY_VTCR1_HVSS_DEFVAL 
#undef DDR_PHY_VTCR1_HVSS_SHIFT 
#undef DDR_PHY_VTCR1_HVSS_MASK 
#define DDR_PHY_VTCR1_HVSS_DEFVAL                              0x07F00072
#define DDR_PHY_VTCR1_HVSS_SHIFT                               28
#define DDR_PHY_VTCR1_HVSS_MASK                                0xF0000000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL 
#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT 
#undef DDR_PHY_VTCR1_RESERVED_27_MASK 
#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL                       0x07F00072
#define DDR_PHY_VTCR1_RESERVED_27_SHIFT                        27
#define DDR_PHY_VTCR1_RESERVED_27_MASK                         0x08000000U

/*
* Maximum VREF limit value used during DRAM VREF training.
*/
#undef DDR_PHY_VTCR1_HVMAX_DEFVAL 
#undef DDR_PHY_VTCR1_HVMAX_SHIFT 
#undef DDR_PHY_VTCR1_HVMAX_MASK 
#define DDR_PHY_VTCR1_HVMAX_DEFVAL                             0x07F00072
#define DDR_PHY_VTCR1_HVMAX_SHIFT                              20
#define DDR_PHY_VTCR1_HVMAX_MASK                               0x07F00000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL 
#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT 
#undef DDR_PHY_VTCR1_RESERVED_19_MASK 
#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL                       0x07F00072
#define DDR_PHY_VTCR1_RESERVED_19_SHIFT                        19
#define DDR_PHY_VTCR1_RESERVED_19_MASK                         0x00080000U

/*
* Minimum VREF limit value used during DRAM VREF training.
*/
#undef DDR_PHY_VTCR1_HVMIN_DEFVAL 
#undef DDR_PHY_VTCR1_HVMIN_SHIFT 
#undef DDR_PHY_VTCR1_HVMIN_MASK 
#define DDR_PHY_VTCR1_HVMIN_DEFVAL                             0x07F00072
#define DDR_PHY_VTCR1_HVMIN_SHIFT                              12
#define DDR_PHY_VTCR1_HVMIN_MASK                               0x0007F000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL 
#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT 
#undef DDR_PHY_VTCR1_RESERVED_11_MASK 
#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL                       0x07F00072
#define DDR_PHY_VTCR1_RESERVED_11_SHIFT                        11
#define DDR_PHY_VTCR1_RESERVED_11_MASK                         0x00000800U

/*
* Static Host Vref Rank Value
*/
#undef DDR_PHY_VTCR1_SHRNK_DEFVAL 
#undef DDR_PHY_VTCR1_SHRNK_SHIFT 
#undef DDR_PHY_VTCR1_SHRNK_MASK 
#define DDR_PHY_VTCR1_SHRNK_DEFVAL                             0x07F00072
#define DDR_PHY_VTCR1_SHRNK_SHIFT                              9
#define DDR_PHY_VTCR1_SHRNK_MASK                               0x00000600U

/*
* Static Host Vref Rank Enable
*/
#undef DDR_PHY_VTCR1_SHREN_DEFVAL 
#undef DDR_PHY_VTCR1_SHREN_SHIFT 
#undef DDR_PHY_VTCR1_SHREN_MASK 
#define DDR_PHY_VTCR1_SHREN_DEFVAL                             0x07F00072
#define DDR_PHY_VTCR1_SHREN_SHIFT                              8
#define DDR_PHY_VTCR1_SHREN_MASK                               0x00000100U

/*
* Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir
    * ements during Host IO VREF training
*/
#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL 
#undef DDR_PHY_VTCR1_TVREFIO_SHIFT 
#undef DDR_PHY_VTCR1_TVREFIO_MASK 
#define DDR_PHY_VTCR1_TVREFIO_DEFVAL                           0x07F00072
#define DDR_PHY_VTCR1_TVREFIO_SHIFT                            5
#define DDR_PHY_VTCR1_TVREFIO_MASK                             0x000000E0U

/*
* Eye LCDL Offset value for VREF training
*/
#undef DDR_PHY_VTCR1_EOFF_DEFVAL 
#undef DDR_PHY_VTCR1_EOFF_SHIFT 
#undef DDR_PHY_VTCR1_EOFF_MASK 
#define DDR_PHY_VTCR1_EOFF_DEFVAL                              0x07F00072
#define DDR_PHY_VTCR1_EOFF_SHIFT                               3
#define DDR_PHY_VTCR1_EOFF_MASK                                0x00000018U

/*
* Number of LCDL Eye points for which VREF training is repeated
*/
#undef DDR_PHY_VTCR1_ENUM_DEFVAL 
#undef DDR_PHY_VTCR1_ENUM_SHIFT 
#undef DDR_PHY_VTCR1_ENUM_MASK 
#define DDR_PHY_VTCR1_ENUM_DEFVAL                              0x07F00072
#define DDR_PHY_VTCR1_ENUM_SHIFT                               2
#define DDR_PHY_VTCR1_ENUM_MASK                                0x00000004U

/*
* HOST (IO) internal VREF training Enable
*/
#undef DDR_PHY_VTCR1_HVEN_DEFVAL 
#undef DDR_PHY_VTCR1_HVEN_SHIFT 
#undef DDR_PHY_VTCR1_HVEN_MASK 
#define DDR_PHY_VTCR1_HVEN_DEFVAL                              0x07F00072
#define DDR_PHY_VTCR1_HVEN_SHIFT                               1
#define DDR_PHY_VTCR1_HVEN_MASK                                0x00000002U

/*
* Host IO Type Control
*/
#undef DDR_PHY_VTCR1_HVIO_DEFVAL 
#undef DDR_PHY_VTCR1_HVIO_SHIFT 
#undef DDR_PHY_VTCR1_HVIO_MASK 
#define DDR_PHY_VTCR1_HVIO_DEFVAL                              0x07F00072
#define DDR_PHY_VTCR1_HVIO_SHIFT                               0
#define DDR_PHY_VTCR1_HVIO_MASK                                0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 
#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 
#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK                    0xC0000000U

/*
* Delay select for the BDL on Parity.
*/
#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL 
#undef DDR_PHY_ACBDLR1_PARBD_SHIFT 
#undef DDR_PHY_ACBDLR1_PARBD_MASK 
#define DDR_PHY_ACBDLR1_PARBD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR1_PARBD_SHIFT                            24
#define DDR_PHY_ACBDLR1_PARBD_MASK                             0x3F000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 
#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 
#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK                    0x00C00000U

/*
* Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn
    * ected to WE.
*/
#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL 
#undef DDR_PHY_ACBDLR1_A16BD_SHIFT 
#undef DDR_PHY_ACBDLR1_A16BD_MASK 
#define DDR_PHY_ACBDLR1_A16BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR1_A16BD_SHIFT                            16
#define DDR_PHY_ACBDLR1_A16BD_MASK                             0x003F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 
#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 
#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK                    0x0000C000U

/*
* Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi
    * s pin is connected to CAS.
*/
#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL 
#undef DDR_PHY_ACBDLR1_A17BD_SHIFT 
#undef DDR_PHY_ACBDLR1_A17BD_MASK 
#define DDR_PHY_ACBDLR1_A17BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR1_A17BD_SHIFT                            8
#define DDR_PHY_ACBDLR1_A17BD_MASK                             0x00003F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 
#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 
#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL                    0x00000000
#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK                      0x000000C0U

/*
* Delay select for the BDL on ACTN.
*/
#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL 
#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT 
#undef DDR_PHY_ACBDLR1_ACTBD_MASK 
#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR1_ACTBD_SHIFT                            0
#define DDR_PHY_ACBDLR1_ACTBD_MASK                             0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 
#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 
#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK                    0xC0000000U

/*
* Delay select for the BDL on BG[1].
*/
#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL 
#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT 
#undef DDR_PHY_ACBDLR2_BG1BD_MASK 
#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR2_BG1BD_SHIFT                            24
#define DDR_PHY_ACBDLR2_BG1BD_MASK                             0x3F000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 
#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 
#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK                    0x00C00000U

/*
* Delay select for the BDL on BG[0].
*/
#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL 
#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT 
#undef DDR_PHY_ACBDLR2_BG0BD_MASK 
#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR2_BG0BD_SHIFT                            16
#define DDR_PHY_ACBDLR2_BG0BD_MASK                             0x003F0000U

/*
* Reser.ved Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 
#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 
#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK                    0x0000C000U

/*
* Delay select for the BDL on BA[1].
*/
#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL 
#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT 
#undef DDR_PHY_ACBDLR2_BA1BD_MASK 
#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR2_BA1BD_SHIFT                            8
#define DDR_PHY_ACBDLR2_BA1BD_MASK                             0x00003F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 
#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 
#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL                    0x00000000
#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK                      0x000000C0U

/*
* Delay select for the BDL on BA[0].
*/
#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL 
#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT 
#undef DDR_PHY_ACBDLR2_BA0BD_MASK 
#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR2_BA0BD_SHIFT                            0
#define DDR_PHY_ACBDLR2_BA0BD_MASK                             0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 
#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* Delay select for the BDL on Address A[3].
*/
#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL 
#undef DDR_PHY_ACBDLR6_A03BD_SHIFT 
#undef DDR_PHY_ACBDLR6_A03BD_MASK 
#define DDR_PHY_ACBDLR6_A03BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR6_A03BD_SHIFT                            24
#define DDR_PHY_ACBDLR6_A03BD_MASK                             0x3F000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 
#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* Delay select for the BDL on Address A[2].
*/
#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL 
#undef DDR_PHY_ACBDLR6_A02BD_SHIFT 
#undef DDR_PHY_ACBDLR6_A02BD_MASK 
#define DDR_PHY_ACBDLR6_A02BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR6_A02BD_SHIFT                            16
#define DDR_PHY_ACBDLR6_A02BD_MASK                             0x003F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 
#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* Delay select for the BDL on Address A[1].
*/
#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL 
#undef DDR_PHY_ACBDLR6_A01BD_SHIFT 
#undef DDR_PHY_ACBDLR6_A01BD_MASK 
#define DDR_PHY_ACBDLR6_A01BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR6_A01BD_SHIFT                            8
#define DDR_PHY_ACBDLR6_A01BD_MASK                             0x00003F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 
#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL                    0x00000000
#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* Delay select for the BDL on Address A[0].
*/
#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL 
#undef DDR_PHY_ACBDLR6_A00BD_SHIFT 
#undef DDR_PHY_ACBDLR6_A00BD_MASK 
#define DDR_PHY_ACBDLR6_A00BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR6_A00BD_SHIFT                            0
#define DDR_PHY_ACBDLR6_A00BD_MASK                             0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 
#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 
#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK                    0xC0000000U

/*
* Delay select for the BDL on Address A[7].
*/
#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL 
#undef DDR_PHY_ACBDLR7_A07BD_SHIFT 
#undef DDR_PHY_ACBDLR7_A07BD_MASK 
#define DDR_PHY_ACBDLR7_A07BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR7_A07BD_SHIFT                            24
#define DDR_PHY_ACBDLR7_A07BD_MASK                             0x3F000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 
#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 
#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK                    0x00C00000U

/*
* Delay select for the BDL on Address A[6].
*/
#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL 
#undef DDR_PHY_ACBDLR7_A06BD_SHIFT 
#undef DDR_PHY_ACBDLR7_A06BD_MASK 
#define DDR_PHY_ACBDLR7_A06BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR7_A06BD_SHIFT                            16
#define DDR_PHY_ACBDLR7_A06BD_MASK                             0x003F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 
#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 
#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK                    0x0000C000U

/*
* Delay select for the BDL on Address A[5].
*/
#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL 
#undef DDR_PHY_ACBDLR7_A05BD_SHIFT 
#undef DDR_PHY_ACBDLR7_A05BD_MASK 
#define DDR_PHY_ACBDLR7_A05BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR7_A05BD_SHIFT                            8
#define DDR_PHY_ACBDLR7_A05BD_MASK                             0x00003F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 
#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 
#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL                    0x00000000
#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK                      0x000000C0U

/*
* Delay select for the BDL on Address A[4].
*/
#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL 
#undef DDR_PHY_ACBDLR7_A04BD_SHIFT 
#undef DDR_PHY_ACBDLR7_A04BD_MASK 
#define DDR_PHY_ACBDLR7_A04BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR7_A04BD_SHIFT                            0
#define DDR_PHY_ACBDLR7_A04BD_MASK                             0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 
#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 
#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK                    0xC0000000U

/*
* Delay select for the BDL on Address A[11].
*/
#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL 
#undef DDR_PHY_ACBDLR8_A11BD_SHIFT 
#undef DDR_PHY_ACBDLR8_A11BD_MASK 
#define DDR_PHY_ACBDLR8_A11BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR8_A11BD_SHIFT                            24
#define DDR_PHY_ACBDLR8_A11BD_MASK                             0x3F000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 
#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 
#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK                    0x00C00000U

/*
* Delay select for the BDL on Address A[10].
*/
#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL 
#undef DDR_PHY_ACBDLR8_A10BD_SHIFT 
#undef DDR_PHY_ACBDLR8_A10BD_MASK 
#define DDR_PHY_ACBDLR8_A10BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR8_A10BD_SHIFT                            16
#define DDR_PHY_ACBDLR8_A10BD_MASK                             0x003F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 
#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 
#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK                    0x0000C000U

/*
* Delay select for the BDL on Address A[9].
*/
#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL 
#undef DDR_PHY_ACBDLR8_A09BD_SHIFT 
#undef DDR_PHY_ACBDLR8_A09BD_MASK 
#define DDR_PHY_ACBDLR8_A09BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR8_A09BD_SHIFT                            8
#define DDR_PHY_ACBDLR8_A09BD_MASK                             0x00003F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 
#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 
#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL                    0x00000000
#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK                      0x000000C0U

/*
* Delay select for the BDL on Address A[8].
*/
#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL 
#undef DDR_PHY_ACBDLR8_A08BD_SHIFT 
#undef DDR_PHY_ACBDLR8_A08BD_MASK 
#define DDR_PHY_ACBDLR8_A08BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR8_A08BD_SHIFT                            0
#define DDR_PHY_ACBDLR8_A08BD_MASK                             0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 
#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 
#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK                    0xC0000000U

/*
* Delay select for the BDL on Address A[15].
*/
#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL 
#undef DDR_PHY_ACBDLR9_A15BD_SHIFT 
#undef DDR_PHY_ACBDLR9_A15BD_MASK 
#define DDR_PHY_ACBDLR9_A15BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR9_A15BD_SHIFT                            24
#define DDR_PHY_ACBDLR9_A15BD_MASK                             0x3F000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 
#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 
#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK                    0x00C00000U

/*
* Delay select for the BDL on Address A[14].
*/
#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL 
#undef DDR_PHY_ACBDLR9_A14BD_SHIFT 
#undef DDR_PHY_ACBDLR9_A14BD_MASK 
#define DDR_PHY_ACBDLR9_A14BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR9_A14BD_SHIFT                            16
#define DDR_PHY_ACBDLR9_A14BD_MASK                             0x003F0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 
#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 
#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL                  0x00000000
#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK                    0x0000C000U

/*
* Delay select for the BDL on Address A[13].
*/
#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL 
#undef DDR_PHY_ACBDLR9_A13BD_SHIFT 
#undef DDR_PHY_ACBDLR9_A13BD_MASK 
#define DDR_PHY_ACBDLR9_A13BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR9_A13BD_SHIFT                            8
#define DDR_PHY_ACBDLR9_A13BD_MASK                             0x00003F00U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 
#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 
#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL                    0x00000000
#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK                      0x000000C0U

/*
* Delay select for the BDL on Address A[12].
*/
#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL 
#undef DDR_PHY_ACBDLR9_A12BD_SHIFT 
#undef DDR_PHY_ACBDLR9_A12BD_MASK 
#define DDR_PHY_ACBDLR9_A12BD_DEFVAL                           0x00000000
#define DDR_PHY_ACBDLR9_A12BD_SHIFT                            0
#define DDR_PHY_ACBDLR9_A12BD_MASK                             0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 
#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 
#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK 
#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL                     0x008A2858
#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT                      26
#define DDR_PHY_ZQCR_RESERVED_31_26_MASK                       0xFC000000U

/*
* ZQ VREF Range
*/
#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 
#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 
#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 
#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL                     0x008A2858
#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT                      25
#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK                       0x02000000U

/*
* Programmable Wait for Frequency B
*/
#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 
#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 
#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 
#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL                        0x008A2858
#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT                         19
#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK                          0x01F80000U

/*
* Programmable Wait for Frequency A
*/
#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 
#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 
#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 
#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL                        0x008A2858
#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT                         13
#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK                          0x0007E000U

/*
* ZQ VREF Pad Enable
*/
#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 
#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT 
#undef DDR_PHY_ZQCR_ZQREFPEN_MASK 
#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL                           0x008A2858
#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT                            12
#define DDR_PHY_ZQCR_ZQREFPEN_MASK                             0x00001000U

/*
* ZQ Internal VREF Enable
*/
#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 
#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT 
#undef DDR_PHY_ZQCR_ZQREFIEN_MASK 
#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL                           0x008A2858
#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT                            11
#define DDR_PHY_ZQCR_ZQREFIEN_MASK                             0x00000800U

/*
* Choice of termination mode
*/
#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL 
#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT 
#undef DDR_PHY_ZQCR_ODT_MODE_MASK 
#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL                           0x008A2858
#define DDR_PHY_ZQCR_ODT_MODE_SHIFT                            9
#define DDR_PHY_ZQCR_ODT_MODE_MASK                             0x00000600U

/*
* Force ZCAL VT update
*/
#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 
#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 
#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 
#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL               0x008A2858
#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT                8
#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK                 0x00000100U

/*
* IO VT Drift Limit
*/
#undef DDR_PHY_ZQCR_IODLMT_DEFVAL 
#undef DDR_PHY_ZQCR_IODLMT_SHIFT 
#undef DDR_PHY_ZQCR_IODLMT_MASK 
#define DDR_PHY_ZQCR_IODLMT_DEFVAL                             0x008A2858
#define DDR_PHY_ZQCR_IODLMT_SHIFT                              5
#define DDR_PHY_ZQCR_IODLMT_MASK                               0x000000E0U

/*
* Averaging algorithm enable, if set, enables averaging algorithm
*/
#undef DDR_PHY_ZQCR_AVGEN_DEFVAL 
#undef DDR_PHY_ZQCR_AVGEN_SHIFT 
#undef DDR_PHY_ZQCR_AVGEN_MASK 
#define DDR_PHY_ZQCR_AVGEN_DEFVAL                              0x008A2858
#define DDR_PHY_ZQCR_AVGEN_SHIFT                               4
#define DDR_PHY_ZQCR_AVGEN_MASK                                0x00000010U

/*
* Maximum number of averaging rounds to be used by averaging algorithm
*/
#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL 
#undef DDR_PHY_ZQCR_AVGMAX_SHIFT 
#undef DDR_PHY_ZQCR_AVGMAX_MASK 
#define DDR_PHY_ZQCR_AVGMAX_DEFVAL                             0x008A2858
#define DDR_PHY_ZQCR_AVGMAX_SHIFT                              2
#define DDR_PHY_ZQCR_AVGMAX_MASK                               0x0000000CU

/*
* ZQ Calibration Type
*/
#undef DDR_PHY_ZQCR_ZCALT_DEFVAL 
#undef DDR_PHY_ZQCR_ZCALT_SHIFT 
#undef DDR_PHY_ZQCR_ZCALT_MASK 
#define DDR_PHY_ZQCR_ZCALT_DEFVAL                              0x008A2858
#define DDR_PHY_ZQCR_ZCALT_SHIFT                               1
#define DDR_PHY_ZQCR_ZCALT_MASK                                0x00000002U

/*
* ZQ Power Down
*/
#undef DDR_PHY_ZQCR_ZQPD_DEFVAL 
#undef DDR_PHY_ZQCR_ZQPD_SHIFT 
#undef DDR_PHY_ZQCR_ZQPD_MASK 
#define DDR_PHY_ZQCR_ZQPD_DEFVAL                               0x008A2858
#define DDR_PHY_ZQCR_ZQPD_SHIFT                                0
#define DDR_PHY_ZQCR_ZQPD_MASK                                 0x00000001U

/*
* Pull-down drive strength ZCTRL over-ride enable
*/
#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 
#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 
#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 
#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL                      0x000077BB
#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT                       31
#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK                        0x80000000U

/*
* Pull-up drive strength ZCTRL over-ride enable
*/
#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 
#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 
#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 
#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL                      0x000077BB
#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT                       30
#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK                        0x40000000U

/*
* Pull-down termination ZCTRL over-ride enable
*/
#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 
#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 
#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 
#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL                      0x000077BB
#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT                       29
#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK                        0x20000000U

/*
* Pull-up termination ZCTRL over-ride enable
*/
#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 
#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 
#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 
#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL                      0x000077BB
#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT                       28
#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK                        0x10000000U

/*
* Calibration segment bypass
*/
#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 
#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 
#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 
#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL                          0x000077BB
#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT                           27
#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK                            0x08000000U

/*
* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
    *  is driven by the PUB
*/
#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 
#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 
#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 
#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL                         0x000077BB
#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT                          25
#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK                           0x06000000U

/*
* Termination adjustment
*/
#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 
#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 
#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 
#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL                       0x000077BB
#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT                        22
#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK                         0x01C00000U

/*
* Pulldown drive strength adjustment
*/
#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 
#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 
#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 
#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL                    0x000077BB
#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT                     19
#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK                      0x00380000U

/*
* Pullup drive strength adjustment
*/
#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 
#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 
#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 
#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL                    0x000077BB
#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT                     16
#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK                      0x00070000U

/*
* DRAM Impedance Divide Ratio
*/
#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 
#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 
#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 
#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL                   0x000077BB
#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT                    12
#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK                     0x0000F000U

/*
* HOST Impedance Divide Ratio
*/
#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 
#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 
#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 
#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL                   0x000077BB
#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT                    8
#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK                     0x00000F00U

/*
* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
    * ve strength calibration)
*/
#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 
#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 
#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL                0x000077BB
#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT                 4
#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK                  0x000000F0U

/*
* Impedance Divide Ratio (pullup drive calibration during asymmetric drive
    *  strength calibration)
*/
#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 
#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 
#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL                0x000077BB
#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT                 0
#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK                  0x0000000FU

/*
* Reserved. Return zeros on reads.
*/
#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 
#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 
#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 
#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL                   0x00000000
#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT                    26
#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK                     0xFC000000U

/*
* Override value for the pull-up output impedance
*/
#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 
#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 
#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 
#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL                0x00000000
#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT                 16
#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK                  0x03FF0000U

/*
* Reserved. Return zeros on reads.
*/
#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 
#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 
#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 
#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL                   0x00000000
#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT                    10
#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK                     0x0000FC00U

/*
* Override value for the pull-down output impedance
*/
#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 
#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 
#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 
#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL                0x00000000
#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT                 0
#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK                  0x000003FFU

/*
* Reserved. Return zeros on reads.
*/
#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 
#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 
#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 
#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL                   0x00000000
#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT                    26
#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK                     0xFC000000U

/*
* Override value for the pull-up termination
*/
#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 
#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 
#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 
#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL                0x00000000
#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT                 16
#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK                  0x03FF0000U

/*
* Reserved. Return zeros on reads.
*/
#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 
#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 
#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 
#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL                   0x00000000
#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT                    10
#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK                     0x0000FC00U

/*
* Override value for the pull-down termination
*/
#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 
#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 
#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 
#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL                0x00000000
#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT                 0
#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK                  0x000003FFU

/*
* Pull-down drive strength ZCTRL over-ride enable
*/
#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 
#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 
#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 
#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL                      0x000077BB
#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT                       31
#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK                        0x80000000U

/*
* Pull-up drive strength ZCTRL over-ride enable
*/
#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 
#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 
#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 
#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL                      0x000077BB
#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT                       30
#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK                        0x40000000U

/*
* Pull-down termination ZCTRL over-ride enable
*/
#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 
#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 
#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 
#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL                      0x000077BB
#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT                       29
#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK                        0x20000000U

/*
* Pull-up termination ZCTRL over-ride enable
*/
#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 
#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 
#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 
#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL                      0x000077BB
#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT                       28
#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK                        0x10000000U

/*
* Calibration segment bypass
*/
#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 
#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 
#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 
#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL                          0x000077BB
#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT                           27
#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK                            0x08000000U

/*
* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
    *  is driven by the PUB
*/
#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 
#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 
#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 
#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL                         0x000077BB
#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT                          25
#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK                           0x06000000U

/*
* Termination adjustment
*/
#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 
#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 
#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 
#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL                       0x000077BB
#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT                        22
#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK                         0x01C00000U

/*
* Pulldown drive strength adjustment
*/
#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 
#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 
#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 
#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL                    0x000077BB
#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT                     19
#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK                      0x00380000U

/*
* Pullup drive strength adjustment
*/
#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 
#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 
#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 
#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL                    0x000077BB
#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT                     16
#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK                      0x00070000U

/*
* DRAM Impedance Divide Ratio
*/
#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 
#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 
#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 
#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL                   0x000077BB
#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT                    12
#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK                     0x0000F000U

/*
* HOST Impedance Divide Ratio
*/
#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 
#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 
#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 
#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL                   0x000077BB
#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT                    8
#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK                     0x00000F00U

/*
* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
    * ve strength calibration)
*/
#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 
#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 
#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL                0x000077BB
#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT                 4
#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK                  0x000000F0U

/*
* Impedance Divide Ratio (pullup drive calibration during asymmetric drive
    *  strength calibration)
*/
#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 
#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 
#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL                0x000077BB
#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT                 0
#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK                  0x0000000FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX0GCR0_CALBYP_MASK 
#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX0GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX0GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX0GCR0_MDLEN_MASK 
#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX0GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX0GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX0GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX0GCR0_DQSDCC_MASK 
#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX0GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX0GCR0_RDDLY_MASK 
#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX0GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX0GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX0GCR0_RTTOAL_MASK 
#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX0GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX0GCR0_RTTOH_MASK 
#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX0GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX0GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX0GCR0_DQSRPD_MASK 
#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX0GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX0GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX0GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX0GCR0_DQSGODT_MASK 
#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX0GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX0GCR0_DQSGOE_MASK 
#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX0GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX0GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX0GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX0GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX0GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX0GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX0GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX0GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX0GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX0GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX0GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX0GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX1GCR0_CALBYP_MASK 
#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX1GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX1GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX1GCR0_MDLEN_MASK 
#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX1GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX1GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX1GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX1GCR0_DQSDCC_MASK 
#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX1GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX1GCR0_RDDLY_MASK 
#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX1GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX1GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX1GCR0_RTTOAL_MASK 
#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX1GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX1GCR0_RTTOH_MASK 
#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX1GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX1GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX1GCR0_DQSRPD_MASK 
#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX1GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX1GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX1GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX1GCR0_DQSGODT_MASK 
#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX1GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX1GCR0_DQSGOE_MASK 
#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX1GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX1GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX1GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX1GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX1GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX1GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX1GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX1GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX1GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX1GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX1GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX1GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX2GCR0_CALBYP_MASK 
#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX2GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX2GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX2GCR0_MDLEN_MASK 
#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX2GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX2GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX2GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX2GCR0_DQSDCC_MASK 
#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX2GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX2GCR0_RDDLY_MASK 
#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX2GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX2GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX2GCR0_RTTOAL_MASK 
#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX2GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX2GCR0_RTTOH_MASK 
#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX2GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX2GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX2GCR0_DQSRPD_MASK 
#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX2GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX2GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX2GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX2GCR0_DQSGODT_MASK 
#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX2GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX2GCR0_DQSGOE_MASK 
#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX2GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Enables the PDR mode for DQ[7:0]
*/
#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 
#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 
#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK 
#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT                        16
#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK                         0xFFFF0000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 
#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK 
#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL                     0x00007FFF
#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX2GCR1_RESERVED_15_MASK                       0x00008000U

/*
* Select the delayed or non-delayed read data strobe #
*/
#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 
#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT 
#undef DDR_PHY_DX2GCR1_QSNSEL_MASK 
#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL                          0x00007FFF
#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT                           14
#define DDR_PHY_DX2GCR1_QSNSEL_MASK                            0x00004000U

/*
* Select the delayed or non-delayed read data strobe
*/
#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL 
#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT 
#undef DDR_PHY_DX2GCR1_QSSEL_MASK 
#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL                           0x00007FFF
#define DDR_PHY_DX2GCR1_QSSEL_SHIFT                            13
#define DDR_PHY_DX2GCR1_QSSEL_MASK                             0x00002000U

/*
* Enables Read Data Strobe in a byte lane
*/
#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL 
#undef DDR_PHY_DX2GCR1_OEEN_SHIFT 
#undef DDR_PHY_DX2GCR1_OEEN_MASK 
#define DDR_PHY_DX2GCR1_OEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX2GCR1_OEEN_SHIFT                             12
#define DDR_PHY_DX2GCR1_OEEN_MASK                              0x00001000U

/*
* Enables PDR in a byte lane
*/
#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL 
#undef DDR_PHY_DX2GCR1_PDREN_SHIFT 
#undef DDR_PHY_DX2GCR1_PDREN_MASK 
#define DDR_PHY_DX2GCR1_PDREN_DEFVAL                           0x00007FFF
#define DDR_PHY_DX2GCR1_PDREN_SHIFT                            11
#define DDR_PHY_DX2GCR1_PDREN_MASK                             0x00000800U

/*
* Enables ODT/TE in a byte lane
*/
#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL 
#undef DDR_PHY_DX2GCR1_TEEN_SHIFT 
#undef DDR_PHY_DX2GCR1_TEEN_MASK 
#define DDR_PHY_DX2GCR1_TEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX2GCR1_TEEN_SHIFT                             10
#define DDR_PHY_DX2GCR1_TEEN_MASK                              0x00000400U

/*
* Enables Write Data strobe in a byte lane
*/
#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL 
#undef DDR_PHY_DX2GCR1_DSEN_SHIFT 
#undef DDR_PHY_DX2GCR1_DSEN_MASK 
#define DDR_PHY_DX2GCR1_DSEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX2GCR1_DSEN_SHIFT                             9
#define DDR_PHY_DX2GCR1_DSEN_MASK                              0x00000200U

/*
* Enables DM pin in a byte lane
*/
#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL 
#undef DDR_PHY_DX2GCR1_DMEN_SHIFT 
#undef DDR_PHY_DX2GCR1_DMEN_MASK 
#define DDR_PHY_DX2GCR1_DMEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX2GCR1_DMEN_SHIFT                             8
#define DDR_PHY_DX2GCR1_DMEN_MASK                              0x00000100U

/*
* Enables DQ corresponding to each bit in a byte
*/
#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL 
#undef DDR_PHY_DX2GCR1_DQEN_SHIFT 
#undef DDR_PHY_DX2GCR1_DQEN_MASK 
#define DDR_PHY_DX2GCR1_DQEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX2GCR1_DQEN_SHIFT                             0
#define DDR_PHY_DX2GCR1_DQEN_MASK                              0x000000FFU

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX2GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX2GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX2GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX2GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX2GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX2GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX2GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX2GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX2GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX2GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX2GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX3GCR0_CALBYP_MASK 
#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX3GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX3GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX3GCR0_MDLEN_MASK 
#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX3GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX3GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX3GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX3GCR0_DQSDCC_MASK 
#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX3GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX3GCR0_RDDLY_MASK 
#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX3GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX3GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX3GCR0_RTTOAL_MASK 
#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX3GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX3GCR0_RTTOH_MASK 
#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX3GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX3GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX3GCR0_DQSRPD_MASK 
#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX3GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX3GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX3GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX3GCR0_DQSGODT_MASK 
#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX3GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX3GCR0_DQSGOE_MASK 
#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX3GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Enables the PDR mode for DQ[7:0]
*/
#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 
#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 
#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK 
#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT                        16
#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK                         0xFFFF0000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 
#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK 
#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL                     0x00007FFF
#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX3GCR1_RESERVED_15_MASK                       0x00008000U

/*
* Select the delayed or non-delayed read data strobe #
*/
#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 
#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT 
#undef DDR_PHY_DX3GCR1_QSNSEL_MASK 
#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL                          0x00007FFF
#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT                           14
#define DDR_PHY_DX3GCR1_QSNSEL_MASK                            0x00004000U

/*
* Select the delayed or non-delayed read data strobe
*/
#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL 
#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT 
#undef DDR_PHY_DX3GCR1_QSSEL_MASK 
#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL                           0x00007FFF
#define DDR_PHY_DX3GCR1_QSSEL_SHIFT                            13
#define DDR_PHY_DX3GCR1_QSSEL_MASK                             0x00002000U

/*
* Enables Read Data Strobe in a byte lane
*/
#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL 
#undef DDR_PHY_DX3GCR1_OEEN_SHIFT 
#undef DDR_PHY_DX3GCR1_OEEN_MASK 
#define DDR_PHY_DX3GCR1_OEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX3GCR1_OEEN_SHIFT                             12
#define DDR_PHY_DX3GCR1_OEEN_MASK                              0x00001000U

/*
* Enables PDR in a byte lane
*/
#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL 
#undef DDR_PHY_DX3GCR1_PDREN_SHIFT 
#undef DDR_PHY_DX3GCR1_PDREN_MASK 
#define DDR_PHY_DX3GCR1_PDREN_DEFVAL                           0x00007FFF
#define DDR_PHY_DX3GCR1_PDREN_SHIFT                            11
#define DDR_PHY_DX3GCR1_PDREN_MASK                             0x00000800U

/*
* Enables ODT/TE in a byte lane
*/
#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL 
#undef DDR_PHY_DX3GCR1_TEEN_SHIFT 
#undef DDR_PHY_DX3GCR1_TEEN_MASK 
#define DDR_PHY_DX3GCR1_TEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX3GCR1_TEEN_SHIFT                             10
#define DDR_PHY_DX3GCR1_TEEN_MASK                              0x00000400U

/*
* Enables Write Data strobe in a byte lane
*/
#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL 
#undef DDR_PHY_DX3GCR1_DSEN_SHIFT 
#undef DDR_PHY_DX3GCR1_DSEN_MASK 
#define DDR_PHY_DX3GCR1_DSEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX3GCR1_DSEN_SHIFT                             9
#define DDR_PHY_DX3GCR1_DSEN_MASK                              0x00000200U

/*
* Enables DM pin in a byte lane
*/
#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL 
#undef DDR_PHY_DX3GCR1_DMEN_SHIFT 
#undef DDR_PHY_DX3GCR1_DMEN_MASK 
#define DDR_PHY_DX3GCR1_DMEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX3GCR1_DMEN_SHIFT                             8
#define DDR_PHY_DX3GCR1_DMEN_MASK                              0x00000100U

/*
* Enables DQ corresponding to each bit in a byte
*/
#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL 
#undef DDR_PHY_DX3GCR1_DQEN_SHIFT 
#undef DDR_PHY_DX3GCR1_DQEN_MASK 
#define DDR_PHY_DX3GCR1_DQEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX3GCR1_DQEN_SHIFT                             0
#define DDR_PHY_DX3GCR1_DQEN_MASK                              0x000000FFU

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX3GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX3GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX3GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX3GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX3GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX3GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX3GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX3GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX3GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX3GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX3GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX4GCR0_CALBYP_MASK 
#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX4GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX4GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX4GCR0_MDLEN_MASK 
#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX4GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX4GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX4GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX4GCR0_DQSDCC_MASK 
#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX4GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX4GCR0_RDDLY_MASK 
#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX4GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX4GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX4GCR0_RTTOAL_MASK 
#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX4GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX4GCR0_RTTOH_MASK 
#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX4GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX4GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX4GCR0_DQSRPD_MASK 
#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX4GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX4GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX4GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX4GCR0_DQSGODT_MASK 
#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX4GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX4GCR0_DQSGOE_MASK 
#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX4GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Enables the PDR mode for DQ[7:0]
*/
#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 
#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 
#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK 
#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT                        16
#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK                         0xFFFF0000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 
#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK 
#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL                     0x00007FFF
#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX4GCR1_RESERVED_15_MASK                       0x00008000U

/*
* Select the delayed or non-delayed read data strobe #
*/
#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 
#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT 
#undef DDR_PHY_DX4GCR1_QSNSEL_MASK 
#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL                          0x00007FFF
#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT                           14
#define DDR_PHY_DX4GCR1_QSNSEL_MASK                            0x00004000U

/*
* Select the delayed or non-delayed read data strobe
*/
#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL 
#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT 
#undef DDR_PHY_DX4GCR1_QSSEL_MASK 
#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL                           0x00007FFF
#define DDR_PHY_DX4GCR1_QSSEL_SHIFT                            13
#define DDR_PHY_DX4GCR1_QSSEL_MASK                             0x00002000U

/*
* Enables Read Data Strobe in a byte lane
*/
#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL 
#undef DDR_PHY_DX4GCR1_OEEN_SHIFT 
#undef DDR_PHY_DX4GCR1_OEEN_MASK 
#define DDR_PHY_DX4GCR1_OEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX4GCR1_OEEN_SHIFT                             12
#define DDR_PHY_DX4GCR1_OEEN_MASK                              0x00001000U

/*
* Enables PDR in a byte lane
*/
#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL 
#undef DDR_PHY_DX4GCR1_PDREN_SHIFT 
#undef DDR_PHY_DX4GCR1_PDREN_MASK 
#define DDR_PHY_DX4GCR1_PDREN_DEFVAL                           0x00007FFF
#define DDR_PHY_DX4GCR1_PDREN_SHIFT                            11
#define DDR_PHY_DX4GCR1_PDREN_MASK                             0x00000800U

/*
* Enables ODT/TE in a byte lane
*/
#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL 
#undef DDR_PHY_DX4GCR1_TEEN_SHIFT 
#undef DDR_PHY_DX4GCR1_TEEN_MASK 
#define DDR_PHY_DX4GCR1_TEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX4GCR1_TEEN_SHIFT                             10
#define DDR_PHY_DX4GCR1_TEEN_MASK                              0x00000400U

/*
* Enables Write Data strobe in a byte lane
*/
#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL 
#undef DDR_PHY_DX4GCR1_DSEN_SHIFT 
#undef DDR_PHY_DX4GCR1_DSEN_MASK 
#define DDR_PHY_DX4GCR1_DSEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX4GCR1_DSEN_SHIFT                             9
#define DDR_PHY_DX4GCR1_DSEN_MASK                              0x00000200U

/*
* Enables DM pin in a byte lane
*/
#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL 
#undef DDR_PHY_DX4GCR1_DMEN_SHIFT 
#undef DDR_PHY_DX4GCR1_DMEN_MASK 
#define DDR_PHY_DX4GCR1_DMEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX4GCR1_DMEN_SHIFT                             8
#define DDR_PHY_DX4GCR1_DMEN_MASK                              0x00000100U

/*
* Enables DQ corresponding to each bit in a byte
*/
#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL 
#undef DDR_PHY_DX4GCR1_DQEN_SHIFT 
#undef DDR_PHY_DX4GCR1_DQEN_MASK 
#define DDR_PHY_DX4GCR1_DQEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX4GCR1_DQEN_SHIFT                             0
#define DDR_PHY_DX4GCR1_DQEN_MASK                              0x000000FFU

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX4GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX4GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX4GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX4GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX4GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX4GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX4GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX4GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX4GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX4GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX4GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX5GCR0_CALBYP_MASK 
#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX5GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX5GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX5GCR0_MDLEN_MASK 
#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX5GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX5GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX5GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX5GCR0_DQSDCC_MASK 
#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX5GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX5GCR0_RDDLY_MASK 
#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX5GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX5GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX5GCR0_RTTOAL_MASK 
#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX5GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX5GCR0_RTTOH_MASK 
#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX5GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX5GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX5GCR0_DQSRPD_MASK 
#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX5GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX5GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX5GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX5GCR0_DQSGODT_MASK 
#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX5GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX5GCR0_DQSGOE_MASK 
#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX5GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Enables the PDR mode for DQ[7:0]
*/
#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 
#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 
#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK 
#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT                        16
#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK                         0xFFFF0000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 
#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK 
#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL                     0x00007FFF
#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX5GCR1_RESERVED_15_MASK                       0x00008000U

/*
* Select the delayed or non-delayed read data strobe #
*/
#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 
#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT 
#undef DDR_PHY_DX5GCR1_QSNSEL_MASK 
#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL                          0x00007FFF
#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT                           14
#define DDR_PHY_DX5GCR1_QSNSEL_MASK                            0x00004000U

/*
* Select the delayed or non-delayed read data strobe
*/
#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL 
#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT 
#undef DDR_PHY_DX5GCR1_QSSEL_MASK 
#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL                           0x00007FFF
#define DDR_PHY_DX5GCR1_QSSEL_SHIFT                            13
#define DDR_PHY_DX5GCR1_QSSEL_MASK                             0x00002000U

/*
* Enables Read Data Strobe in a byte lane
*/
#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL 
#undef DDR_PHY_DX5GCR1_OEEN_SHIFT 
#undef DDR_PHY_DX5GCR1_OEEN_MASK 
#define DDR_PHY_DX5GCR1_OEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX5GCR1_OEEN_SHIFT                             12
#define DDR_PHY_DX5GCR1_OEEN_MASK                              0x00001000U

/*
* Enables PDR in a byte lane
*/
#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL 
#undef DDR_PHY_DX5GCR1_PDREN_SHIFT 
#undef DDR_PHY_DX5GCR1_PDREN_MASK 
#define DDR_PHY_DX5GCR1_PDREN_DEFVAL                           0x00007FFF
#define DDR_PHY_DX5GCR1_PDREN_SHIFT                            11
#define DDR_PHY_DX5GCR1_PDREN_MASK                             0x00000800U

/*
* Enables ODT/TE in a byte lane
*/
#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL 
#undef DDR_PHY_DX5GCR1_TEEN_SHIFT 
#undef DDR_PHY_DX5GCR1_TEEN_MASK 
#define DDR_PHY_DX5GCR1_TEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX5GCR1_TEEN_SHIFT                             10
#define DDR_PHY_DX5GCR1_TEEN_MASK                              0x00000400U

/*
* Enables Write Data strobe in a byte lane
*/
#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL 
#undef DDR_PHY_DX5GCR1_DSEN_SHIFT 
#undef DDR_PHY_DX5GCR1_DSEN_MASK 
#define DDR_PHY_DX5GCR1_DSEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX5GCR1_DSEN_SHIFT                             9
#define DDR_PHY_DX5GCR1_DSEN_MASK                              0x00000200U

/*
* Enables DM pin in a byte lane
*/
#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL 
#undef DDR_PHY_DX5GCR1_DMEN_SHIFT 
#undef DDR_PHY_DX5GCR1_DMEN_MASK 
#define DDR_PHY_DX5GCR1_DMEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX5GCR1_DMEN_SHIFT                             8
#define DDR_PHY_DX5GCR1_DMEN_MASK                              0x00000100U

/*
* Enables DQ corresponding to each bit in a byte
*/
#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL 
#undef DDR_PHY_DX5GCR1_DQEN_SHIFT 
#undef DDR_PHY_DX5GCR1_DQEN_MASK 
#define DDR_PHY_DX5GCR1_DQEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX5GCR1_DQEN_SHIFT                             0
#define DDR_PHY_DX5GCR1_DQEN_MASK                              0x000000FFU

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX5GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX5GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX5GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX5GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX5GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX5GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX5GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX5GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX5GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX5GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX5GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX6GCR0_CALBYP_MASK 
#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX6GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX6GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX6GCR0_MDLEN_MASK 
#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX6GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX6GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX6GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX6GCR0_DQSDCC_MASK 
#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX6GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX6GCR0_RDDLY_MASK 
#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX6GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX6GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX6GCR0_RTTOAL_MASK 
#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX6GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX6GCR0_RTTOH_MASK 
#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX6GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX6GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX6GCR0_DQSRPD_MASK 
#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX6GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX6GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX6GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX6GCR0_DQSGODT_MASK 
#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX6GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX6GCR0_DQSGOE_MASK 
#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX6GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Enables the PDR mode for DQ[7:0]
*/
#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 
#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 
#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK 
#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT                        16
#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK                         0xFFFF0000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 
#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK 
#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL                     0x00007FFF
#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX6GCR1_RESERVED_15_MASK                       0x00008000U

/*
* Select the delayed or non-delayed read data strobe #
*/
#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 
#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT 
#undef DDR_PHY_DX6GCR1_QSNSEL_MASK 
#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL                          0x00007FFF
#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT                           14
#define DDR_PHY_DX6GCR1_QSNSEL_MASK                            0x00004000U

/*
* Select the delayed or non-delayed read data strobe
*/
#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL 
#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT 
#undef DDR_PHY_DX6GCR1_QSSEL_MASK 
#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL                           0x00007FFF
#define DDR_PHY_DX6GCR1_QSSEL_SHIFT                            13
#define DDR_PHY_DX6GCR1_QSSEL_MASK                             0x00002000U

/*
* Enables Read Data Strobe in a byte lane
*/
#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL 
#undef DDR_PHY_DX6GCR1_OEEN_SHIFT 
#undef DDR_PHY_DX6GCR1_OEEN_MASK 
#define DDR_PHY_DX6GCR1_OEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX6GCR1_OEEN_SHIFT                             12
#define DDR_PHY_DX6GCR1_OEEN_MASK                              0x00001000U

/*
* Enables PDR in a byte lane
*/
#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL 
#undef DDR_PHY_DX6GCR1_PDREN_SHIFT 
#undef DDR_PHY_DX6GCR1_PDREN_MASK 
#define DDR_PHY_DX6GCR1_PDREN_DEFVAL                           0x00007FFF
#define DDR_PHY_DX6GCR1_PDREN_SHIFT                            11
#define DDR_PHY_DX6GCR1_PDREN_MASK                             0x00000800U

/*
* Enables ODT/TE in a byte lane
*/
#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL 
#undef DDR_PHY_DX6GCR1_TEEN_SHIFT 
#undef DDR_PHY_DX6GCR1_TEEN_MASK 
#define DDR_PHY_DX6GCR1_TEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX6GCR1_TEEN_SHIFT                             10
#define DDR_PHY_DX6GCR1_TEEN_MASK                              0x00000400U

/*
* Enables Write Data strobe in a byte lane
*/
#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL 
#undef DDR_PHY_DX6GCR1_DSEN_SHIFT 
#undef DDR_PHY_DX6GCR1_DSEN_MASK 
#define DDR_PHY_DX6GCR1_DSEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX6GCR1_DSEN_SHIFT                             9
#define DDR_PHY_DX6GCR1_DSEN_MASK                              0x00000200U

/*
* Enables DM pin in a byte lane
*/
#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL 
#undef DDR_PHY_DX6GCR1_DMEN_SHIFT 
#undef DDR_PHY_DX6GCR1_DMEN_MASK 
#define DDR_PHY_DX6GCR1_DMEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX6GCR1_DMEN_SHIFT                             8
#define DDR_PHY_DX6GCR1_DMEN_MASK                              0x00000100U

/*
* Enables DQ corresponding to each bit in a byte
*/
#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL 
#undef DDR_PHY_DX6GCR1_DQEN_SHIFT 
#undef DDR_PHY_DX6GCR1_DQEN_MASK 
#define DDR_PHY_DX6GCR1_DQEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX6GCR1_DQEN_SHIFT                             0
#define DDR_PHY_DX6GCR1_DQEN_MASK                              0x000000FFU

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX6GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX6GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX6GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX6GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX6GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX6GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX6GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX6GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX6GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX6GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX6GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX7GCR0_CALBYP_MASK 
#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX7GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX7GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX7GCR0_MDLEN_MASK 
#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX7GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX7GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX7GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX7GCR0_DQSDCC_MASK 
#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX7GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX7GCR0_RDDLY_MASK 
#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX7GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX7GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX7GCR0_RTTOAL_MASK 
#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX7GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX7GCR0_RTTOH_MASK 
#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX7GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX7GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX7GCR0_DQSRPD_MASK 
#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX7GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX7GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX7GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX7GCR0_DQSGODT_MASK 
#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX7GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX7GCR0_DQSGOE_MASK 
#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX7GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Enables the PDR mode for DQ[7:0]
*/
#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 
#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 
#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK 
#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT                        16
#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK                         0xFFFF0000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 
#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK 
#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL                     0x00007FFF
#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX7GCR1_RESERVED_15_MASK                       0x00008000U

/*
* Select the delayed or non-delayed read data strobe #
*/
#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 
#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT 
#undef DDR_PHY_DX7GCR1_QSNSEL_MASK 
#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL                          0x00007FFF
#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT                           14
#define DDR_PHY_DX7GCR1_QSNSEL_MASK                            0x00004000U

/*
* Select the delayed or non-delayed read data strobe
*/
#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL 
#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT 
#undef DDR_PHY_DX7GCR1_QSSEL_MASK 
#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL                           0x00007FFF
#define DDR_PHY_DX7GCR1_QSSEL_SHIFT                            13
#define DDR_PHY_DX7GCR1_QSSEL_MASK                             0x00002000U

/*
* Enables Read Data Strobe in a byte lane
*/
#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL 
#undef DDR_PHY_DX7GCR1_OEEN_SHIFT 
#undef DDR_PHY_DX7GCR1_OEEN_MASK 
#define DDR_PHY_DX7GCR1_OEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX7GCR1_OEEN_SHIFT                             12
#define DDR_PHY_DX7GCR1_OEEN_MASK                              0x00001000U

/*
* Enables PDR in a byte lane
*/
#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL 
#undef DDR_PHY_DX7GCR1_PDREN_SHIFT 
#undef DDR_PHY_DX7GCR1_PDREN_MASK 
#define DDR_PHY_DX7GCR1_PDREN_DEFVAL                           0x00007FFF
#define DDR_PHY_DX7GCR1_PDREN_SHIFT                            11
#define DDR_PHY_DX7GCR1_PDREN_MASK                             0x00000800U

/*
* Enables ODT/TE in a byte lane
*/
#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL 
#undef DDR_PHY_DX7GCR1_TEEN_SHIFT 
#undef DDR_PHY_DX7GCR1_TEEN_MASK 
#define DDR_PHY_DX7GCR1_TEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX7GCR1_TEEN_SHIFT                             10
#define DDR_PHY_DX7GCR1_TEEN_MASK                              0x00000400U

/*
* Enables Write Data strobe in a byte lane
*/
#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL 
#undef DDR_PHY_DX7GCR1_DSEN_SHIFT 
#undef DDR_PHY_DX7GCR1_DSEN_MASK 
#define DDR_PHY_DX7GCR1_DSEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX7GCR1_DSEN_SHIFT                             9
#define DDR_PHY_DX7GCR1_DSEN_MASK                              0x00000200U

/*
* Enables DM pin in a byte lane
*/
#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL 
#undef DDR_PHY_DX7GCR1_DMEN_SHIFT 
#undef DDR_PHY_DX7GCR1_DMEN_MASK 
#define DDR_PHY_DX7GCR1_DMEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX7GCR1_DMEN_SHIFT                             8
#define DDR_PHY_DX7GCR1_DMEN_MASK                              0x00000100U

/*
* Enables DQ corresponding to each bit in a byte
*/
#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL 
#undef DDR_PHY_DX7GCR1_DQEN_SHIFT 
#undef DDR_PHY_DX7GCR1_DQEN_MASK 
#define DDR_PHY_DX7GCR1_DQEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX7GCR1_DQEN_SHIFT                             0
#define DDR_PHY_DX7GCR1_DQEN_MASK                              0x000000FFU

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX7GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX7GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX7GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX7GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX7GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX7GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX7GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX7GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX7GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX7GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX7GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Calibration Bypass
*/
#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL 
#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT 
#undef DDR_PHY_DX8GCR0_CALBYP_MASK 
#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL                          0x40200204
#define DDR_PHY_DX8GCR0_CALBYP_SHIFT                           31
#define DDR_PHY_DX8GCR0_CALBYP_MASK                            0x80000000U

/*
* Master Delay Line Enable
*/
#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL 
#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT 
#undef DDR_PHY_DX8GCR0_MDLEN_MASK 
#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL                           0x40200204
#define DDR_PHY_DX8GCR0_MDLEN_SHIFT                            30
#define DDR_PHY_DX8GCR0_MDLEN_MASK                             0x40000000U

/*
* Configurable ODT(TE) Phase Shift
*/
#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 
#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 
#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK 
#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT                         28
#define DDR_PHY_DX8GCR0_CODTSHFT_MASK                          0x30000000U

/*
* DQS Duty Cycle Correction
*/
#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 
#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT 
#undef DDR_PHY_DX8GCR0_DQSDCC_MASK 
#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL                          0x40200204
#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT                           24
#define DDR_PHY_DX8GCR0_DQSDCC_MASK                            0x0F000000U

/*
* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
    *  input for the respective bypte lane of the PHY
*/
#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL 
#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT 
#undef DDR_PHY_DX8GCR0_RDDLY_MASK 
#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL                           0x40200204
#define DDR_PHY_DX8GCR0_RDDLY_SHIFT                            20
#define DDR_PHY_DX8GCR0_RDDLY_MASK                             0x00F00000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 
#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 
#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 
#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL                  0x40200204
#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT                   14
#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK                    0x000FC000U

/*
* DQSNSE Power Down Receiver
*/
#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 
#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 
#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 
#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL                       0x40200204
#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT                        13
#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK                         0x00002000U

/*
* DQSSE Power Down Receiver
*/
#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 
#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 
#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK 
#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL                        0x40200204
#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT                         12
#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK                          0x00001000U

/*
* RTT On Additive Latency
*/
#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 
#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT 
#undef DDR_PHY_DX8GCR0_RTTOAL_MASK 
#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL                          0x40200204
#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT                           11
#define DDR_PHY_DX8GCR0_RTTOAL_MASK                            0x00000800U

/*
* RTT Output Hold
*/
#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL 
#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT 
#undef DDR_PHY_DX8GCR0_RTTOH_MASK 
#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL                           0x40200204
#define DDR_PHY_DX8GCR0_RTTOH_SHIFT                            9
#define DDR_PHY_DX8GCR0_RTTOH_MASK                             0x00000600U

/*
* Configurable PDR Phase Shift
*/
#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 
#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 
#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK 
#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL                        0x40200204
#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT                         7
#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK                          0x00000180U

/*
* DQSR Power Down
*/
#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 
#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT 
#undef DDR_PHY_DX8GCR0_DQSRPD_MASK 
#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL                          0x40200204
#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT                           6
#define DDR_PHY_DX8GCR0_DQSRPD_MASK                            0x00000040U

/*
* DQSG Power Down Receiver
*/
#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 
#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 
#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK 
#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL                         0x40200204
#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT                          5
#define DDR_PHY_DX8GCR0_DQSGPDR_MASK                           0x00000020U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 
#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 
#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK 
#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL                      0x40200204
#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT                       4
#define DDR_PHY_DX8GCR0_RESERVED_4_MASK                        0x00000010U

/*
* DQSG On-Die Termination
*/
#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 
#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT 
#undef DDR_PHY_DX8GCR0_DQSGODT_MASK 
#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL                         0x40200204
#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT                          3
#define DDR_PHY_DX8GCR0_DQSGODT_MASK                           0x00000008U

/*
* DQSG Output Enable
*/
#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 
#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT 
#undef DDR_PHY_DX8GCR0_DQSGOE_MASK 
#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL                          0x40200204
#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT                           2
#define DDR_PHY_DX8GCR0_DQSGOE_MASK                            0x00000004U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 
#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 
#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 
#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL                    0x40200204
#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT                     0
#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK                      0x00000003U

/*
* Enables the PDR mode for DQ[7:0]
*/
#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 
#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 
#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK 
#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT                        16
#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK                         0xFFFF0000U

/*
* Reserved. Returns zeroes on reads.
*/
#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 
#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK 
#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL                     0x00007FFF
#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX8GCR1_RESERVED_15_MASK                       0x00008000U

/*
* Select the delayed or non-delayed read data strobe #
*/
#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 
#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT 
#undef DDR_PHY_DX8GCR1_QSNSEL_MASK 
#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL                          0x00007FFF
#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT                           14
#define DDR_PHY_DX8GCR1_QSNSEL_MASK                            0x00004000U

/*
* Select the delayed or non-delayed read data strobe
*/
#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL 
#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT 
#undef DDR_PHY_DX8GCR1_QSSEL_MASK 
#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL                           0x00007FFF
#define DDR_PHY_DX8GCR1_QSSEL_SHIFT                            13
#define DDR_PHY_DX8GCR1_QSSEL_MASK                             0x00002000U

/*
* Enables Read Data Strobe in a byte lane
*/
#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL 
#undef DDR_PHY_DX8GCR1_OEEN_SHIFT 
#undef DDR_PHY_DX8GCR1_OEEN_MASK 
#define DDR_PHY_DX8GCR1_OEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX8GCR1_OEEN_SHIFT                             12
#define DDR_PHY_DX8GCR1_OEEN_MASK                              0x00001000U

/*
* Enables PDR in a byte lane
*/
#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL 
#undef DDR_PHY_DX8GCR1_PDREN_SHIFT 
#undef DDR_PHY_DX8GCR1_PDREN_MASK 
#define DDR_PHY_DX8GCR1_PDREN_DEFVAL                           0x00007FFF
#define DDR_PHY_DX8GCR1_PDREN_SHIFT                            11
#define DDR_PHY_DX8GCR1_PDREN_MASK                             0x00000800U

/*
* Enables ODT/TE in a byte lane
*/
#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL 
#undef DDR_PHY_DX8GCR1_TEEN_SHIFT 
#undef DDR_PHY_DX8GCR1_TEEN_MASK 
#define DDR_PHY_DX8GCR1_TEEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX8GCR1_TEEN_SHIFT                             10
#define DDR_PHY_DX8GCR1_TEEN_MASK                              0x00000400U

/*
* Enables Write Data strobe in a byte lane
*/
#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL 
#undef DDR_PHY_DX8GCR1_DSEN_SHIFT 
#undef DDR_PHY_DX8GCR1_DSEN_MASK 
#define DDR_PHY_DX8GCR1_DSEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX8GCR1_DSEN_SHIFT                             9
#define DDR_PHY_DX8GCR1_DSEN_MASK                              0x00000200U

/*
* Enables DM pin in a byte lane
*/
#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL 
#undef DDR_PHY_DX8GCR1_DMEN_SHIFT 
#undef DDR_PHY_DX8GCR1_DMEN_MASK 
#define DDR_PHY_DX8GCR1_DMEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX8GCR1_DMEN_SHIFT                             8
#define DDR_PHY_DX8GCR1_DMEN_MASK                              0x00000100U

/*
* Enables DQ corresponding to each bit in a byte
*/
#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL 
#undef DDR_PHY_DX8GCR1_DQEN_SHIFT 
#undef DDR_PHY_DX8GCR1_DQEN_MASK 
#define DDR_PHY_DX8GCR1_DQEN_DEFVAL                            0x00007FFF
#define DDR_PHY_DX8GCR1_DQEN_SHIFT                             0
#define DDR_PHY_DX8GCR1_DQEN_MASK                              0x000000FFU

/*
* Byte lane VREF IOM (Used only by D4MU IOs)
*/
#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 
#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 
#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 
#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT                   29
#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK                    0xE0000000U

/*
* Byte Lane VREF Pad Enable
*/
#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK 
#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT                         28
#define DDR_PHY_DX8GCR4_DXREFPEN_MASK                          0x10000000U

/*
* Byte Lane Internal VREF Enable
*/
#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK 
#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT                         26
#define DDR_PHY_DX8GCR4_DXREFEEN_MASK                          0x0C000000U

/*
* Byte Lane Single-End VREF Enable
*/
#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK 
#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT                         25
#define DDR_PHY_DX8GCR4_DXREFSEN_MASK                          0x02000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 
#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 
#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK 
#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL                     0x0E00003C
#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT                      24
#define DDR_PHY_DX8GCR4_RESERVED_24_MASK                       0x01000000U

/*
* External VREF generator REFSEL range select
*/
#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 
#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT                   23
#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK                    0x00800000U

/*
* Byte Lane External VREF Select
*/
#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK 
#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT                        16
#define DDR_PHY_DX8GCR4_DXREFESEL_MASK                         0x007F0000U

/*
* Single ended VREF generator REFSEL range select
*/
#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 
#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT                   15
#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK                    0x00008000U

/*
* Byte Lane Single-End VREF Select
*/
#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK 
#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT                        8
#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK                         0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 
#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK                      0x000000C0U

/*
* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK 
#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL                        0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT                         2
#define DDR_PHY_DX8GCR4_DXREFIEN_MASK                          0x0000003CU

/*
* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
*/
#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 
#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 
#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK 
#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL                       0x0E00003C
#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT                        0
#define DDR_PHY_DX8GCR4_DXREFIMON_MASK                         0x00000003U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 
#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK 
#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL                     0x09090909
#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT                      31
#define DDR_PHY_DX8GCR5_RESERVED_31_MASK                       0x80000000U

/*
* Byte Lane internal VREF Select for Rank 3
*/
#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 
#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 
#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK 
#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL                     0x09090909
#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT                      24
#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK                       0x7F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 
#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 
#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK 
#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL                     0x09090909
#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT                      23
#define DDR_PHY_DX8GCR5_RESERVED_23_MASK                       0x00800000U

/*
* Byte Lane internal VREF Select for Rank 2
*/
#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 
#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 
#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK 
#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL                     0x09090909
#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT                      16
#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK                       0x007F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 
#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 
#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK 
#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL                     0x09090909
#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT                      15
#define DDR_PHY_DX8GCR5_RESERVED_15_MASK                       0x00008000U

/*
* Byte Lane internal VREF Select for Rank 1
*/
#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 
#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 
#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK 
#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL                     0x09090909
#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT                      8
#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK                       0x00007F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 
#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 
#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK 
#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL                      0x09090909
#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT                       7
#define DDR_PHY_DX8GCR5_RESERVED_7_MASK                        0x00000080U

/*
* Byte Lane internal VREF Select for Rank 0
*/
#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 
#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 
#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK 
#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL                     0x09090909
#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT                      0
#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK                       0x0000007FU

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 
#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL                  0x09090909
#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT                   30
#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK                    0xC0000000U

/*
* DRAM DQ VREF Select for Rank3
*/
#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 
#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 
#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 
#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL                      0x09090909
#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT                       24
#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK                        0x3F000000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 
#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL                  0x09090909
#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT                   22
#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK                    0x00C00000U

/*
* DRAM DQ VREF Select for Rank2
*/
#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 
#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 
#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 
#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL                      0x09090909
#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT                       16
#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK                        0x003F0000U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 
#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 
#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 
#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL                  0x09090909
#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT                   14
#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK                    0x0000C000U

/*
* DRAM DQ VREF Select for Rank1
*/
#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 
#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 
#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 
#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL                      0x09090909
#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT                       8
#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK                        0x00003F00U

/*
* Reserved. Returns zeros on reads.
*/
#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 
#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 
#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 
#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL                    0x09090909
#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT                     6
#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK                      0x000000C0U

/*
* DRAM DQ VREF Select for Rank0
*/
#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 
#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 
#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 
#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL                      0x09090909
#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT                       0
#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK                        0x0000003FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 
#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT                 30
#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK                  0xC0000000U

/*
* Enable Clock Gating for DX ddr_clk
*/
#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 
#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 
#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT                    28
#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK                     0x30000000U

/*
* Enable Clock Gating for DX ctl_rd_clk
*/
#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 
#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 
#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT                   26
#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK                    0x0C000000U

/*
* Enable Clock Gating for DX ctl_clk
*/
#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 
#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 
#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT                   24
#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK                    0x03000000U

/*
* Selects the level to which clocks will be stalled when clock gating is e
    * nabled.
*/
#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 
#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 
#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL                      0x00019FFE
#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT                       22
#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK                        0x00C00000U

/*
* Loopback Mode
*/
#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 
#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK 
#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT                         21
#define DDR_PHY_DX8SL0OSC_LBMODE_MASK                          0x00200000U

/*
* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
*/
#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 
#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 
#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT                        20
#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK                         0x00100000U

/*
* Loopback DQS Gating
*/
#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 
#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK 
#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT                         18
#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK                          0x000C0000U

/*
* Loopback DQS Shift
*/
#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 
#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK 
#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT                         17
#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK                          0x00020000U

/*
* PHY High-Speed Reset
*/
#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 
#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK 
#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT                        16
#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK                         0x00010000U

/*
* PHY FIFO Reset
*/
#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 
#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK 
#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT                        15
#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK                         0x00008000U

/*
* Delay Line Test Start
*/
#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT 
#undef DDR_PHY_DX8SL0OSC_DLTST_MASK 
#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT                          14
#define DDR_PHY_DX8SL0OSC_DLTST_MASK                           0x00004000U

/*
* Delay Line Test Mode
*/
#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 
#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK 
#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT                        13
#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK                         0x00002000U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 
#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 
#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT                 11
#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK                  0x00001800U

/*
* Oscillator Mode Write-Data Delay Line Select
*/
#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 
#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 
#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT                        9
#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK                         0x00000600U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 
#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 
#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT                   7
#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK                    0x00000180U

/*
* Oscillator Mode Write-Leveling Delay Line Select
*/
#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 
#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK 
#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT                         5
#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK                          0x00000060U

/*
* Oscillator Mode Division
*/
#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 
#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK 
#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT                         1
#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK                          0x0000001EU

/*
* Oscillator Enable
*/
#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 
#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 
#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK 
#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT                          0
#define DDR_PHY_DX8SL0OSC_OSCEN_MASK                           0x00000001U

/*
* PLL Bypass
*/
#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 
#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT                      31
#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK                       0x80000000U

/*
* PLL Reset
*/
#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 
#define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT                      30
#define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK                       0x40000000U

/*
* PLL Power Down
*/
#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 
#define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT                       29
#define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK                        0x20000000U

/*
* Reference Stop Mode
*/
#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 
#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT                      28
#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK                       0x10000000U

/*
* PLL Frequency Select
*/
#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 
#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT                      24
#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK                       0x0F000000U

/*
* Relock Mode
*/
#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 
#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT                      23
#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK                       0x00800000U

/*
* Charge Pump Proportional Current Control
*/
#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 
#define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT                        17
#define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK                         0x007E0000U

/*
* Charge Pump Integrating Current Control
*/
#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 
#define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT                        13
#define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK                         0x0001E000U

/*
* Gear Shift
*/
#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 
#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT                      12
#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK                       0x00001000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 
#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT               9
#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK                0x00000E00U

/*
* Analog Test Enable (ATOEN)
*/
#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 
#define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT                       8
#define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK                        0x00000100U

/*
* Analog Test Control
*/
#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK 
#define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT                         4
#define DDR_PHY_DX8SL0PLLCR0_ATC_MASK                          0x000000F0U

/*
* Digital Test Control
*/
#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 
#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 
#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK 
#define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT                         0
#define DDR_PHY_DX8SL0PLLCR0_DTC_MASK                          0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT              25
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK               0xFE000000U

/*
* Read Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 
#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT                     24
#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK                      0x01000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT              22
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK               0x00C00000U

/*
* Write Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 
#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT                     21
#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK                      0x00200000U

/*
* DQS Gate Extension
*/
#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 
#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL                      0x01264000
#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT                       19
#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK                        0x00180000U

/*
* Low Power PLL Power Down
*/
#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 
#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT                     18
#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK                      0x00040000U

/*
* Low Power I/O Power Down
*/
#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 
#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT                      17
#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK                       0x00020000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT              15
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK               0x00018000U

/*
* QS Counter Enable
*/
#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 
#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT                     14
#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK                      0x00004000U

/*
* Unused DQ I/O Mode
*/
#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 
#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT                      13
#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK                       0x00002000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT              10
#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK               0x00001C00U

/*
* Data Slew Rate
*/
#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 
#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL                       0x01264000
#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT                        8
#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK                         0x00000300U

/*
* DQS_N Resistor
*/
#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 
#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT                     4
#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK                      0x000000F0U

/*
* DQS Resistor
*/
#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 
#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 
#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 
#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT                      0
#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK                       0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT              24
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK               0xFF000000U

/*
* Configurable Read Data Enable
*/
#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 
#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL                      0x00141800
#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT                       23
#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK                        0x00800000U

/*
* OX Extension during Post-amble
*/
#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 
#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT                      20
#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK                       0x00700000U

/*
* OE Extension during Pre-amble
*/
#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 
#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT                      18
#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK                       0x000C0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL                0x00141800
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT                 17
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK                  0x00020000U

/*
* I/O Assisted Gate Select
*/
#undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 
#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT                        16
#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK                         0x00010000U

/*
* I/O Loopback Select
*/
#undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 
#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT                        15
#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK                         0x00008000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT              13
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK               0x00006000U

/*
* Low Power Wakeup Threshold
*/
#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 
#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT              9
#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U

/*
* Read Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 
#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT                        8
#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK                         0x00000100U

/*
* Write Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 
#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT                        7
#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK                         0x00000080U

/*
* PUB Read FIFO Bypass
*/
#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 
#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT                      6
#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK                       0x00000040U

/*
* DATX8 Receive FIFO Read Mode
*/
#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 
#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT                      4
#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK                       0x00000030U

/*
* Disables the Read FIFO Reset
*/
#undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 
#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT                      3
#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK                       0x00000008U

/*
* Read DQS Gate I/O Loopback
*/
#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 
#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT                      1
#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK                       0x00000006U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 
#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL                 0x00141800
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT                  0
#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK                   0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 
#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 
#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL                  0x00000000
#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT                   31
#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK                    0x80000000U

/*
* PVREF_DAC REFSEL range select
*/
#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 
#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 
#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 
#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL                   0x00000000
#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT                    28
#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK                     0x70000000U

/*
* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
*/
#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 
#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 
#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 
#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL                    0x00000000
#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT                     25
#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK                      0x0E000000U

/*
* DX IO Mode
*/
#undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 
#undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 
#undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK 
#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT                         22
#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK                          0x01C00000U

/*
* DX IO Transmitter Mode
*/
#undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 
#undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 
#undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK 
#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT                         11
#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK                          0x003FF800U

/*
* DX IO Receiver Mode
*/
#undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 
#undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 
#undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK 
#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT                         0
#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK                          0x000007FFU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 
#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT                 30
#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK                  0xC0000000U

/*
* Enable Clock Gating for DX ddr_clk
*/
#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 
#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 
#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT                    28
#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK                     0x30000000U

/*
* Enable Clock Gating for DX ctl_rd_clk
*/
#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 
#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 
#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT                   26
#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK                    0x0C000000U

/*
* Enable Clock Gating for DX ctl_clk
*/
#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 
#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 
#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT                   24
#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK                    0x03000000U

/*
* Selects the level to which clocks will be stalled when clock gating is e
    * nabled.
*/
#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 
#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 
#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL                      0x00019FFE
#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT                       22
#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK                        0x00C00000U

/*
* Loopback Mode
*/
#undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 
#undef DDR_PHY_DX8SL1OSC_LBMODE_MASK 
#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT                         21
#define DDR_PHY_DX8SL1OSC_LBMODE_MASK                          0x00200000U

/*
* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
*/
#undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 
#undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 
#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT                        20
#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK                         0x00100000U

/*
* Loopback DQS Gating
*/
#undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 
#undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK 
#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT                         18
#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK                          0x000C0000U

/*
* Loopback DQS Shift
*/
#undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 
#undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK 
#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT                         17
#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK                          0x00020000U

/*
* PHY High-Speed Reset
*/
#undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 
#undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK 
#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT                        16
#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK                         0x00010000U

/*
* PHY FIFO Reset
*/
#undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 
#undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK 
#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT                        15
#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK                         0x00008000U

/*
* Delay Line Test Start
*/
#undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT 
#undef DDR_PHY_DX8SL1OSC_DLTST_MASK 
#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT                          14
#define DDR_PHY_DX8SL1OSC_DLTST_MASK                           0x00004000U

/*
* Delay Line Test Mode
*/
#undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 
#undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK 
#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT                        13
#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK                         0x00002000U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 
#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 
#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT                 11
#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK                  0x00001800U

/*
* Oscillator Mode Write-Data Delay Line Select
*/
#undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 
#undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 
#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT                        9
#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK                         0x00000600U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 
#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 
#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT                   7
#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK                    0x00000180U

/*
* Oscillator Mode Write-Leveling Delay Line Select
*/
#undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 
#undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK 
#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT                         5
#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK                          0x00000060U

/*
* Oscillator Mode Division
*/
#undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 
#undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK 
#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT                         1
#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK                          0x0000001EU

/*
* Oscillator Enable
*/
#undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 
#undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 
#undef DDR_PHY_DX8SL1OSC_OSCEN_MASK 
#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT                          0
#define DDR_PHY_DX8SL1OSC_OSCEN_MASK                           0x00000001U

/*
* PLL Bypass
*/
#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 
#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT                      31
#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK                       0x80000000U

/*
* PLL Reset
*/
#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 
#define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT                      30
#define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK                       0x40000000U

/*
* PLL Power Down
*/
#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 
#define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT                       29
#define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK                        0x20000000U

/*
* Reference Stop Mode
*/
#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 
#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT                      28
#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK                       0x10000000U

/*
* PLL Frequency Select
*/
#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 
#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT                      24
#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK                       0x0F000000U

/*
* Relock Mode
*/
#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 
#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT                      23
#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK                       0x00800000U

/*
* Charge Pump Proportional Current Control
*/
#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 
#define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT                        17
#define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK                         0x007E0000U

/*
* Charge Pump Integrating Current Control
*/
#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 
#define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT                        13
#define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK                         0x0001E000U

/*
* Gear Shift
*/
#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 
#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT                      12
#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK                       0x00001000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 
#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT               9
#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK                0x00000E00U

/*
* Analog Test Enable (ATOEN)
*/
#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 
#define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT                       8
#define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK                        0x00000100U

/*
* Analog Test Control
*/
#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK 
#define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT                         4
#define DDR_PHY_DX8SL1PLLCR0_ATC_MASK                          0x000000F0U

/*
* Digital Test Control
*/
#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 
#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 
#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK 
#define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT                         0
#define DDR_PHY_DX8SL1PLLCR0_DTC_MASK                          0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT              25
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK               0xFE000000U

/*
* Read Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 
#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT                     24
#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK                      0x01000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT              22
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK               0x00C00000U

/*
* Write Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 
#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT                     21
#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK                      0x00200000U

/*
* DQS Gate Extension
*/
#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 
#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL                      0x01264000
#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT                       19
#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK                        0x00180000U

/*
* Low Power PLL Power Down
*/
#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 
#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT                     18
#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK                      0x00040000U

/*
* Low Power I/O Power Down
*/
#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 
#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT                      17
#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK                       0x00020000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT              15
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK               0x00018000U

/*
* QS Counter Enable
*/
#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 
#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT                     14
#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK                      0x00004000U

/*
* Unused DQ I/O Mode
*/
#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 
#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT                      13
#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK                       0x00002000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT              10
#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK               0x00001C00U

/*
* Data Slew Rate
*/
#undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 
#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL                       0x01264000
#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT                        8
#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK                         0x00000300U

/*
* DQS_N Resistor
*/
#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 
#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT                     4
#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK                      0x000000F0U

/*
* DQS Resistor
*/
#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 
#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 
#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 
#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT                      0
#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK                       0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT              24
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK               0xFF000000U

/*
* Configurable Read Data Enable
*/
#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 
#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL                      0x00141800
#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT                       23
#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK                        0x00800000U

/*
* OX Extension during Post-amble
*/
#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 
#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT                      20
#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK                       0x00700000U

/*
* OE Extension during Pre-amble
*/
#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 
#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT                      18
#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK                       0x000C0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL                0x00141800
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT                 17
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK                  0x00020000U

/*
* I/O Assisted Gate Select
*/
#undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 
#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT                        16
#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK                         0x00010000U

/*
* I/O Loopback Select
*/
#undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 
#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT                        15
#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK                         0x00008000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT              13
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK               0x00006000U

/*
* Low Power Wakeup Threshold
*/
#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 
#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT              9
#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U

/*
* Read Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 
#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT                        8
#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK                         0x00000100U

/*
* Write Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 
#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT                        7
#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK                         0x00000080U

/*
* PUB Read FIFO Bypass
*/
#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 
#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT                      6
#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK                       0x00000040U

/*
* DATX8 Receive FIFO Read Mode
*/
#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 
#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT                      4
#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK                       0x00000030U

/*
* Disables the Read FIFO Reset
*/
#undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 
#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT                      3
#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK                       0x00000008U

/*
* Read DQS Gate I/O Loopback
*/
#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 
#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT                      1
#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK                       0x00000006U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 
#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL                 0x00141800
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT                  0
#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK                   0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 
#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 
#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL                  0x00000000
#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT                   31
#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK                    0x80000000U

/*
* PVREF_DAC REFSEL range select
*/
#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 
#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 
#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 
#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL                   0x00000000
#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT                    28
#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK                     0x70000000U

/*
* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
*/
#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 
#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 
#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 
#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL                    0x00000000
#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT                     25
#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK                      0x0E000000U

/*
* DX IO Mode
*/
#undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 
#undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 
#undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK 
#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT                         22
#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK                          0x01C00000U

/*
* DX IO Transmitter Mode
*/
#undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 
#undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 
#undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK 
#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT                         11
#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK                          0x003FF800U

/*
* DX IO Receiver Mode
*/
#undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 
#undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 
#undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK 
#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT                         0
#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK                          0x000007FFU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 
#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT                 30
#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK                  0xC0000000U

/*
* Enable Clock Gating for DX ddr_clk
*/
#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 
#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 
#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT                    28
#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK                     0x30000000U

/*
* Enable Clock Gating for DX ctl_rd_clk
*/
#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 
#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 
#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT                   26
#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK                    0x0C000000U

/*
* Enable Clock Gating for DX ctl_clk
*/
#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 
#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 
#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT                   24
#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK                    0x03000000U

/*
* Selects the level to which clocks will be stalled when clock gating is e
    * nabled.
*/
#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 
#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 
#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL                      0x00019FFE
#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT                       22
#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK                        0x00C00000U

/*
* Loopback Mode
*/
#undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 
#undef DDR_PHY_DX8SL2OSC_LBMODE_MASK 
#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT                         21
#define DDR_PHY_DX8SL2OSC_LBMODE_MASK                          0x00200000U

/*
* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
*/
#undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 
#undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 
#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT                        20
#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK                         0x00100000U

/*
* Loopback DQS Gating
*/
#undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 
#undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK 
#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT                         18
#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK                          0x000C0000U

/*
* Loopback DQS Shift
*/
#undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 
#undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK 
#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT                         17
#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK                          0x00020000U

/*
* PHY High-Speed Reset
*/
#undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 
#undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK 
#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT                        16
#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK                         0x00010000U

/*
* PHY FIFO Reset
*/
#undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 
#undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK 
#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT                        15
#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK                         0x00008000U

/*
* Delay Line Test Start
*/
#undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT 
#undef DDR_PHY_DX8SL2OSC_DLTST_MASK 
#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT                          14
#define DDR_PHY_DX8SL2OSC_DLTST_MASK                           0x00004000U

/*
* Delay Line Test Mode
*/
#undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 
#undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK 
#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT                        13
#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK                         0x00002000U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 
#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 
#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT                 11
#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK                  0x00001800U

/*
* Oscillator Mode Write-Data Delay Line Select
*/
#undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 
#undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 
#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT                        9
#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK                         0x00000600U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 
#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 
#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT                   7
#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK                    0x00000180U

/*
* Oscillator Mode Write-Leveling Delay Line Select
*/
#undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 
#undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK 
#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT                         5
#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK                          0x00000060U

/*
* Oscillator Mode Division
*/
#undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 
#undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK 
#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT                         1
#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK                          0x0000001EU

/*
* Oscillator Enable
*/
#undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 
#undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 
#undef DDR_PHY_DX8SL2OSC_OSCEN_MASK 
#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT                          0
#define DDR_PHY_DX8SL2OSC_OSCEN_MASK                           0x00000001U

/*
* PLL Bypass
*/
#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 
#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT                      31
#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK                       0x80000000U

/*
* PLL Reset
*/
#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 
#define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT                      30
#define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK                       0x40000000U

/*
* PLL Power Down
*/
#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 
#define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT                       29
#define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK                        0x20000000U

/*
* Reference Stop Mode
*/
#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 
#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT                      28
#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK                       0x10000000U

/*
* PLL Frequency Select
*/
#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 
#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT                      24
#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK                       0x0F000000U

/*
* Relock Mode
*/
#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 
#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT                      23
#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK                       0x00800000U

/*
* Charge Pump Proportional Current Control
*/
#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 
#define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT                        17
#define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK                         0x007E0000U

/*
* Charge Pump Integrating Current Control
*/
#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 
#define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT                        13
#define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK                         0x0001E000U

/*
* Gear Shift
*/
#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 
#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT                      12
#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK                       0x00001000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 
#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT               9
#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK                0x00000E00U

/*
* Analog Test Enable (ATOEN)
*/
#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 
#define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT                       8
#define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK                        0x00000100U

/*
* Analog Test Control
*/
#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK 
#define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT                         4
#define DDR_PHY_DX8SL2PLLCR0_ATC_MASK                          0x000000F0U

/*
* Digital Test Control
*/
#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 
#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 
#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK 
#define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT                         0
#define DDR_PHY_DX8SL2PLLCR0_DTC_MASK                          0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT              25
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK               0xFE000000U

/*
* Read Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 
#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT                     24
#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK                      0x01000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT              22
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK               0x00C00000U

/*
* Write Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 
#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT                     21
#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK                      0x00200000U

/*
* DQS Gate Extension
*/
#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 
#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL                      0x01264000
#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT                       19
#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK                        0x00180000U

/*
* Low Power PLL Power Down
*/
#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 
#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT                     18
#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK                      0x00040000U

/*
* Low Power I/O Power Down
*/
#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 
#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT                      17
#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK                       0x00020000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT              15
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK               0x00018000U

/*
* QS Counter Enable
*/
#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 
#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT                     14
#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK                      0x00004000U

/*
* Unused DQ I/O Mode
*/
#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 
#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT                      13
#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK                       0x00002000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT              10
#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK               0x00001C00U

/*
* Data Slew Rate
*/
#undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 
#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL                       0x01264000
#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT                        8
#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK                         0x00000300U

/*
* DQS_N Resistor
*/
#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 
#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT                     4
#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK                      0x000000F0U

/*
* DQS Resistor
*/
#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 
#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 
#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 
#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT                      0
#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK                       0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT              24
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK               0xFF000000U

/*
* Configurable Read Data Enable
*/
#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 
#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL                      0x00141800
#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT                       23
#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK                        0x00800000U

/*
* OX Extension during Post-amble
*/
#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 
#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT                      20
#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK                       0x00700000U

/*
* OE Extension during Pre-amble
*/
#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 
#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT                      18
#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK                       0x000C0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL                0x00141800
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT                 17
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK                  0x00020000U

/*
* I/O Assisted Gate Select
*/
#undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 
#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT                        16
#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK                         0x00010000U

/*
* I/O Loopback Select
*/
#undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 
#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT                        15
#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK                         0x00008000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT              13
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK               0x00006000U

/*
* Low Power Wakeup Threshold
*/
#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 
#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT              9
#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U

/*
* Read Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 
#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT                        8
#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK                         0x00000100U

/*
* Write Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 
#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT                        7
#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK                         0x00000080U

/*
* PUB Read FIFO Bypass
*/
#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 
#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT                      6
#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK                       0x00000040U

/*
* DATX8 Receive FIFO Read Mode
*/
#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 
#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT                      4
#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK                       0x00000030U

/*
* Disables the Read FIFO Reset
*/
#undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 
#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT                      3
#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK                       0x00000008U

/*
* Read DQS Gate I/O Loopback
*/
#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 
#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT                      1
#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK                       0x00000006U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 
#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL                 0x00141800
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT                  0
#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK                   0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 
#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 
#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL                  0x00000000
#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT                   31
#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK                    0x80000000U

/*
* PVREF_DAC REFSEL range select
*/
#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 
#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 
#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 
#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL                   0x00000000
#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT                    28
#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK                     0x70000000U

/*
* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
*/
#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 
#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 
#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 
#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL                    0x00000000
#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT                     25
#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK                      0x0E000000U

/*
* DX IO Mode
*/
#undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 
#undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 
#undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK 
#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT                         22
#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK                          0x01C00000U

/*
* DX IO Transmitter Mode
*/
#undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 
#undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 
#undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK 
#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT                         11
#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK                          0x003FF800U

/*
* DX IO Receiver Mode
*/
#undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 
#undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 
#undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK 
#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT                         0
#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK                          0x000007FFU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 
#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT                 30
#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK                  0xC0000000U

/*
* Enable Clock Gating for DX ddr_clk
*/
#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 
#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 
#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT                    28
#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK                     0x30000000U

/*
* Enable Clock Gating for DX ctl_rd_clk
*/
#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 
#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 
#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT                   26
#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK                    0x0C000000U

/*
* Enable Clock Gating for DX ctl_clk
*/
#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 
#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 
#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT                   24
#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK                    0x03000000U

/*
* Selects the level to which clocks will be stalled when clock gating is e
    * nabled.
*/
#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 
#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 
#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL                      0x00019FFE
#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT                       22
#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK                        0x00C00000U

/*
* Loopback Mode
*/
#undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 
#undef DDR_PHY_DX8SL3OSC_LBMODE_MASK 
#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT                         21
#define DDR_PHY_DX8SL3OSC_LBMODE_MASK                          0x00200000U

/*
* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
*/
#undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 
#undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 
#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT                        20
#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK                         0x00100000U

/*
* Loopback DQS Gating
*/
#undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 
#undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK 
#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT                         18
#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK                          0x000C0000U

/*
* Loopback DQS Shift
*/
#undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 
#undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK 
#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT                         17
#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK                          0x00020000U

/*
* PHY High-Speed Reset
*/
#undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 
#undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK 
#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT                        16
#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK                         0x00010000U

/*
* PHY FIFO Reset
*/
#undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 
#undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK 
#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT                        15
#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK                         0x00008000U

/*
* Delay Line Test Start
*/
#undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT 
#undef DDR_PHY_DX8SL3OSC_DLTST_MASK 
#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT                          14
#define DDR_PHY_DX8SL3OSC_DLTST_MASK                           0x00004000U

/*
* Delay Line Test Mode
*/
#undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 
#undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK 
#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT                        13
#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK                         0x00002000U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 
#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 
#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT                 11
#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK                  0x00001800U

/*
* Oscillator Mode Write-Data Delay Line Select
*/
#undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 
#undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 
#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT                        9
#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK                         0x00000600U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 
#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 
#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT                   7
#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK                    0x00000180U

/*
* Oscillator Mode Write-Leveling Delay Line Select
*/
#undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 
#undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK 
#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT                         5
#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK                          0x00000060U

/*
* Oscillator Mode Division
*/
#undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 
#undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK 
#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT                         1
#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK                          0x0000001EU

/*
* Oscillator Enable
*/
#undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 
#undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 
#undef DDR_PHY_DX8SL3OSC_OSCEN_MASK 
#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT                          0
#define DDR_PHY_DX8SL3OSC_OSCEN_MASK                           0x00000001U

/*
* PLL Bypass
*/
#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 
#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT                      31
#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK                       0x80000000U

/*
* PLL Reset
*/
#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 
#define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT                      30
#define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK                       0x40000000U

/*
* PLL Power Down
*/
#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 
#define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT                       29
#define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK                        0x20000000U

/*
* Reference Stop Mode
*/
#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 
#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT                      28
#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK                       0x10000000U

/*
* PLL Frequency Select
*/
#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 
#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT                      24
#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK                       0x0F000000U

/*
* Relock Mode
*/
#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 
#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT                      23
#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK                       0x00800000U

/*
* Charge Pump Proportional Current Control
*/
#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 
#define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT                        17
#define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK                         0x007E0000U

/*
* Charge Pump Integrating Current Control
*/
#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 
#define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT                        13
#define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK                         0x0001E000U

/*
* Gear Shift
*/
#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 
#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT                      12
#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK                       0x00001000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 
#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT               9
#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK                0x00000E00U

/*
* Analog Test Enable (ATOEN)
*/
#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 
#define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT                       8
#define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK                        0x00000100U

/*
* Analog Test Control
*/
#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK 
#define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT                         4
#define DDR_PHY_DX8SL3PLLCR0_ATC_MASK                          0x000000F0U

/*
* Digital Test Control
*/
#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 
#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 
#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK 
#define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT                         0
#define DDR_PHY_DX8SL3PLLCR0_DTC_MASK                          0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT              25
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK               0xFE000000U

/*
* Read Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 
#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT                     24
#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK                      0x01000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT              22
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK               0x00C00000U

/*
* Write Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 
#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT                     21
#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK                      0x00200000U

/*
* DQS Gate Extension
*/
#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 
#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL                      0x01264000
#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT                       19
#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK                        0x00180000U

/*
* Low Power PLL Power Down
*/
#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 
#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT                     18
#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK                      0x00040000U

/*
* Low Power I/O Power Down
*/
#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 
#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT                      17
#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK                       0x00020000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT              15
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK               0x00018000U

/*
* QS Counter Enable
*/
#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 
#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT                     14
#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK                      0x00004000U

/*
* Unused DQ I/O Mode
*/
#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 
#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT                      13
#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK                       0x00002000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT              10
#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK               0x00001C00U

/*
* Data Slew Rate
*/
#undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 
#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL                       0x01264000
#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT                        8
#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK                         0x00000300U

/*
* DQS_N Resistor
*/
#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 
#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT                     4
#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK                      0x000000F0U

/*
* DQS Resistor
*/
#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 
#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 
#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 
#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT                      0
#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK                       0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT              24
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK               0xFF000000U

/*
* Configurable Read Data Enable
*/
#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 
#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL                      0x00141800
#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT                       23
#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK                        0x00800000U

/*
* OX Extension during Post-amble
*/
#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 
#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT                      20
#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK                       0x00700000U

/*
* OE Extension during Pre-amble
*/
#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 
#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT                      18
#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK                       0x000C0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL                0x00141800
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT                 17
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK                  0x00020000U

/*
* I/O Assisted Gate Select
*/
#undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 
#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT                        16
#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK                         0x00010000U

/*
* I/O Loopback Select
*/
#undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 
#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT                        15
#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK                         0x00008000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT              13
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK               0x00006000U

/*
* Low Power Wakeup Threshold
*/
#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 
#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT              9
#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U

/*
* Read Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 
#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT                        8
#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK                         0x00000100U

/*
* Write Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 
#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT                        7
#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK                         0x00000080U

/*
* PUB Read FIFO Bypass
*/
#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 
#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT                      6
#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK                       0x00000040U

/*
* DATX8 Receive FIFO Read Mode
*/
#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 
#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT                      4
#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK                       0x00000030U

/*
* Disables the Read FIFO Reset
*/
#undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 
#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT                      3
#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK                       0x00000008U

/*
* Read DQS Gate I/O Loopback
*/
#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 
#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT                      1
#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK                       0x00000006U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 
#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL                 0x00141800
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT                  0
#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK                   0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 
#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 
#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL                  0x00000000
#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT                   31
#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK                    0x80000000U

/*
* PVREF_DAC REFSEL range select
*/
#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 
#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 
#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 
#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL                   0x00000000
#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT                    28
#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK                     0x70000000U

/*
* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
*/
#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 
#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 
#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 
#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL                    0x00000000
#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT                     25
#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK                      0x0E000000U

/*
* DX IO Mode
*/
#undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 
#undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 
#undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK 
#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT                         22
#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK                          0x01C00000U

/*
* DX IO Transmitter Mode
*/
#undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 
#undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 
#undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK 
#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT                         11
#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK                          0x003FF800U

/*
* DX IO Receiver Mode
*/
#undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 
#undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 
#undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK 
#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT                         0
#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK                          0x000007FFU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 
#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 
#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT                 30
#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK                  0xC0000000U

/*
* Enable Clock Gating for DX ddr_clk
*/
#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 
#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 
#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT                    28
#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK                     0x30000000U

/*
* Enable Clock Gating for DX ctl_rd_clk
*/
#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 
#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 
#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT                   26
#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK                    0x0C000000U

/*
* Enable Clock Gating for DX ctl_clk
*/
#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 
#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 
#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT                   24
#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK                    0x03000000U

/*
* Selects the level to which clocks will be stalled when clock gating is e
    * nabled.
*/
#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 
#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 
#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL                      0x00019FFE
#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT                       22
#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK                        0x00C00000U

/*
* Loopback Mode
*/
#undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 
#undef DDR_PHY_DX8SL4OSC_LBMODE_MASK 
#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT                         21
#define DDR_PHY_DX8SL4OSC_LBMODE_MASK                          0x00200000U

/*
* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
*/
#undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 
#undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 
#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT                        20
#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK                         0x00100000U

/*
* Loopback DQS Gating
*/
#undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 
#undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK 
#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT                         18
#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK                          0x000C0000U

/*
* Loopback DQS Shift
*/
#undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 
#undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK 
#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT                         17
#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK                          0x00020000U

/*
* PHY High-Speed Reset
*/
#undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 
#undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK 
#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT                        16
#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK                         0x00010000U

/*
* PHY FIFO Reset
*/
#undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 
#undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK 
#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT                        15
#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK                         0x00008000U

/*
* Delay Line Test Start
*/
#undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT 
#undef DDR_PHY_DX8SL4OSC_DLTST_MASK 
#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT                          14
#define DDR_PHY_DX8SL4OSC_DLTST_MASK                           0x00004000U

/*
* Delay Line Test Mode
*/
#undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 
#undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK 
#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT                        13
#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK                         0x00002000U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 
#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 
#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL                0x00019FFE
#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT                 11
#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK                  0x00001800U

/*
* Oscillator Mode Write-Data Delay Line Select
*/
#undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 
#undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 
#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL                       0x00019FFE
#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT                        9
#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK                         0x00000600U

/*
* Reserved. Caution, do not write to this register field.
*/
#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 
#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 
#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT                   7
#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK                    0x00000180U

/*
* Oscillator Mode Write-Leveling Delay Line Select
*/
#undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 
#undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK 
#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT                         5
#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK                          0x00000060U

/*
* Oscillator Mode Division
*/
#undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 
#undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK 
#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL                        0x00019FFE
#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT                         1
#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK                          0x0000001EU

/*
* Oscillator Enable
*/
#undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 
#undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 
#undef DDR_PHY_DX8SL4OSC_OSCEN_MASK 
#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL                         0x00019FFE
#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT                          0
#define DDR_PHY_DX8SL4OSC_OSCEN_MASK                           0x00000001U

/*
* PLL Bypass
*/
#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 
#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT                      31
#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK                       0x80000000U

/*
* PLL Reset
*/
#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 
#define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT                      30
#define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK                       0x40000000U

/*
* PLL Power Down
*/
#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 
#define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT                       29
#define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK                        0x20000000U

/*
* Reference Stop Mode
*/
#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 
#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT                      28
#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK                       0x10000000U

/*
* PLL Frequency Select
*/
#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 
#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT                      24
#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK                       0x0F000000U

/*
* Relock Mode
*/
#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 
#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT                      23
#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK                       0x00800000U

/*
* Charge Pump Proportional Current Control
*/
#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 
#define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT                        17
#define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK                         0x007E0000U

/*
* Charge Pump Integrating Current Control
*/
#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 
#define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL                       0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT                        13
#define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK                         0x0001E000U

/*
* Gear Shift
*/
#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 
#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL                     0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT                      12
#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK                       0x00001000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 
#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT               9
#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK                0x00000E00U

/*
* Analog Test Enable (ATOEN)
*/
#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 
#define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL                      0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT                       8
#define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK                        0x00000100U

/*
* Analog Test Control
*/
#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK 
#define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT                         4
#define DDR_PHY_DX8SL4PLLCR0_ATC_MASK                          0x000000F0U

/*
* Digital Test Control
*/
#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 
#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 
#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK 
#define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL                        0x001C0000
#define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT                         0
#define DDR_PHY_DX8SL4PLLCR0_DTC_MASK                          0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT              25
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK               0xFE000000U

/*
* Read Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 
#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT                     24
#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK                      0x01000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT              22
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK               0x00C00000U

/*
* Write Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 
#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT                     21
#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK                      0x00200000U

/*
* DQS Gate Extension
*/
#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 
#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL                      0x01264000
#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT                       19
#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK                        0x00180000U

/*
* Low Power PLL Power Down
*/
#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 
#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT                     18
#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK                      0x00040000U

/*
* Low Power I/O Power Down
*/
#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 
#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT                      17
#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK                       0x00020000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT              15
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK               0x00018000U

/*
* QS Counter Enable
*/
#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 
#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT                     14
#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK                      0x00004000U

/*
* Unused DQ I/O Mode
*/
#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 
#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT                      13
#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK                       0x00002000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT              10
#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK               0x00001C00U

/*
* Data Slew Rate
*/
#undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 
#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL                       0x01264000
#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT                        8
#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK                         0x00000300U

/*
* DQS_N Resistor
*/
#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 
#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL                    0x01264000
#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT                     4
#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK                      0x000000F0U

/*
* DQS Resistor
*/
#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 
#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 
#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 
#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL                     0x01264000
#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT                      0
#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK                       0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT              24
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK               0xFF000000U

/*
* Configurable Read Data Enable
*/
#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 
#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL                      0x00141800
#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT                       23
#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK                        0x00800000U

/*
* OX Extension during Post-amble
*/
#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 
#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT                      20
#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK                       0x00700000U

/*
* OE Extension during Pre-amble
*/
#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 
#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT                      18
#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK                       0x000C0000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL                0x00141800
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT                 17
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK                  0x00020000U

/*
* I/O Assisted Gate Select
*/
#undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 
#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT                        16
#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK                         0x00010000U

/*
* I/O Loopback Select
*/
#undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 
#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT                        15
#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK                         0x00008000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT              13
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK               0x00006000U

/*
* Low Power Wakeup Threshold
*/
#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 
#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT              9
#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U

/*
* Read Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 
#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT                        8
#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK                         0x00000100U

/*
* Write Data Bus Inversion Enable
*/
#undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 
#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL                       0x00141800
#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT                        7
#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK                         0x00000080U

/*
* PUB Read FIFO Bypass
*/
#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 
#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT                      6
#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK                       0x00000040U

/*
* DATX8 Receive FIFO Read Mode
*/
#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 
#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT                      4
#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK                       0x00000030U

/*
* Disables the Read FIFO Reset
*/
#undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 
#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT                      3
#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK                       0x00000008U

/*
* Read DQS Gate I/O Loopback
*/
#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 
#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL                     0x00141800
#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT                      1
#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK                       0x00000006U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 
#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL                 0x00141800
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT                  0
#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK                   0x00000001U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 
#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 
#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 
#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL                  0x00000000
#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT                   31
#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK                    0x80000000U

/*
* PVREF_DAC REFSEL range select
*/
#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 
#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 
#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 
#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL                   0x00000000
#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT                    28
#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK                     0x70000000U

/*
* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
*/
#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 
#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 
#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 
#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL                    0x00000000
#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT                     25
#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK                      0x0E000000U

/*
* DX IO Mode
*/
#undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 
#undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 
#undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK 
#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT                         22
#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK                          0x01C00000U

/*
* DX IO Transmitter Mode
*/
#undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 
#undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 
#undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK 
#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT                         11
#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK                          0x003FF800U

/*
* DX IO Receiver Mode
*/
#undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 
#undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 
#undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK 
#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL                        0x00000000
#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT                         0
#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK                          0x000007FFU

/*
* PLL Bypass
*/
#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK 
#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT                      31
#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK                       0x80000000U

/*
* PLL Reset
*/
#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK 
#define DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT                      30
#define DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK                       0x40000000U

/*
* PLL Power Down
*/
#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK 
#define DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL                      0x00000000
#define DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT                       29
#define DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK                        0x20000000U

/*
* Reference Stop Mode
*/
#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK 
#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT                      28
#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK                       0x10000000U

/*
* PLL Frequency Select
*/
#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK 
#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT                      24
#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK                       0x0F000000U

/*
* Relock Mode
*/
#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK 
#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT                      23
#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK                       0x00800000U

/*
* Charge Pump Proportional Current Control
*/
#undef DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_CPPC_MASK 
#define DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL                       0x00000000
#define DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT                        17
#define DDR_PHY_DX8SLBPLLCR0_CPPC_MASK                         0x007E0000U

/*
* Charge Pump Integrating Current Control
*/
#undef DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_CPIC_MASK 
#define DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL                       0x00000000
#define DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT                        13
#define DDR_PHY_DX8SLBPLLCR0_CPIC_MASK                         0x0001E000U

/*
* Gear Shift
*/
#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK 
#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT                      12
#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK                       0x00001000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK 
#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL              0x00000000
#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT               9
#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK                0x00000E00U

/*
* Analog Test Enable (ATOEN)
*/
#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK 
#define DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL                      0x00000000
#define DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT                       8
#define DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK                        0x00000100U

/*
* Analog Test Control
*/
#undef DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_ATC_MASK 
#define DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL                        0x00000000
#define DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT                         4
#define DDR_PHY_DX8SLBPLLCR0_ATC_MASK                          0x000000F0U

/*
* Digital Test Control
*/
#undef DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL 
#undef DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT 
#undef DDR_PHY_DX8SLBPLLCR0_DTC_MASK 
#define DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL                        0x00000000
#define DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT                         0
#define DDR_PHY_DX8SLBPLLCR0_DTC_MASK                          0x0000000FU

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL             0x00000000
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT              25
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK               0xFE000000U

/*
* Read Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 
#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL                    0x00000000
#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT                     24
#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK                      0x01000000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL             0x00000000
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT              22
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK               0x00C00000U

/*
* Write Path Rise-to-Rise Mode
*/
#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 
#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL                    0x00000000
#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT                     21
#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK                      0x00200000U

/*
* DQS Gate Extension
*/
#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 
#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL                      0x00000000
#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT                       19
#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK                        0x00180000U

/*
* Low Power PLL Power Down
*/
#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 
#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL                    0x00000000
#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT                     18
#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK                      0x00040000U

/*
* Low Power I/O Power Down
*/
#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 
#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT                      17
#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK                       0x00020000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL             0x00000000
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT              15
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK               0x00018000U

/*
* QS Counter Enable
*/
#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 
#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL                    0x00000000
#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT                     14
#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK                      0x00004000U

/*
* Unused DQ I/O Mode
*/
#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 
#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT                      13
#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK                       0x00002000U

/*
* Reserved. Return zeroes on reads.
*/
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL             0x00000000
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT              10
#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK               0x00001C00U

/*
* Data Slew Rate
*/
#undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 
#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL                       0x00000000
#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT                        8
#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK                         0x00000300U

/*
* DQS# Resistor
*/
#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 
#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL                    0x00000000
#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT                     4
#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK                      0x000000F0U

/*
* DQS Resistor
*/
#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 
#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 
#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 
#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL                     0x00000000
#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT                      0
#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK                       0x0000000FU
#undef IOU_SLCR_MIO_PIN_0_OFFSET 
#define IOU_SLCR_MIO_PIN_0_OFFSET                                                  0XFF180000
#undef IOU_SLCR_MIO_PIN_1_OFFSET 
#define IOU_SLCR_MIO_PIN_1_OFFSET                                                  0XFF180004
#undef IOU_SLCR_MIO_PIN_2_OFFSET 
#define IOU_SLCR_MIO_PIN_2_OFFSET                                                  0XFF180008
#undef IOU_SLCR_MIO_PIN_3_OFFSET 
#define IOU_SLCR_MIO_PIN_3_OFFSET                                                  0XFF18000C
#undef IOU_SLCR_MIO_PIN_4_OFFSET 
#define IOU_SLCR_MIO_PIN_4_OFFSET                                                  0XFF180010
#undef IOU_SLCR_MIO_PIN_5_OFFSET 
#define IOU_SLCR_MIO_PIN_5_OFFSET                                                  0XFF180014
#undef IOU_SLCR_MIO_PIN_6_OFFSET 
#define IOU_SLCR_MIO_PIN_6_OFFSET                                                  0XFF180018
#undef IOU_SLCR_MIO_PIN_7_OFFSET 
#define IOU_SLCR_MIO_PIN_7_OFFSET                                                  0XFF18001C
#undef IOU_SLCR_MIO_PIN_8_OFFSET 
#define IOU_SLCR_MIO_PIN_8_OFFSET                                                  0XFF180020
#undef IOU_SLCR_MIO_PIN_9_OFFSET 
#define IOU_SLCR_MIO_PIN_9_OFFSET                                                  0XFF180024
#undef IOU_SLCR_MIO_PIN_10_OFFSET 
#define IOU_SLCR_MIO_PIN_10_OFFSET                                                 0XFF180028
#undef IOU_SLCR_MIO_PIN_11_OFFSET 
#define IOU_SLCR_MIO_PIN_11_OFFSET                                                 0XFF18002C
#undef IOU_SLCR_MIO_PIN_12_OFFSET 
#define IOU_SLCR_MIO_PIN_12_OFFSET                                                 0XFF180030
#undef IOU_SLCR_MIO_PIN_13_OFFSET 
#define IOU_SLCR_MIO_PIN_13_OFFSET                                                 0XFF180034
#undef IOU_SLCR_MIO_PIN_14_OFFSET 
#define IOU_SLCR_MIO_PIN_14_OFFSET                                                 0XFF180038
#undef IOU_SLCR_MIO_PIN_15_OFFSET 
#define IOU_SLCR_MIO_PIN_15_OFFSET                                                 0XFF18003C
#undef IOU_SLCR_MIO_PIN_16_OFFSET 
#define IOU_SLCR_MIO_PIN_16_OFFSET                                                 0XFF180040
#undef IOU_SLCR_MIO_PIN_17_OFFSET 
#define IOU_SLCR_MIO_PIN_17_OFFSET                                                 0XFF180044
#undef IOU_SLCR_MIO_PIN_18_OFFSET 
#define IOU_SLCR_MIO_PIN_18_OFFSET                                                 0XFF180048
#undef IOU_SLCR_MIO_PIN_19_OFFSET 
#define IOU_SLCR_MIO_PIN_19_OFFSET                                                 0XFF18004C
#undef IOU_SLCR_MIO_PIN_20_OFFSET 
#define IOU_SLCR_MIO_PIN_20_OFFSET                                                 0XFF180050
#undef IOU_SLCR_MIO_PIN_21_OFFSET 
#define IOU_SLCR_MIO_PIN_21_OFFSET                                                 0XFF180054
#undef IOU_SLCR_MIO_PIN_22_OFFSET 
#define IOU_SLCR_MIO_PIN_22_OFFSET                                                 0XFF180058
#undef IOU_SLCR_MIO_PIN_23_OFFSET 
#define IOU_SLCR_MIO_PIN_23_OFFSET                                                 0XFF18005C
#undef IOU_SLCR_MIO_PIN_24_OFFSET 
#define IOU_SLCR_MIO_PIN_24_OFFSET                                                 0XFF180060
#undef IOU_SLCR_MIO_PIN_25_OFFSET 
#define IOU_SLCR_MIO_PIN_25_OFFSET                                                 0XFF180064
#undef IOU_SLCR_MIO_PIN_26_OFFSET 
#define IOU_SLCR_MIO_PIN_26_OFFSET                                                 0XFF180068
#undef IOU_SLCR_MIO_PIN_27_OFFSET 
#define IOU_SLCR_MIO_PIN_27_OFFSET                                                 0XFF18006C
#undef IOU_SLCR_MIO_PIN_28_OFFSET 
#define IOU_SLCR_MIO_PIN_28_OFFSET                                                 0XFF180070
#undef IOU_SLCR_MIO_PIN_29_OFFSET 
#define IOU_SLCR_MIO_PIN_29_OFFSET                                                 0XFF180074
#undef IOU_SLCR_MIO_PIN_30_OFFSET 
#define IOU_SLCR_MIO_PIN_30_OFFSET                                                 0XFF180078
#undef IOU_SLCR_MIO_PIN_31_OFFSET 
#define IOU_SLCR_MIO_PIN_31_OFFSET                                                 0XFF18007C
#undef IOU_SLCR_MIO_PIN_32_OFFSET 
#define IOU_SLCR_MIO_PIN_32_OFFSET                                                 0XFF180080
#undef IOU_SLCR_MIO_PIN_33_OFFSET 
#define IOU_SLCR_MIO_PIN_33_OFFSET                                                 0XFF180084
#undef IOU_SLCR_MIO_PIN_34_OFFSET 
#define IOU_SLCR_MIO_PIN_34_OFFSET                                                 0XFF180088
#undef IOU_SLCR_MIO_PIN_35_OFFSET 
#define IOU_SLCR_MIO_PIN_35_OFFSET                                                 0XFF18008C
#undef IOU_SLCR_MIO_PIN_36_OFFSET 
#define IOU_SLCR_MIO_PIN_36_OFFSET                                                 0XFF180090
#undef IOU_SLCR_MIO_PIN_37_OFFSET 
#define IOU_SLCR_MIO_PIN_37_OFFSET                                                 0XFF180094
#undef IOU_SLCR_MIO_PIN_38_OFFSET 
#define IOU_SLCR_MIO_PIN_38_OFFSET                                                 0XFF180098
#undef IOU_SLCR_MIO_PIN_39_OFFSET 
#define IOU_SLCR_MIO_PIN_39_OFFSET                                                 0XFF18009C
#undef IOU_SLCR_MIO_PIN_40_OFFSET 
#define IOU_SLCR_MIO_PIN_40_OFFSET                                                 0XFF1800A0
#undef IOU_SLCR_MIO_PIN_41_OFFSET 
#define IOU_SLCR_MIO_PIN_41_OFFSET                                                 0XFF1800A4
#undef IOU_SLCR_MIO_PIN_42_OFFSET 
#define IOU_SLCR_MIO_PIN_42_OFFSET                                                 0XFF1800A8
#undef IOU_SLCR_MIO_PIN_43_OFFSET 
#define IOU_SLCR_MIO_PIN_43_OFFSET                                                 0XFF1800AC
#undef IOU_SLCR_MIO_PIN_44_OFFSET 
#define IOU_SLCR_MIO_PIN_44_OFFSET                                                 0XFF1800B0
#undef IOU_SLCR_MIO_PIN_45_OFFSET 
#define IOU_SLCR_MIO_PIN_45_OFFSET                                                 0XFF1800B4
#undef IOU_SLCR_MIO_PIN_46_OFFSET 
#define IOU_SLCR_MIO_PIN_46_OFFSET                                                 0XFF1800B8
#undef IOU_SLCR_MIO_PIN_47_OFFSET 
#define IOU_SLCR_MIO_PIN_47_OFFSET                                                 0XFF1800BC
#undef IOU_SLCR_MIO_PIN_48_OFFSET 
#define IOU_SLCR_MIO_PIN_48_OFFSET                                                 0XFF1800C0
#undef IOU_SLCR_MIO_PIN_49_OFFSET 
#define IOU_SLCR_MIO_PIN_49_OFFSET                                                 0XFF1800C4
#undef IOU_SLCR_MIO_PIN_50_OFFSET 
#define IOU_SLCR_MIO_PIN_50_OFFSET                                                 0XFF1800C8
#undef IOU_SLCR_MIO_PIN_51_OFFSET 
#define IOU_SLCR_MIO_PIN_51_OFFSET                                                 0XFF1800CC
#undef IOU_SLCR_MIO_PIN_52_OFFSET 
#define IOU_SLCR_MIO_PIN_52_OFFSET                                                 0XFF1800D0
#undef IOU_SLCR_MIO_PIN_53_OFFSET 
#define IOU_SLCR_MIO_PIN_53_OFFSET                                                 0XFF1800D4
#undef IOU_SLCR_MIO_PIN_54_OFFSET 
#define IOU_SLCR_MIO_PIN_54_OFFSET                                                 0XFF1800D8
#undef IOU_SLCR_MIO_PIN_55_OFFSET 
#define IOU_SLCR_MIO_PIN_55_OFFSET                                                 0XFF1800DC
#undef IOU_SLCR_MIO_PIN_56_OFFSET 
#define IOU_SLCR_MIO_PIN_56_OFFSET                                                 0XFF1800E0
#undef IOU_SLCR_MIO_PIN_57_OFFSET 
#define IOU_SLCR_MIO_PIN_57_OFFSET                                                 0XFF1800E4
#undef IOU_SLCR_MIO_PIN_58_OFFSET 
#define IOU_SLCR_MIO_PIN_58_OFFSET                                                 0XFF1800E8
#undef IOU_SLCR_MIO_PIN_59_OFFSET 
#define IOU_SLCR_MIO_PIN_59_OFFSET                                                 0XFF1800EC
#undef IOU_SLCR_MIO_PIN_60_OFFSET 
#define IOU_SLCR_MIO_PIN_60_OFFSET                                                 0XFF1800F0
#undef IOU_SLCR_MIO_PIN_61_OFFSET 
#define IOU_SLCR_MIO_PIN_61_OFFSET                                                 0XFF1800F4
#undef IOU_SLCR_MIO_PIN_62_OFFSET 
#define IOU_SLCR_MIO_PIN_62_OFFSET                                                 0XFF1800F8
#undef IOU_SLCR_MIO_PIN_63_OFFSET 
#define IOU_SLCR_MIO_PIN_63_OFFSET                                                 0XFF1800FC
#undef IOU_SLCR_MIO_PIN_64_OFFSET 
#define IOU_SLCR_MIO_PIN_64_OFFSET                                                 0XFF180100
#undef IOU_SLCR_MIO_PIN_65_OFFSET 
#define IOU_SLCR_MIO_PIN_65_OFFSET                                                 0XFF180104
#undef IOU_SLCR_MIO_PIN_66_OFFSET 
#define IOU_SLCR_MIO_PIN_66_OFFSET                                                 0XFF180108
#undef IOU_SLCR_MIO_PIN_67_OFFSET 
#define IOU_SLCR_MIO_PIN_67_OFFSET                                                 0XFF18010C
#undef IOU_SLCR_MIO_PIN_68_OFFSET 
#define IOU_SLCR_MIO_PIN_68_OFFSET                                                 0XFF180110
#undef IOU_SLCR_MIO_PIN_69_OFFSET 
#define IOU_SLCR_MIO_PIN_69_OFFSET                                                 0XFF180114
#undef IOU_SLCR_MIO_PIN_70_OFFSET 
#define IOU_SLCR_MIO_PIN_70_OFFSET                                                 0XFF180118
#undef IOU_SLCR_MIO_PIN_71_OFFSET 
#define IOU_SLCR_MIO_PIN_71_OFFSET                                                 0XFF18011C
#undef IOU_SLCR_MIO_PIN_72_OFFSET 
#define IOU_SLCR_MIO_PIN_72_OFFSET                                                 0XFF180120
#undef IOU_SLCR_MIO_PIN_73_OFFSET 
#define IOU_SLCR_MIO_PIN_73_OFFSET                                                 0XFF180124
#undef IOU_SLCR_MIO_PIN_74_OFFSET 
#define IOU_SLCR_MIO_PIN_74_OFFSET                                                 0XFF180128
#undef IOU_SLCR_MIO_PIN_75_OFFSET 
#define IOU_SLCR_MIO_PIN_75_OFFSET                                                 0XFF18012C
#undef IOU_SLCR_MIO_PIN_76_OFFSET 
#define IOU_SLCR_MIO_PIN_76_OFFSET                                                 0XFF180130
#undef IOU_SLCR_MIO_PIN_77_OFFSET 
#define IOU_SLCR_MIO_PIN_77_OFFSET                                                 0XFF180134
#undef IOU_SLCR_MIO_MST_TRI0_OFFSET 
#define IOU_SLCR_MIO_MST_TRI0_OFFSET                                               0XFF180204
#undef IOU_SLCR_MIO_MST_TRI1_OFFSET 
#define IOU_SLCR_MIO_MST_TRI1_OFFSET                                               0XFF180208
#undef IOU_SLCR_MIO_MST_TRI2_OFFSET 
#define IOU_SLCR_MIO_MST_TRI2_OFFSET                                               0XFF18020C
#undef IOU_SLCR_BANK0_CTRL0_OFFSET 
#define IOU_SLCR_BANK0_CTRL0_OFFSET                                                0XFF180138
#undef IOU_SLCR_BANK0_CTRL1_OFFSET 
#define IOU_SLCR_BANK0_CTRL1_OFFSET                                                0XFF18013C
#undef IOU_SLCR_BANK0_CTRL3_OFFSET 
#define IOU_SLCR_BANK0_CTRL3_OFFSET                                                0XFF180140
#undef IOU_SLCR_BANK0_CTRL4_OFFSET 
#define IOU_SLCR_BANK0_CTRL4_OFFSET                                                0XFF180144
#undef IOU_SLCR_BANK0_CTRL5_OFFSET 
#define IOU_SLCR_BANK0_CTRL5_OFFSET                                                0XFF180148
#undef IOU_SLCR_BANK0_CTRL6_OFFSET 
#define IOU_SLCR_BANK0_CTRL6_OFFSET                                                0XFF18014C
#undef IOU_SLCR_BANK1_CTRL0_OFFSET 
#define IOU_SLCR_BANK1_CTRL0_OFFSET                                                0XFF180154
#undef IOU_SLCR_BANK1_CTRL1_OFFSET 
#define IOU_SLCR_BANK1_CTRL1_OFFSET                                                0XFF180158
#undef IOU_SLCR_BANK1_CTRL3_OFFSET 
#define IOU_SLCR_BANK1_CTRL3_OFFSET                                                0XFF18015C
#undef IOU_SLCR_BANK1_CTRL4_OFFSET 
#define IOU_SLCR_BANK1_CTRL4_OFFSET                                                0XFF180160
#undef IOU_SLCR_BANK1_CTRL5_OFFSET 
#define IOU_SLCR_BANK1_CTRL5_OFFSET                                                0XFF180164
#undef IOU_SLCR_BANK1_CTRL6_OFFSET 
#define IOU_SLCR_BANK1_CTRL6_OFFSET                                                0XFF180168
#undef IOU_SLCR_BANK2_CTRL0_OFFSET 
#define IOU_SLCR_BANK2_CTRL0_OFFSET                                                0XFF180170
#undef IOU_SLCR_BANK2_CTRL1_OFFSET 
#define IOU_SLCR_BANK2_CTRL1_OFFSET                                                0XFF180174
#undef IOU_SLCR_BANK2_CTRL3_OFFSET 
#define IOU_SLCR_BANK2_CTRL3_OFFSET                                                0XFF180178
#undef IOU_SLCR_BANK2_CTRL4_OFFSET 
#define IOU_SLCR_BANK2_CTRL4_OFFSET                                                0XFF18017C
#undef IOU_SLCR_BANK2_CTRL5_OFFSET 
#define IOU_SLCR_BANK2_CTRL5_OFFSET                                                0XFF180180
#undef IOU_SLCR_BANK2_CTRL6_OFFSET 
#define IOU_SLCR_BANK2_CTRL6_OFFSET                                                0XFF180184
#undef IOU_SLCR_MIO_LOOPBACK_OFFSET 
#define IOU_SLCR_MIO_LOOPBACK_OFFSET                                               0XFF180200

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out-
    *  (QSPI Clock)
*/
#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy
    * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
    * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
    *  TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
    * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out
    * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
    * lk- (Trace Port Clock)
*/
#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q
    * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
*/
#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_
    * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
    * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
    * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou
    * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
    * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
    * Signal)
*/
#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI
    *  Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
*/
#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_
    * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
    * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
    *  TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I
    * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
    * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI
    *  Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
*/
#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy
    * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
    * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
    *  TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
    * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out-
    *  (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
    * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (
    * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
*/
#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy
    * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
    * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
    * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
    * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc
    * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
    * utput, tracedq[2]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out-
    *  (QSPI Slave Select)
*/
#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_
    * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
    * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
    * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
    * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC
    *  Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
    *  trace, Output, tracedq[3]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l
    * pbk- (QSPI Clock to be fed-back)
*/
#undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_
    * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
    * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
    * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s
    * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT
    * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
    * Output, tracedq[4]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_
    * upper- (QSPI Slave Select upper)
*/
#undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy
    * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
    * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
    * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma
    * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua
    * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t
    * racedq[5]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0
    * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D
    * atabus)
*/
#undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy
    * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
    * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
    * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste
    * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_
    * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra
    * ce Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1
    * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D
    * atabus)
*/
#undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT                        1
#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK                         0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
    * ND chip enable)
*/
#undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT                        2
#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK                         0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9
    * ]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT                        3
#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK                         0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g
    * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_
    * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
    * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
    * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S
    * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3,
    *  Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA
    * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data
    * bus)
*/
#undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL                       0x00000000
#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT                        5
#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK                         0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2
    * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D
    * atabus)
*/
#undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
    * AND Ready/Busy)
*/
#undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[
    * 10]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
    * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
    * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
    * t, tracedq[8]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3
    * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D
    * atabus)
*/
#undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
    * AND Ready/Busy)
*/
#undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[
    * 11]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
    * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
    * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
    * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_
    * upper- (QSPI Upper Clock)
*/
#undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
    * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
*/
#undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input
    * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[
    * 12]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT
    * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_
    * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O
    * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace
    * dq[10]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA
    * ND chip enable)
*/
#undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t
    * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output,
    *  test_scan_out[13]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA
    * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1,
    * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR
    * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data
    * bus)
*/
#undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND
    *  Command Latch Enable)
*/
#undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t
    * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output,
    *  test_scan_out[14]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT
    * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0,
    *  Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver
    * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND
    *  Address Latch Enable)
*/
#undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t
    * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output,
    *  test_scan_out[15]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT
    * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp
    * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou
    * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria
    * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (
    * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)
*/
#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t
    * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output,
    *  test_scan_out[16]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
    * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
    * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
    *  Output, tracedq[14]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (
    * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)
*/
#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t
    * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output,
    *  test_scan_out[17]- (Test Scan Port) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
    * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
    * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
    * 7= trace, Output, tracedq[15]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (
    * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)
*/
#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t
    * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output,
    *  test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
    *  Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
    * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
    * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (
    * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)
*/
#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t
    * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output,
    *  test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
    *  Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
    * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6=
    * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (
    * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)
*/
#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t
    * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output,
    *  test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
    *  Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
    * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua
    * 1_txd- (UART transmitter serial output) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (
    * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)
*/
#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
    * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes
    * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t
    * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E
    * xt Tamper)
*/
#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
    *  Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc
    * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (
    * UART receiver serial input) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN
    * D Write Enable)
*/
#undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
    * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) =
    *  test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c
    * su_ext_tamper- (CSU Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
    *  spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
    * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
    * sed
*/
#undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (
    * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)
*/
#undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
    * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po
    * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp
    * ut, csu_ext_tamper- (CSU Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
    * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
    * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
    * tput) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (
    * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)
*/
#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
    * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test
    *  Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3=
    * csu, Input, csu_ext_tamper- (CSU Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T
    * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N
    * ot Used
*/
#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN
    * D Read Enable)
*/
#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
    * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]-
    * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port
    * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0=
    * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou
    * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
    * put) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
    * clk- (TX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA
    * ND chip enable)
*/
#undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU
    *  GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca
    * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta
    * mper- (CSU Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_
    * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
    * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
    * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl
    * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
    * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
    * Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
    * [0]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
    * AND Ready/Busy)
*/
#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU
    *  GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca
    * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
    * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
*/
#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy
    * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
    * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
    *  TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
    * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
    * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
    * atabus)
*/
#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
    * [1]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
    * AND Ready/Busy)
*/
#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU
    *  GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca
    * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
    * lug_detect- (Dp Aux Hot Plug)
*/
#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy
    * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
    * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
    * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
    * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
    * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
    * [2]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
    * PCIE Reset signal)
*/
#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU
    *  GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca
    * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
    * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
*/
#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_
    * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
    * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
    * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output,
    *  spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
    * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
    * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
    * [3]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
    * PCIE Reset signal)
*/
#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU
    *  GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca
    * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
    * lug_detect- (Dp Aux Hot Plug)
*/
#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_
    * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
    * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
    * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0
    * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock
    * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output,
    *  tracedq[8]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_
    * ctl- (TX RGMII control)
*/
#undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
    * PCIE Reset signal)
*/
#undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU
    *  GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca
    * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta
    * mper- (CSU Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy
    * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
    * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
    * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
    *  spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT
    * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp
    * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
    * lk- (RX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA
    * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
*/
#undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM
    * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc
    * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t
    * amper- (CSU Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy
    * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
    * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
    * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
    * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T
    * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t
    * race, Output, tracedq[10]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
    * 0]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
    * PCIE Reset signal)
*/
#undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM
    * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc
    * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t
    * amper- (CSU Ext Tamper)
*/
#undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_
    * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
    * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
    * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas
    * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1
    * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq
    * [11]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
    * 1]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
    * PCIE Reset signal)
*/
#undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM
    * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc
    * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_
    * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
*/
#undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_
    * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
    * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat
    * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master
    *  Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx
    * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po
    * rt Databus)
*/
#undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
    * 2]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
    * PCIE Reset signal)
*/
#undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM
    * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc
    * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_
    * plug_detect- (Dp Aux Hot Plug)
*/
#undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g
    * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy
    * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
    * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (
    * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
    * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2
    * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (
    * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po
    * rt Databus)
*/
#undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[
    * 3]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
    * PCIE Reset signal)
*/
#undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM
    * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc
    * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_
    * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
*/
#undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
    * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
    * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
    *  Output, tracedq[14]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c
    * tl- (RX RGMII control )
*/
#undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
    * PCIE Reset signal)
*/
#undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM
    * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc
    * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_
    * plug_detect- (Dp Aux Hot Plug)
*/
#undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
    * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
    * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
    * 7= trace, Output, tracedq[15]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
    * clk- (TX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
    * (SDSDIO clock) 2= Not Used 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA
    * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s
    * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In
    * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
    * (Trace Port Clock)
*/
#undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
    * [0]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
    * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b
    * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT
    * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0,
    *  Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U
    * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
    * Control Signal)
*/
#undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
    * [1]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
    * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1
    * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[
    * 5]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ
    * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3
    * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi
    * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
    * [2]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[6]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA
    * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu
    * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out
    * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp
    * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd
    * [3]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[7]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp
    * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
    * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
    * t, tracedq[2]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_
    * ctl- (TX RGMII control)
*/
#undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
    * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal)
    * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (
    * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
    * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
    * lk- (RX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
    * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4
    * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in-
    * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
    *  Not Used
*/
#undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
    * 0]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
    * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M
    * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u
    * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
    * 1]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[0]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast
    * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_
    * rxd- (UART receiver serial input) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
    * 2]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[1]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste
    * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt
    * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
    *  (UART transmitter serial output) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
    * 3]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[2]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s
    * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl
    * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us
    * ed
*/
#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
    * tl- (RX RGMII control )
*/
#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
    * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd
    * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4
    * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T
    * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
    * 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
    *  (TSU clock)
*/
#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
    * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind
    * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5=
    * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece
    * iver serial input) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
    *  (TSU clock)
*/
#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi
    * o1_clk_out- (SDSDIO clock) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0=
    * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat
    * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa
    * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
    * serial output) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
    * clk- (TX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i
    * n- (ULPI Clock)
*/
#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy
    * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
    * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
    *  TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc
    * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out
    * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
    * lk- (Trace Port Clock)
*/
#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
    * [0]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir-
    * (Data bus direction control)
*/
#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_
    * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
    * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
    * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou
    * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART
    * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
    * Signal)
*/
#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
    * [1]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
    * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_
    * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
    * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG
    *  TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I
    * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
    * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
    * [2]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt-
    * (Data flow control signal from the PHY)
*/
#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy
    * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
    * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
    *  TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output
    * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out-
    *  (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
    * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
    * [3]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
    * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy
    * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
    * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa
    * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi
    * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc
    * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
    * utput, tracedq[2]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
    * ctl- (TX RGMII control)
*/
#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
    * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_
    * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
    * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W
    * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4=
    * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC
    *  Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
    *  trace, Output, tracedq[3]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
    * lk- (RX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp-
    *  (Asserted to end or interrupt transfers)
*/
#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_
    * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0
    * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG
    * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl
    * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu
    * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
    * Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
    * 0]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
    * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy
    * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c
    * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG
    *  TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O
    * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR
    * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
    * atabus)
*/
#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
    * 1]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
    * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy
    * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c
    * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA
    * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1,
    * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
    * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
    * 2]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
    * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g
    * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_
    * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1
    * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG
    * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output,
    *  spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out-
    * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
    * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
    * 3]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
    * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
    * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo
    * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
    * t, tracedq[8]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
    * tl- (RX RGMII control )
*/
#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da
    * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
    * Used
*/
#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
    * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (
    * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
    * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
    * clk- (TX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i
    * n- (ULPI Clock)
*/
#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
    * (SDSDIO clock) 2= Not Used 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4
    * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in-
    * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
    *  trace, Output, tracedq[10]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
    * [0]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir-
    * (Data bus direction control)
*/
#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
    * card detect from connector) 2= Not Used 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M
    * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u
    * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace
    * dq[11]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
    * [1]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
    * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com
    * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not
    *  Used 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast
    * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_
    * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
    * Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
    * [2]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt-
    * (Data flow control signal from the PHY)
*/
#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N
    * ot Used 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste
    * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt
    * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
    *  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace
    * Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
    * [3]- (TX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
    * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N
    * ot Used 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s
    * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl
    * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
    *  Output, tracedq[14]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
    * ctl- (TX RGMII control)
*/
#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
    * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
    * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4
    * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T
    * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
    * 7= trace, Output, tracedq[15]- (Trace Port Databus)
*/
#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
    * lk- (RX RGMII clock)
*/
#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp-
    *  (Asserted to end or interrupt transfers)
*/
#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
    * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4=
    *  spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (
    * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
    * sed
*/
#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
    * 0]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
    * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[0]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI
    * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6=
    * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
    * 1]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
    * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[1]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (
    * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas
    * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri
    * al output) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
    * 2]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
    * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[2]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out-
    * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master
    *  Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not
    *  Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
    * 3]- (RX RGMII data)
*/
#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
    * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]-
    * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s
    * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
    * t[3]- (8-bit Data bus) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph
    * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2
    * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W
    * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp
    * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (
    * UART receiver serial input) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
    * tl- (RX RGMII control )
*/
#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da
    * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data
    *  bus)
*/
#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow-
    * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1
    * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p
    * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i
    * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out-
    *  (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal)
    * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t
    * xd- (UART transmitter serial output) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca
    * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO
    * clock) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p
    * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i
    * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI
    * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2
    * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK                        0x000000E0U

/*
* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 
#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT                       1
#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK                        0x00000002U

/*
* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
*/
#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 
#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT                       2
#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK                        0x00000004U

/*
* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio
    * 1_cd_n- (SD card detect from connector) 3= Not Used
*/
#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 
#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT                       3
#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK                        0x00000018U

/*
* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0=
    * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph
    * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2
    * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M
    * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input,
    * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5
    * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou
    * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp
    * ut, gem3_mdio_out- (MDIO Data) 7= Not Used
*/
#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 
#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 
#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 
#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL                      0x00000000
#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT                       5
#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK                        0x000000E0U

/*
* Master Tri-state Enable for pin 0, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT                 0
#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK                  0x00000001U

/*
* Master Tri-state Enable for pin 1, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT                 1
#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK                  0x00000002U

/*
* Master Tri-state Enable for pin 2, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT                 2
#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK                  0x00000004U

/*
* Master Tri-state Enable for pin 3, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT                 3
#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK                  0x00000008U

/*
* Master Tri-state Enable for pin 4, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT                 4
#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK                  0x00000010U

/*
* Master Tri-state Enable for pin 5, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT                 5
#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK                  0x00000020U

/*
* Master Tri-state Enable for pin 6, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT                 6
#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK                  0x00000040U

/*
* Master Tri-state Enable for pin 7, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT                 7
#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK                  0x00000080U

/*
* Master Tri-state Enable for pin 8, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT                 8
#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK                  0x00000100U

/*
* Master Tri-state Enable for pin 9, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT                 9
#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK                  0x00000200U

/*
* Master Tri-state Enable for pin 10, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT                 10
#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK                  0x00000400U

/*
* Master Tri-state Enable for pin 11, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT                 11
#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK                  0x00000800U

/*
* Master Tri-state Enable for pin 12, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT                 12
#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK                  0x00001000U

/*
* Master Tri-state Enable for pin 13, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT                 13
#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK                  0x00002000U

/*
* Master Tri-state Enable for pin 14, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT                 14
#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK                  0x00004000U

/*
* Master Tri-state Enable for pin 15, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT                 15
#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK                  0x00008000U

/*
* Master Tri-state Enable for pin 16, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT                 16
#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK                  0x00010000U

/*
* Master Tri-state Enable for pin 17, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT                 17
#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK                  0x00020000U

/*
* Master Tri-state Enable for pin 18, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT                 18
#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK                  0x00040000U

/*
* Master Tri-state Enable for pin 19, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT                 19
#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK                  0x00080000U

/*
* Master Tri-state Enable for pin 20, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT                 20
#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK                  0x00100000U

/*
* Master Tri-state Enable for pin 21, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT                 21
#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK                  0x00200000U

/*
* Master Tri-state Enable for pin 22, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT                 22
#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK                  0x00400000U

/*
* Master Tri-state Enable for pin 23, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT                 23
#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK                  0x00800000U

/*
* Master Tri-state Enable for pin 24, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT                 24
#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK                  0x01000000U

/*
* Master Tri-state Enable for pin 25, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT                 25
#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK                  0x02000000U

/*
* Master Tri-state Enable for pin 26, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT                 26
#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK                  0x04000000U

/*
* Master Tri-state Enable for pin 27, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT                 27
#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK                  0x08000000U

/*
* Master Tri-state Enable for pin 28, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT                 28
#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK                  0x10000000U

/*
* Master Tri-state Enable for pin 29, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT                 29
#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK                  0x20000000U

/*
* Master Tri-state Enable for pin 30, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT                 30
#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK                  0x40000000U

/*
* Master Tri-state Enable for pin 31, active high
*/
#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT                 31
#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK                  0x80000000U

/*
* Master Tri-state Enable for pin 32, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT                 0
#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK                  0x00000001U

/*
* Master Tri-state Enable for pin 33, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT                 1
#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK                  0x00000002U

/*
* Master Tri-state Enable for pin 34, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT                 2
#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK                  0x00000004U

/*
* Master Tri-state Enable for pin 35, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT                 3
#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK                  0x00000008U

/*
* Master Tri-state Enable for pin 36, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT                 4
#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK                  0x00000010U

/*
* Master Tri-state Enable for pin 37, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT                 5
#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK                  0x00000020U

/*
* Master Tri-state Enable for pin 38, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT                 6
#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK                  0x00000040U

/*
* Master Tri-state Enable for pin 39, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT                 7
#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK                  0x00000080U

/*
* Master Tri-state Enable for pin 40, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT                 8
#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK                  0x00000100U

/*
* Master Tri-state Enable for pin 41, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT                 9
#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK                  0x00000200U

/*
* Master Tri-state Enable for pin 42, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT                 10
#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK                  0x00000400U

/*
* Master Tri-state Enable for pin 43, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT                 11
#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK                  0x00000800U

/*
* Master Tri-state Enable for pin 44, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT                 12
#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK                  0x00001000U

/*
* Master Tri-state Enable for pin 45, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT                 13
#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK                  0x00002000U

/*
* Master Tri-state Enable for pin 46, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT                 14
#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK                  0x00004000U

/*
* Master Tri-state Enable for pin 47, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT                 15
#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK                  0x00008000U

/*
* Master Tri-state Enable for pin 48, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT                 16
#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK                  0x00010000U

/*
* Master Tri-state Enable for pin 49, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT                 17
#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK                  0x00020000U

/*
* Master Tri-state Enable for pin 50, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT                 18
#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK                  0x00040000U

/*
* Master Tri-state Enable for pin 51, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT                 19
#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK                  0x00080000U

/*
* Master Tri-state Enable for pin 52, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT                 20
#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK                  0x00100000U

/*
* Master Tri-state Enable for pin 53, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT                 21
#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK                  0x00200000U

/*
* Master Tri-state Enable for pin 54, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT                 22
#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK                  0x00400000U

/*
* Master Tri-state Enable for pin 55, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT                 23
#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK                  0x00800000U

/*
* Master Tri-state Enable for pin 56, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT                 24
#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK                  0x01000000U

/*
* Master Tri-state Enable for pin 57, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT                 25
#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK                  0x02000000U

/*
* Master Tri-state Enable for pin 58, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT                 26
#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK                  0x04000000U

/*
* Master Tri-state Enable for pin 59, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT                 27
#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK                  0x08000000U

/*
* Master Tri-state Enable for pin 60, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT                 28
#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK                  0x10000000U

/*
* Master Tri-state Enable for pin 61, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT                 29
#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK                  0x20000000U

/*
* Master Tri-state Enable for pin 62, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT                 30
#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK                  0x40000000U

/*
* Master Tri-state Enable for pin 63, active high
*/
#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL                0xFFFFFFFF
#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT                 31
#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK                  0x80000000U

/*
* Master Tri-state Enable for pin 64, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT                 0
#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK                  0x00000001U

/*
* Master Tri-state Enable for pin 65, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT                 1
#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK                  0x00000002U

/*
* Master Tri-state Enable for pin 66, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT                 2
#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK                  0x00000004U

/*
* Master Tri-state Enable for pin 67, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT                 3
#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK                  0x00000008U

/*
* Master Tri-state Enable for pin 68, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT                 4
#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK                  0x00000010U

/*
* Master Tri-state Enable for pin 69, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT                 5
#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK                  0x00000020U

/*
* Master Tri-state Enable for pin 70, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT                 6
#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK                  0x00000040U

/*
* Master Tri-state Enable for pin 71, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT                 7
#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK                  0x00000080U

/*
* Master Tri-state Enable for pin 72, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT                 8
#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK                  0x00000100U

/*
* Master Tri-state Enable for pin 73, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT                 9
#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK                  0x00000200U

/*
* Master Tri-state Enable for pin 74, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT                 10
#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK                  0x00000400U

/*
* Master Tri-state Enable for pin 75, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT                 11
#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK                  0x00000800U

/*
* Master Tri-state Enable for pin 76, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT                 12
#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK                  0x00001000U

/*
* Master Tri-state Enable for pin 77, active high
*/
#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 
#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 
#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL                0x00003FFF
#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT                 13
#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK                  0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT                0
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK                 0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT                1
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK                 0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT                2
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK                 0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT                3
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK                 0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT                4
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK                 0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT                5
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK                 0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT                6
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK                 0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT                7
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK                 0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT                8
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK                 0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL               
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT                9
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK                 0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT               10
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK                0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT               11
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK                0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT               12
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK                0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT               13
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK                0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT               14
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK                0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT               15
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK                0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT               16
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK                0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT               17
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK                0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT               18
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK                0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT               19
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK                0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT               20
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK                0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT               21
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK                0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT               22
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK                0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT               23
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK                0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT               24
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK                0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 
#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL              
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT               25
#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK                0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT                0
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK                 0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT                1
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK                 0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT                2
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK                 0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT                3
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK                 0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT                4
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK                 0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT                5
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK                 0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT                6
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK                 0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT                7
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK                 0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT                8
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK                 0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL               
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT                9
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK                 0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT               10
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK                0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT               11
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK                0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT               12
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK                0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT               13
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK                0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT               14
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK                0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT               15
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK                0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT               16
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK                0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT               17
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK                0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT               18
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK                0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT               19
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK                0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT               20
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK                0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT               21
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK                0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT               22
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK                0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT               23
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK                0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT               24
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK                0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 
#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL              
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT               25
#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK                0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT        0
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK         0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT        1
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK         0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT        2
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK         0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT        3
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK         0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT        4
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK         0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT        5
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK         0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT        6
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK         0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT        7
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK         0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT        8
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK         0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL       
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT        9
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK         0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT       10
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK        0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT       11
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK        0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT       12
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK        0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT       13
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK        0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT       14
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK        0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT       15
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK        0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT       16
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK        0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT       17
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK        0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT       18
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK        0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT       19
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK        0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT       20
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK        0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT       21
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK        0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT       22
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK        0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT       23
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK        0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT       24
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK        0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL      
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT       25
#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK        0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT       0
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK        0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT       1
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK        0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT       2
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK        0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT       3
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK        0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT       4
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK        0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT       5
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK        0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT       6
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK        0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT       7
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK        0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT       8
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK        0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL      
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT       9
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK        0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT      10
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK       0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT      11
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK       0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT      12
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK       0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT      13
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK       0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT      14
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK       0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT      15
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK       0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT      16
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK       0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT      17
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK       0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT      18
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK       0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT      19
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK       0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT      20
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK       0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT      21
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK       0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT      22
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK       0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT      23
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK       0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT      24
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK       0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL     
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT      25
#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK       0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT           0
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK            0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT           1
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK            0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT           2
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK            0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT           3
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK            0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT           4
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK            0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT           5
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK            0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT           6
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK            0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT           7
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK            0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT           8
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK            0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL          
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT           9
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK            0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT          10
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK           0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT          11
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK           0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT          12
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK           0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT          13
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK           0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT          14
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK           0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT          15
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK           0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT          16
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK           0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT          17
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK           0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT          18
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK           0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT          19
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK           0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT          20
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK           0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT          21
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK           0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT          22
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK           0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT          23
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK           0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT          24
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK           0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL         
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT          25
#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK           0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT      0
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK       0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT      1
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK       0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT      2
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK       0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT      3
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK       0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT      4
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK       0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT      5
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK       0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT      6
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK       0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT      7
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK       0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT      8
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK       0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL     
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT      9
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK       0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT     10
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK      0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT     11
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK      0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT     12
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK      0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT     13
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK      0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT     14
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK      0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT     15
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK      0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT     16
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK      0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT     17
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK      0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT     18
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK      0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT     19
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK      0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT     20
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK      0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT     21
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK      0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT     22
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK      0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT     23
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK      0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT     24
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK      0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[0].
*/
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL    
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT     25
#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK      0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT                0
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK                 0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT                1
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK                 0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT                2
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK                 0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT                3
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK                 0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT                4
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK                 0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT                5
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK                 0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT                6
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK                 0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT                7
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK                 0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT                8
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK                 0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL               
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT                9
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK                 0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT               10
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK                0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT               11
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK                0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT               12
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK                0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT               13
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK                0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT               14
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK                0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT               15
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK                0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT               16
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK                0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT               17
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK                0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT               18
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK                0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT               19
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK                0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT               20
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK                0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT               21
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK                0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT               22
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK                0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT               23
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK                0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT               24
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK                0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 
#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL              
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT               25
#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK                0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT                0
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK                 0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT                1
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK                 0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT                2
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK                 0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT                3
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK                 0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT                4
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK                 0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT                5
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK                 0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT                6
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK                 0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT                7
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK                 0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT                8
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK                 0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL               
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT                9
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK                 0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT               10
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK                0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT               11
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK                0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT               12
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK                0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT               13
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK                0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT               14
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK                0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT               15
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK                0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT               16
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK                0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT               17
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK                0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT               18
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK                0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT               19
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK                0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT               20
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK                0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT               21
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK                0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT               22
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK                0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT               23
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK                0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT               24
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK                0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 
#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL              
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT               25
#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK                0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT        0
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK         0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT        1
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK         0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT        2
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK         0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT        3
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK         0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT        4
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK         0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT        5
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK         0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT        6
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK         0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT        7
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK         0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT        8
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK         0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL       
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT        9
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK         0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT       10
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK        0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT       11
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK        0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT       12
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK        0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT       13
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK        0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT       14
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK        0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT       15
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK        0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT       16
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK        0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT       17
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK        0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT       18
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK        0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT       19
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK        0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT       20
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK        0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT       21
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK        0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT       22
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK        0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT       23
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK        0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT       24
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK        0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL      
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT       25
#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK        0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT       0
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK        0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT       1
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK        0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT       2
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK        0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT       3
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK        0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT       4
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK        0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT       5
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK        0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT       6
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK        0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT       7
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK        0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT       8
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK        0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL      
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT       9
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK        0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT      10
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK       0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT      11
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK       0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT      12
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK       0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT      13
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK       0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT      14
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK       0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT      15
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK       0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT      16
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK       0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT      17
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK       0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT      18
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK       0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT      19
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK       0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT      20
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK       0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT      21
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK       0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT      22
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK       0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT      23
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK       0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT      24
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK       0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL     
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT      25
#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK       0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT           12
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK            0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT           13
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK            0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT           14
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK            0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT           15
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK            0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT           16
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK            0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT           17
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK            0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT           18
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK            0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT           19
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK            0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT           20
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK            0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL          
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT           21
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK            0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT          22
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK           0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT          23
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK           0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT          24
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK           0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT          25
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK           0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT          0
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK           0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT          1
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK           0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT          2
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK           0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT          3
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK           0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT          4
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK           0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT          5
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK           0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT          6
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK           0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT          7
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK           0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT          8
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK           0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT          9
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK           0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT          10
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK           0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL         
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT          11
#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK           0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT      0
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK       0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT      1
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK       0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT      2
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK       0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT      3
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK       0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT      4
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK       0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT      5
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK       0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT      6
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK       0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT      7
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK       0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT      8
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK       0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL     
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT      9
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK       0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT     10
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK      0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT     11
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK      0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT     12
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK      0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT     13
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK      0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT     14
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK      0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT     15
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK      0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT     16
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK      0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT     17
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK      0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT     18
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK      0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT     19
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK      0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT     20
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK      0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT     21
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK      0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT     22
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK      0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT     23
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK      0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT     24
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK      0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[26].
*/
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL    
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT     25
#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK      0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT                0
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK                 0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT                1
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK                 0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT                2
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK                 0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT                3
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK                 0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT                4
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK                 0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT                5
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK                 0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT                6
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK                 0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT                7
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK                 0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT                8
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK                 0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL               
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT                9
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK                 0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT               10
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK                0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT               11
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK                0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT               12
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK                0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT               13
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK                0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT               14
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK                0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT               15
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK                0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT               16
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK                0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT               17
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK                0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT               18
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK                0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT               19
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK                0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT               20
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK                0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT               21
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK                0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT               22
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK                0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT               23
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK                0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT               24
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK                0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 
#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL              
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT               25
#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK                0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT                0
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK                 0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT                1
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK                 0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT                2
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK                 0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT                3
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK                 0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT                4
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK                 0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT                5
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK                 0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT                6
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK                 0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT                7
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK                 0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT                8
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK                 0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL               
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT                9
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK                 0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT               10
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK                0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT               11
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK                0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT               12
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK                0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT               13
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK                0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT               14
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK                0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT               15
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK                0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT               16
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK                0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT               17
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK                0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT               18
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK                0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT               19
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK                0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT               20
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK                0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT               21
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK                0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT               22
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK                0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT               23
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK                0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT               24
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK                0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 
#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL              
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT               25
#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK                0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT        0
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK         0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT        1
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK         0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT        2
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK         0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT        3
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK         0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT        4
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK         0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT        5
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK         0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT        6
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK         0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT        7
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK         0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT        8
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK         0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL       
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT        9
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK         0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT       10
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK        0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT       11
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK        0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT       12
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK        0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT       13
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK        0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT       14
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK        0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT       15
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK        0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT       16
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK        0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT       17
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK        0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT       18
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK        0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT       19
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK        0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT       20
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK        0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT       21
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK        0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT       22
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK        0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT       23
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK        0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT       24
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK        0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL      
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT       25
#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK        0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT       0
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK        0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT       1
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK        0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT       2
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK        0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT       3
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK        0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT       4
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK        0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT       5
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK        0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT       6
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK        0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT       7
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK        0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT       8
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK        0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL      
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT       9
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK        0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT      10
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK       0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT      11
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK       0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT      12
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK       0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT      13
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK       0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT      14
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK       0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT      15
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK       0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT      16
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK       0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT      17
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK       0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT      18
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK       0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT      19
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK       0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT      20
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK       0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT      21
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK       0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT      22
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK       0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT      23
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK       0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT      24
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK       0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL     
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT      25
#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK       0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT           0
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK            0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT           1
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK            0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT           2
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK            0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT           3
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK            0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT           4
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK            0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT           5
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK            0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT           6
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK            0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT           7
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK            0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT           8
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK            0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL          
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT           9
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK            0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT          10
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK           0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT          11
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK           0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT          12
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK           0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT          13
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK           0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT          14
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK           0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT          15
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK           0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT          16
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK           0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT          17
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK           0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT          18
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK           0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT          19
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK           0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT          20
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK           0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT          21
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK           0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT          22
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK           0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT          23
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK           0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT          24
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK           0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL         
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT          25
#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK           0x02000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT      0
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK       0x00000001U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT      1
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK       0x00000002U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT      2
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK       0x00000004U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT      3
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK       0x00000008U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT      4
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK       0x00000010U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT      5
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK       0x00000020U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT      6
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK       0x00000040U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT      7
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK       0x00000080U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT      8
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK       0x00000100U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL     
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT      9
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK       0x00000200U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT     10
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK      0x00000400U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT     11
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK      0x00000800U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT     12
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK      0x00001000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT     13
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK      0x00002000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT     14
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK      0x00004000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT     15
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK      0x00008000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT     16
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK      0x00010000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT     17
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK      0x00020000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT     18
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK      0x00040000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT     19
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK      0x00080000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT     20
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK      0x00100000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT     21
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK      0x00200000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT     22
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK      0x00400000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT     23
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK      0x00800000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT     24
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK      0x01000000U

/*
* Each bit applies to a single IO. Bit 0 for MIO[52].
*/
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL    
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT     25
#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK      0x02000000U

/*
* I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1
    *  = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs
    * .
*/
#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 
#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 
#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 
#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL            0x00000000
#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT             3
#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK              0x00000008U

/*
* CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1
    *  = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.
*/
#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 
#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 
#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 
#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL            0x00000000
#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT             2
#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK              0x00000004U

/*
* UART Loopback Control. 0 = Connect UART inputs according to MIO mapping.
    *  1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0
    * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD
    * and RI not used.
*/
#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 
#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 
#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 
#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL              0x00000000
#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT               1
#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK                0x00000002U

/*
* SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1
    *  = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs
    * . The other SPI core will appear on the LS Slave Select.
*/
#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 
#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 
#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL            0x00000000
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT             0
#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK              0x00000001U
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef CRL_APB_RST_LPD_TOP_OFFSET 
#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET 
#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 
#define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET                                          0XFF180390
#undef CRL_APB_RST_LPD_TOP_OFFSET 
#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
#undef USB3_0_FPD_POWER_PRSNT_OFFSET 
#define USB3_0_FPD_POWER_PRSNT_OFFSET                                              0XFF9D0080
#undef USB3_0_FPD_PIPE_CLK_OFFSET 
#define USB3_0_FPD_PIPE_CLK_OFFSET                                                 0XFF9D007C
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef IOU_SLCR_CTRL_REG_SD_OFFSET 
#define IOU_SLCR_CTRL_REG_SD_OFFSET                                                0XFF180310
#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET 
#define IOU_SLCR_SD_CONFIG_REG2_OFFSET                                             0XFF180320
#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET 
#define IOU_SLCR_SD_CONFIG_REG1_OFFSET                                             0XFF18031C
#undef IOU_SLCR_SD_DLL_CTRL_OFFSET 
#define IOU_SLCR_SD_DLL_CTRL_OFFSET                                                0XFF180358
#undef IOU_SLCR_SD_CONFIG_REG3_OFFSET 
#define IOU_SLCR_SD_CONFIG_REG3_OFFSET                                             0XFF180324
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 
#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF000034
#undef UART0_BAUD_RATE_GEN_REG0_OFFSET 
#define UART0_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF000018
#undef UART0_CONTROL_REG0_OFFSET 
#define UART0_CONTROL_REG0_OFFSET                                                  0XFF000000
#undef UART0_MODE_REG0_OFFSET 
#define UART0_MODE_REG0_OFFSET                                                     0XFF000004
#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 
#define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF010034
#undef UART1_BAUD_RATE_GEN_REG0_OFFSET 
#define UART1_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF010018
#undef UART1_CONTROL_REG0_OFFSET 
#define UART1_CONTROL_REG0_OFFSET                                                  0XFF010000
#undef UART1_MODE_REG0_OFFSET 
#define UART1_MODE_REG0_OFFSET                                                     0XFF010004
#undef CRL_APB_RST_LPD_IOU2_OFFSET 
#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 
#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
#undef CSU_TAMPER_STATUS_OFFSET 
#define CSU_TAMPER_STATUS_OFFSET                                                   0XFFCA5000
#undef APU_ACE_CTRL_OFFSET 
#define APU_ACE_CTRL_OFFSET                                                        0XFD5C0060
#undef RTC_CONTROL_OFFSET 
#define RTC_CONTROL_OFFSET                                                         0XFFA60040
#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 
#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET                               0XFF260020
#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 
#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET                                 0XFF260000
#undef GPIO_DIRM_1_OFFSET 
#define GPIO_DIRM_1_OFFSET                                                         0XFF0A0244
#undef GPIO_OEN_1_OFFSET 
#define GPIO_OEN_1_OFFSET                                                          0XFF0A0248
#undef GPIO_MASK_DATA_1_LSW_OFFSET 
#define GPIO_MASK_DATA_1_LSW_OFFSET                                                0XFF0A0008
#undef GPIO_MASK_DATA_1_LSW_OFFSET 
#define GPIO_MASK_DATA_1_LSW_OFFSET                                                0XFF0A0008

/*
* PCIE config reset
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL              0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT               19
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                0x00080000U

/*
* PCIE control block level reset
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL             0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT              17
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK               0x00020000U

/*
* PCIE bridge block level reset (AXI interface)
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL           0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT            18
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK             0x00040000U

/*
* Display Port block level reset (includes DPDMA)
*/
#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                    0x000F9FFE
#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                     16
#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                      0x00010000U

/*
* FPD WDT reset
*/
#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL                  0x000F9FFE
#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT                   15
#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK                    0x00008000U

/*
* GDMA block level reset
*/
#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL                  0x000F9FFE
#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT                   6
#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK                    0x00000040U

/*
* Pixel Processor (submodule of GPU) block level reset
*/
#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL               0x000F9FFE
#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT                4
#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK                 0x00000010U

/*
* Pixel Processor (submodule of GPU) block level reset
*/
#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL               0x000F9FFE
#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT                5
#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK                 0x00000020U

/*
* GPU block level reset
*/
#undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL                   0x000F9FFE
#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT                    3
#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK                     0x00000008U

/*
* GT block level reset
*/
#undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL                    0x000F9FFE
#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT                     2
#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK                      0x00000004U

/*
* Sata block level reset
*/
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                  0x000F9FFE
#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                   1
#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                    0x00000002U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL            0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT             20
#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK              0x00100000U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL               0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT                19
#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK                 0x00080000U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT                  17
#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK                   0x00020000U

/*
* Reset entire full power domain.
*/
#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL                   0x00188FDF
#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT                    23
#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK                     0x00800000U

/*
* LPD SWDT
*/
#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL              0x00188FDF
#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT               20
#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK                0x00100000U

/*
* Sysmonitor reset
*/
#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL                0x00188FDF
#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT                 17
#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK                  0x00020000U

/*
* Real Time Clock reset
*/
#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL                   0x00188FDF
#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT                    16
#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK                     0x00010000U

/*
* APM reset
*/
#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL                   0x00188FDF
#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT                    15
#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK                     0x00008000U

/*
* IPI reset
*/
#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL                   0x00188FDF
#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT                    14
#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK                     0x00004000U

/*
* reset entire RPU power island
*/
#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL               0x00188FDF
#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT                4
#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK                 0x00000010U

/*
* reset ocm
*/
#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL                   0x00188FDF
#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT                    3
#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK                     0x00000008U

/*
* GEM 3 reset
*/
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                 0x0000000F
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                  3
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                   0x00000008U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT                  0
#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK                   0x00000001U

/*
* 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
    * ss the Tap delay on the Rx clock signal of LQSPI
*/
#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 
#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 
#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 
#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL             0x00000007
#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT              2
#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK               0x00000004U

/*
* USB 0 reset for control registers
*/
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL              0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT               10
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                0x00000400U

/*
* USB 0 sleep circuit reset
*/
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL             0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT              8
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK               0x00000100U

/*
* USB 0 reset
*/
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL              0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT               6
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                0x00000040U

/*
* This bit is used to choose between PIPE power present and 1'b1
*/
#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL 
#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 
#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK 
#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL                   
#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT                    0
#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK                     0x00000001U

/*
* This bit is used to choose between PIPE clock coming from SerDes and the
    *  suspend clk
*/
#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL 
#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 
#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK 
#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL                      
#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT                       0
#define USB3_0_FPD_PIPE_CLK_OPTION_MASK                        0x00000001U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL                0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT                 6
#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK                  0x00000040U

/*
* SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
*/
#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 
#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 
#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 
#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL               0x00000000
#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT                15
#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK                 0x00008000U

/*
* Should be set based on the final product usage 00 - Removable SCard Slot
    *  01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
*/
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 
#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL            0x0FFC0FFC
#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT             28
#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK              0x30000000U

/*
* 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
*/
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 
#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL                0x0FFC0FFC
#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT                 25
#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK                  0x02000000U

/*
* 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
*/
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 
#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL                0x0FFC0FFC
#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT                 24
#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK                  0x01000000U

/*
* 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
*/
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 
#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 
#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL                0x0FFC0FFC
#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT                 23
#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK                  0x00800000U

/*
* Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
*/
#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 
#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 
#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 
#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL             0x32403240
#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT              23
#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK               0x7F800000U

/*
* Configures the Number of Taps (Phases) of the rxclk_in that is supported
    * .
*/
#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 
#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 
#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 
#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL          0x32403240
#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT           17
#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK            0x007E0000U

/*
* Reserved.
*/
#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 
#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 
#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 
#define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL                   0x00080008
#define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT                    3
#define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK                     0x00000008U

/*
* This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S
    * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other
    * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n
    * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved
*/
#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 
#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 
#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 
#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL           0x06070607
#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT            22
#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK             0x03C00000U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT                  8
#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK                   0x00000100U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT                  9
#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK                   0x00000200U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT                  10
#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK                   0x00000400U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT                  15
#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK                   0x00008000U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT                  11
#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK                   0x00000800U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT                  12
#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK                   0x00001000U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT                  13
#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK                   0x00002000U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT                  14
#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK                   0x00004000U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL                0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT                 1
#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK                  0x00000002U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL                0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT                 2
#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK                  0x00000004U

/*
* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
*/
#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL               0x0000000F
#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                0
#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                 0x000000FFU

/*
* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
    * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
*/
#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 
#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 
#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK 
#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL                     0x0000028B
#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT                      0
#define UART0_BAUD_RATE_GEN_REG0_CD_MASK                       0x0000FFFFU

/*
* Stop transmitter break: 0: no affect 1: stop transmission of the break a
    * fter a minimum of one character length and transmit a high level during
    * 12 bit periods. It can be set regardless of the value of STTBRK.
*/
#undef UART0_CONTROL_REG0_STPBRK_DEFVAL 
#undef UART0_CONTROL_REG0_STPBRK_SHIFT 
#undef UART0_CONTROL_REG0_STPBRK_MASK 
#define UART0_CONTROL_REG0_STPBRK_DEFVAL                       0x00000128
#define UART0_CONTROL_REG0_STPBRK_SHIFT                        8
#define UART0_CONTROL_REG0_STPBRK_MASK                         0x00000100U

/*
* Start transmitter break: 0: no affect 1: start to transmit a break after
    *  the characters currently present in the FIFO and the transmit shift reg
    * ister have been transmitted. It can only be set if STPBRK (Stop transmit
    * ter break) is not high.
*/
#undef UART0_CONTROL_REG0_STTBRK_DEFVAL 
#undef UART0_CONTROL_REG0_STTBRK_SHIFT 
#undef UART0_CONTROL_REG0_STTBRK_MASK 
#define UART0_CONTROL_REG0_STTBRK_DEFVAL                       0x00000128
#define UART0_CONTROL_REG0_STTBRK_SHIFT                        7
#define UART0_CONTROL_REG0_STTBRK_MASK                         0x00000080U

/*
* Restart receiver timeout counter: 1: receiver timeout counter is restart
    * ed. This bit is self clearing once the restart has completed.
*/
#undef UART0_CONTROL_REG0_RSTTO_DEFVAL 
#undef UART0_CONTROL_REG0_RSTTO_SHIFT 
#undef UART0_CONTROL_REG0_RSTTO_MASK 
#define UART0_CONTROL_REG0_RSTTO_DEFVAL                        0x00000128
#define UART0_CONTROL_REG0_RSTTO_SHIFT                         6
#define UART0_CONTROL_REG0_RSTTO_MASK                          0x00000040U

/*
* Transmit disable: 0: enable transmitter 1: disable transmitter
*/
#undef UART0_CONTROL_REG0_TXDIS_DEFVAL 
#undef UART0_CONTROL_REG0_TXDIS_SHIFT 
#undef UART0_CONTROL_REG0_TXDIS_MASK 
#define UART0_CONTROL_REG0_TXDIS_DEFVAL                        0x00000128
#define UART0_CONTROL_REG0_TXDIS_SHIFT                         5
#define UART0_CONTROL_REG0_TXDIS_MASK                          0x00000020U

/*
* Transmit enable: 0: disable transmitter 1: enable transmitter, provided
    * the TXDIS field is set to 0.
*/
#undef UART0_CONTROL_REG0_TXEN_DEFVAL 
#undef UART0_CONTROL_REG0_TXEN_SHIFT 
#undef UART0_CONTROL_REG0_TXEN_MASK 
#define UART0_CONTROL_REG0_TXEN_DEFVAL                         0x00000128
#define UART0_CONTROL_REG0_TXEN_SHIFT                          4
#define UART0_CONTROL_REG0_TXEN_MASK                           0x00000010U

/*
* Receive disable: 0: enable 1: disable, regardless of the value of RXEN
*/
#undef UART0_CONTROL_REG0_RXDIS_DEFVAL 
#undef UART0_CONTROL_REG0_RXDIS_SHIFT 
#undef UART0_CONTROL_REG0_RXDIS_MASK 
#define UART0_CONTROL_REG0_RXDIS_DEFVAL                        0x00000128
#define UART0_CONTROL_REG0_RXDIS_SHIFT                         3
#define UART0_CONTROL_REG0_RXDIS_MASK                          0x00000008U

/*
* Receive enable: 0: disable 1: enable When set to one, the receiver logic
    *  is enabled, provided the RXDIS field is set to zero.
*/
#undef UART0_CONTROL_REG0_RXEN_DEFVAL 
#undef UART0_CONTROL_REG0_RXEN_SHIFT 
#undef UART0_CONTROL_REG0_RXEN_MASK 
#define UART0_CONTROL_REG0_RXEN_DEFVAL                         0x00000128
#define UART0_CONTROL_REG0_RXEN_SHIFT                          2
#define UART0_CONTROL_REG0_RXEN_MASK                           0x00000004U

/*
* Software reset for Tx data path: 0: no affect 1: transmitter logic is re
    * set and all pending transmitter data is discarded This bit is self clear
    * ing once the reset has completed.
*/
#undef UART0_CONTROL_REG0_TXRES_DEFVAL 
#undef UART0_CONTROL_REG0_TXRES_SHIFT 
#undef UART0_CONTROL_REG0_TXRES_MASK 
#define UART0_CONTROL_REG0_TXRES_DEFVAL                        0x00000128
#define UART0_CONTROL_REG0_TXRES_SHIFT                         1
#define UART0_CONTROL_REG0_TXRES_MASK                          0x00000002U

/*
* Software reset for Rx data path: 0: no affect 1: receiver logic is reset
    *  and all pending receiver data is discarded. This bit is self clearing o
    * nce the reset has completed.
*/
#undef UART0_CONTROL_REG0_RXRES_DEFVAL 
#undef UART0_CONTROL_REG0_RXRES_SHIFT 
#undef UART0_CONTROL_REG0_RXRES_MASK 
#define UART0_CONTROL_REG0_RXRES_DEFVAL                        0x00000128
#define UART0_CONTROL_REG0_RXRES_SHIFT                         0
#define UART0_CONTROL_REG0_RXRES_MASK                          0x00000001U

/*
* Channel mode: Defines the mode of operation of the UART. 00: normal 01:
    * automatic echo 10: local loopback 11: remote loopback
*/
#undef UART0_MODE_REG0_CHMODE_DEFVAL 
#undef UART0_MODE_REG0_CHMODE_SHIFT 
#undef UART0_MODE_REG0_CHMODE_MASK 
#define UART0_MODE_REG0_CHMODE_DEFVAL                          0x00000000
#define UART0_MODE_REG0_CHMODE_SHIFT                           8
#define UART0_MODE_REG0_CHMODE_MASK                            0x00000300U

/*
* Number of stop bits: Defines the number of stop bits to detect on receiv
    * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
    * op bits 11: reserved
*/
#undef UART0_MODE_REG0_NBSTOP_DEFVAL 
#undef UART0_MODE_REG0_NBSTOP_SHIFT 
#undef UART0_MODE_REG0_NBSTOP_MASK 
#define UART0_MODE_REG0_NBSTOP_DEFVAL                          0x00000000
#define UART0_MODE_REG0_NBSTOP_SHIFT                           6
#define UART0_MODE_REG0_NBSTOP_MASK                            0x000000C0U

/*
* Parity type select: Defines the expected parity to check on receive and
    * the parity to generate on transmit. 000: even parity 001: odd parity 010
    * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
    * ty
*/
#undef UART0_MODE_REG0_PAR_DEFVAL 
#undef UART0_MODE_REG0_PAR_SHIFT 
#undef UART0_MODE_REG0_PAR_MASK 
#define UART0_MODE_REG0_PAR_DEFVAL                             0x00000000
#define UART0_MODE_REG0_PAR_SHIFT                              3
#define UART0_MODE_REG0_PAR_MASK                               0x00000038U

/*
* Character length select: Defines the number of bits in each character. 1
    * 1: 6 bits 10: 7 bits 0x: 8 bits
*/
#undef UART0_MODE_REG0_CHRL_DEFVAL 
#undef UART0_MODE_REG0_CHRL_SHIFT 
#undef UART0_MODE_REG0_CHRL_MASK 
#define UART0_MODE_REG0_CHRL_DEFVAL                            0x00000000
#define UART0_MODE_REG0_CHRL_SHIFT                             1
#define UART0_MODE_REG0_CHRL_MASK                              0x00000006U

/*
* Clock source select: This field defines whether a pre-scalar of 8 is app
    * lied to the baud rate generator input clock. 0: clock source is uart_ref
    * _clk 1: clock source is uart_ref_clk/8
*/
#undef UART0_MODE_REG0_CLKS_DEFVAL 
#undef UART0_MODE_REG0_CLKS_SHIFT 
#undef UART0_MODE_REG0_CLKS_MASK 
#define UART0_MODE_REG0_CLKS_DEFVAL                            0x00000000
#define UART0_MODE_REG0_CLKS_SHIFT                             0
#define UART0_MODE_REG0_CLKS_MASK                              0x00000001U

/*
* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
*/
#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL               0x0000000F
#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                0
#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                 0x000000FFU

/*
* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
    * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
*/
#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 
#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 
#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK 
#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL                     0x0000028B
#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT                      0
#define UART1_BAUD_RATE_GEN_REG0_CD_MASK                       0x0000FFFFU

/*
* Stop transmitter break: 0: no affect 1: stop transmission of the break a
    * fter a minimum of one character length and transmit a high level during
    * 12 bit periods. It can be set regardless of the value of STTBRK.
*/
#undef UART1_CONTROL_REG0_STPBRK_DEFVAL 
#undef UART1_CONTROL_REG0_STPBRK_SHIFT 
#undef UART1_CONTROL_REG0_STPBRK_MASK 
#define UART1_CONTROL_REG0_STPBRK_DEFVAL                       0x00000128
#define UART1_CONTROL_REG0_STPBRK_SHIFT                        8
#define UART1_CONTROL_REG0_STPBRK_MASK                         0x00000100U

/*
* Start transmitter break: 0: no affect 1: start to transmit a break after
    *  the characters currently present in the FIFO and the transmit shift reg
    * ister have been transmitted. It can only be set if STPBRK (Stop transmit
    * ter break) is not high.
*/
#undef UART1_CONTROL_REG0_STTBRK_DEFVAL 
#undef UART1_CONTROL_REG0_STTBRK_SHIFT 
#undef UART1_CONTROL_REG0_STTBRK_MASK 
#define UART1_CONTROL_REG0_STTBRK_DEFVAL                       0x00000128
#define UART1_CONTROL_REG0_STTBRK_SHIFT                        7
#define UART1_CONTROL_REG0_STTBRK_MASK                         0x00000080U

/*
* Restart receiver timeout counter: 1: receiver timeout counter is restart
    * ed. This bit is self clearing once the restart has completed.
*/
#undef UART1_CONTROL_REG0_RSTTO_DEFVAL 
#undef UART1_CONTROL_REG0_RSTTO_SHIFT 
#undef UART1_CONTROL_REG0_RSTTO_MASK 
#define UART1_CONTROL_REG0_RSTTO_DEFVAL                        0x00000128
#define UART1_CONTROL_REG0_RSTTO_SHIFT                         6
#define UART1_CONTROL_REG0_RSTTO_MASK                          0x00000040U

/*
* Transmit disable: 0: enable transmitter 1: disable transmitter
*/
#undef UART1_CONTROL_REG0_TXDIS_DEFVAL 
#undef UART1_CONTROL_REG0_TXDIS_SHIFT 
#undef UART1_CONTROL_REG0_TXDIS_MASK 
#define UART1_CONTROL_REG0_TXDIS_DEFVAL                        0x00000128
#define UART1_CONTROL_REG0_TXDIS_SHIFT                         5
#define UART1_CONTROL_REG0_TXDIS_MASK                          0x00000020U

/*
* Transmit enable: 0: disable transmitter 1: enable transmitter, provided
    * the TXDIS field is set to 0.
*/
#undef UART1_CONTROL_REG0_TXEN_DEFVAL 
#undef UART1_CONTROL_REG0_TXEN_SHIFT 
#undef UART1_CONTROL_REG0_TXEN_MASK 
#define UART1_CONTROL_REG0_TXEN_DEFVAL                         0x00000128
#define UART1_CONTROL_REG0_TXEN_SHIFT                          4
#define UART1_CONTROL_REG0_TXEN_MASK                           0x00000010U

/*
* Receive disable: 0: enable 1: disable, regardless of the value of RXEN
*/
#undef UART1_CONTROL_REG0_RXDIS_DEFVAL 
#undef UART1_CONTROL_REG0_RXDIS_SHIFT 
#undef UART1_CONTROL_REG0_RXDIS_MASK 
#define UART1_CONTROL_REG0_RXDIS_DEFVAL                        0x00000128
#define UART1_CONTROL_REG0_RXDIS_SHIFT                         3
#define UART1_CONTROL_REG0_RXDIS_MASK                          0x00000008U

/*
* Receive enable: 0: disable 1: enable When set to one, the receiver logic
    *  is enabled, provided the RXDIS field is set to zero.
*/
#undef UART1_CONTROL_REG0_RXEN_DEFVAL 
#undef UART1_CONTROL_REG0_RXEN_SHIFT 
#undef UART1_CONTROL_REG0_RXEN_MASK 
#define UART1_CONTROL_REG0_RXEN_DEFVAL                         0x00000128
#define UART1_CONTROL_REG0_RXEN_SHIFT                          2
#define UART1_CONTROL_REG0_RXEN_MASK                           0x00000004U

/*
* Software reset for Tx data path: 0: no affect 1: transmitter logic is re
    * set and all pending transmitter data is discarded This bit is self clear
    * ing once the reset has completed.
*/
#undef UART1_CONTROL_REG0_TXRES_DEFVAL 
#undef UART1_CONTROL_REG0_TXRES_SHIFT 
#undef UART1_CONTROL_REG0_TXRES_MASK 
#define UART1_CONTROL_REG0_TXRES_DEFVAL                        0x00000128
#define UART1_CONTROL_REG0_TXRES_SHIFT                         1
#define UART1_CONTROL_REG0_TXRES_MASK                          0x00000002U

/*
* Software reset for Rx data path: 0: no affect 1: receiver logic is reset
    *  and all pending receiver data is discarded. This bit is self clearing o
    * nce the reset has completed.
*/
#undef UART1_CONTROL_REG0_RXRES_DEFVAL 
#undef UART1_CONTROL_REG0_RXRES_SHIFT 
#undef UART1_CONTROL_REG0_RXRES_MASK 
#define UART1_CONTROL_REG0_RXRES_DEFVAL                        0x00000128
#define UART1_CONTROL_REG0_RXRES_SHIFT                         0
#define UART1_CONTROL_REG0_RXRES_MASK                          0x00000001U

/*
* Channel mode: Defines the mode of operation of the UART. 00: normal 01:
    * automatic echo 10: local loopback 11: remote loopback
*/
#undef UART1_MODE_REG0_CHMODE_DEFVAL 
#undef UART1_MODE_REG0_CHMODE_SHIFT 
#undef UART1_MODE_REG0_CHMODE_MASK 
#define UART1_MODE_REG0_CHMODE_DEFVAL                          0x00000000
#define UART1_MODE_REG0_CHMODE_SHIFT                           8
#define UART1_MODE_REG0_CHMODE_MASK                            0x00000300U

/*
* Number of stop bits: Defines the number of stop bits to detect on receiv
    * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
    * op bits 11: reserved
*/
#undef UART1_MODE_REG0_NBSTOP_DEFVAL 
#undef UART1_MODE_REG0_NBSTOP_SHIFT 
#undef UART1_MODE_REG0_NBSTOP_MASK 
#define UART1_MODE_REG0_NBSTOP_DEFVAL                          0x00000000
#define UART1_MODE_REG0_NBSTOP_SHIFT                           6
#define UART1_MODE_REG0_NBSTOP_MASK                            0x000000C0U

/*
* Parity type select: Defines the expected parity to check on receive and
    * the parity to generate on transmit. 000: even parity 001: odd parity 010
    * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
    * ty
*/
#undef UART1_MODE_REG0_PAR_DEFVAL 
#undef UART1_MODE_REG0_PAR_SHIFT 
#undef UART1_MODE_REG0_PAR_MASK 
#define UART1_MODE_REG0_PAR_DEFVAL                             0x00000000
#define UART1_MODE_REG0_PAR_SHIFT                              3
#define UART1_MODE_REG0_PAR_MASK                               0x00000038U

/*
* Character length select: Defines the number of bits in each character. 1
    * 1: 6 bits 10: 7 bits 0x: 8 bits
*/
#undef UART1_MODE_REG0_CHRL_DEFVAL 
#undef UART1_MODE_REG0_CHRL_SHIFT 
#undef UART1_MODE_REG0_CHRL_MASK 
#define UART1_MODE_REG0_CHRL_DEFVAL                            0x00000000
#define UART1_MODE_REG0_CHRL_SHIFT                             1
#define UART1_MODE_REG0_CHRL_MASK                              0x00000006U

/*
* Clock source select: This field defines whether a pre-scalar of 8 is app
    * lied to the baud rate generator input clock. 0: clock source is uart_ref
    * _clk 1: clock source is uart_ref_clk/8
*/
#undef UART1_MODE_REG0_CLKS_DEFVAL 
#undef UART1_MODE_REG0_CLKS_SHIFT 
#undef UART1_MODE_REG0_CLKS_MASK 
#define UART1_MODE_REG0_CLKS_DEFVAL                            0x00000000
#define UART1_MODE_REG0_CLKS_SHIFT                             0
#define UART1_MODE_REG0_CLKS_MASK                              0x00000001U

/*
* Block level reset
*/
#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 
#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL                 0x0017FFFF
#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT                  18
#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK                   0x00040000U

/*
* TrustZone Classification for ADMA
*/
#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 
#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 
#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 
#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL                    
#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                     0
#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                      0x000000FFU

/*
* CSU regsiter
*/
#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_0_MASK 
#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT                       0
#define CSU_TAMPER_STATUS_TAMPER_0_MASK                        0x00000001U

/*
* External MIO
*/
#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_1_MASK 
#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT                       1
#define CSU_TAMPER_STATUS_TAMPER_1_MASK                        0x00000002U

/*
* JTAG toggle detect
*/
#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_2_MASK 
#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT                       2
#define CSU_TAMPER_STATUS_TAMPER_2_MASK                        0x00000004U

/*
* PL SEU error
*/
#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_3_MASK 
#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT                       3
#define CSU_TAMPER_STATUS_TAMPER_3_MASK                        0x00000008U

/*
* AMS over temperature alarm for LPD
*/
#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_4_MASK 
#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT                       4
#define CSU_TAMPER_STATUS_TAMPER_4_MASK                        0x00000010U

/*
* AMS over temperature alarm for APU
*/
#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_5_MASK 
#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT                       5
#define CSU_TAMPER_STATUS_TAMPER_5_MASK                        0x00000020U

/*
* AMS voltage alarm for VCCPINT_FPD
*/
#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_6_MASK 
#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT                       6
#define CSU_TAMPER_STATUS_TAMPER_6_MASK                        0x00000040U

/*
* AMS voltage alarm for VCCPINT_LPD
*/
#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_7_MASK 
#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT                       7
#define CSU_TAMPER_STATUS_TAMPER_7_MASK                        0x00000080U

/*
* AMS voltage alarm for VCCPAUX
*/
#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_8_MASK 
#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT                       8
#define CSU_TAMPER_STATUS_TAMPER_8_MASK                        0x00000100U

/*
* AMS voltage alarm for DDRPHY
*/
#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_9_MASK 
#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL                      0x00000000
#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT                       9
#define CSU_TAMPER_STATUS_TAMPER_9_MASK                        0x00000200U

/*
* AMS voltage alarm for PSIO bank 0/1/2
*/
#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_10_MASK 
#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL                     0x00000000
#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT                      10
#define CSU_TAMPER_STATUS_TAMPER_10_MASK                       0x00000400U

/*
* AMS voltage alarm for PSIO bank 3 (dedicated pins)
*/
#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_11_MASK 
#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL                     0x00000000
#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT                      11
#define CSU_TAMPER_STATUS_TAMPER_11_MASK                       0x00000800U

/*
* AMS voltaage alarm for GT
*/
#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 
#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT 
#undef CSU_TAMPER_STATUS_TAMPER_12_MASK 
#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL                     0x00000000
#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT                      12
#define CSU_TAMPER_STATUS_TAMPER_12_MASK                       0x00001000U

/*
* Set ACE outgoing AWQOS value
*/
#undef APU_ACE_CTRL_AWQOS_DEFVAL 
#undef APU_ACE_CTRL_AWQOS_SHIFT 
#undef APU_ACE_CTRL_AWQOS_MASK 
#define APU_ACE_CTRL_AWQOS_DEFVAL                              0x000F000F
#define APU_ACE_CTRL_AWQOS_SHIFT                               16
#define APU_ACE_CTRL_AWQOS_MASK                                0x000F0000U

/*
* Set ACE outgoing ARQOS value
*/
#undef APU_ACE_CTRL_ARQOS_DEFVAL 
#undef APU_ACE_CTRL_ARQOS_SHIFT 
#undef APU_ACE_CTRL_ARQOS_MASK 
#define APU_ACE_CTRL_ARQOS_DEFVAL                              0x000F000F
#define APU_ACE_CTRL_ARQOS_SHIFT                               0
#define APU_ACE_CTRL_ARQOS_MASK                                0x0000000FU

/*
* Enables the RTC. By writing a 0 to this bit, RTC will be powered off and
    *  the only module that potentially draws current from the battery will be
    *  BBRAM. The value read through this bit does not necessarily reflect whe
    * ther RTC is enabled or not. It is expected that RTC is enabled every tim
    * e it is being configured. If RTC is not used in the design, FSBL will di
    * sable it by writing a 0 to this bit.
*/
#undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL 
#undef RTC_CONTROL_BATTERY_DISABLE_SHIFT 
#undef RTC_CONTROL_BATTERY_DISABLE_MASK 
#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL                     0x01000000
#define RTC_CONTROL_BATTERY_DISABLE_SHIFT                      31
#define RTC_CONTROL_BATTERY_DISABLE_MASK                       0x80000000U

/*
* Frequency in number of ticks per second. Valid range from 10 MHz to 100
    * MHz.
*/
#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL 
#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 
#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 
#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL      
#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT       0
#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK        0xFFFFFFFFU

/*
* Enable 0: The counter is disabled and not incrementing. 1: The counter i
    * s enabled and is incrementing.
*/
#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 
#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 
#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 
#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL          0x00000000
#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT           0
#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK            0x00000001U

/*
* Operation is the same as DIRM_0[DIRECTION_0]
*/
#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL 
#undef GPIO_DIRM_1_DIRECTION_1_SHIFT 
#undef GPIO_DIRM_1_DIRECTION_1_MASK 
#define GPIO_DIRM_1_DIRECTION_1_DEFVAL                         0x00000000
#define GPIO_DIRM_1_DIRECTION_1_SHIFT                          0
#define GPIO_DIRM_1_DIRECTION_1_MASK                           0x03FFFFFFU

/*
* Operation is the same as OEN_0[OP_ENABLE_0]
*/
#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL 
#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT 
#undef GPIO_OEN_1_OP_ENABLE_1_MASK 
#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL                          0x00000000
#define GPIO_OEN_1_OP_ENABLE_1_SHIFT                           0
#define GPIO_OEN_1_OP_ENABLE_1_MASK                            0x03FFFFFFU

/*
* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
*/
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL                 0x00000000
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT                  16
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK                   0xFFFF0000U

/*
* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
*/
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL                 0x00000000
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT                  0
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK                   0x0000FFFFU

/*
* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
*/
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL                 0x00000000
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT                  16
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK                   0xFFFF0000U

/*
* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
*/
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL                 0x00000000
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT                  0
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK                   0x0000FFFFU
#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 
#define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET                                          0XFD690040
#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 
#define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET                                           0XFD690030
#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET 
#define LPD_SLCR_SECURE_SLCR_USB_OFFSET                                            0XFF4B0034
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET                                      0XFF240004
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET                                      0XFF240000
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET                                      0XFF240004
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET                                      0XFF240000
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET                                      0XFF240000
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET                                      0XFF240004
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET                                      0XFF240000
#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 
#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 
#define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET                                           0XFD690050

/*
* TrustZone classification for DisplayPort DMA
*/
#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 
#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL                   0x00000001
#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT                    0
#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK                     0x00000001U

/*
* TrustZone classification for DMA Channel 0
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL              0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT               21
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK                0x00200000U

/*
* TrustZone classification for DMA Channel 1
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL              0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT               22
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK                0x00400000U

/*
* TrustZone classification for DMA Channel 2
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL              0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT               23
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK                0x00800000U

/*
* TrustZone classification for DMA Channel 3
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL              0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT               24
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK                0x01000000U

/*
* TrustZone classification for Ingress Address Translation 0
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL          0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT           13
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK            0x00002000U

/*
* TrustZone classification for Ingress Address Translation 1
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL          0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT           14
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK            0x00004000U

/*
* TrustZone classification for Ingress Address Translation 2
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL          0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT           15
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK            0x00008000U

/*
* TrustZone classification for Ingress Address Translation 3
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL          0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT           16
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK            0x00010000U

/*
* TrustZone classification for Ingress Address Translation 4
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL          0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT           17
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK            0x00020000U

/*
* TrustZone classification for Ingress Address Translation 5
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL          0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT           18
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK            0x00040000U

/*
* TrustZone classification for Ingress Address Translation 6
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL          0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT           19
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK            0x00080000U

/*
* TrustZone classification for Ingress Address Translation 7
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL          0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT           20
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK            0x00100000U

/*
* TrustZone classification for Egress Address Translation 0
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT            5
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK             0x00000020U

/*
* TrustZone classification for Egress Address Translation 1
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT            6
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK             0x00000040U

/*
* TrustZone classification for Egress Address Translation 2
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT            7
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK             0x00000080U

/*
* TrustZone classification for Egress Address Translation 3
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT            8
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK             0x00000100U

/*
* TrustZone classification for Egress Address Translation 4
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT            9
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK             0x00000200U

/*
* TrustZone classification for Egress Address Translation 5
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT            10
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK             0x00000400U

/*
* TrustZone classification for Egress Address Translation 6
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT            11
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK             0x00000800U

/*
* TrustZone classification for Egress Address Translation 7
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT            12
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK             0x00001000U

/*
* TrustZone classification for DMA Registers
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT            4
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK             0x00000010U

/*
* TrustZone classification for MSIx Table
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL         0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT          2
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK           0x00000004U

/*
* TrustZone classification for MSIx PBA
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL           0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT            3
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK             0x00000008U

/*
* TrustZone classification for ECAM
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL               0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT                1
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK                 0x00000002U

/*
* TrustZone classification for Bridge Common Registers
*/
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL        0x01FFFFFF
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT         0
#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK          0x00000001U

/*
* TrustZone Classification for USB3_0
*/
#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 
#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 
#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 
#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL              0x00000003
#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT               0
#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK                0x00000001U

/*
* TrustZone Classification for USB3_1
*/
#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 
#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 
#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 
#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL              0x00000003
#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT               1
#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK                0x00000002U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL   0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT    16
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK     0x00070000U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL   0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT    19
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK     0x00380000U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL   0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT    16
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK     0x00070000U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL   0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT    19
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK     0x00380000U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT   0
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK    0x00000007U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT   3
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK    0x00000038U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT   6
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK    0x000001C0U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT   9
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK    0x00000E00U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT   0
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK    0x00000007U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT   3
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK    0x00000038U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT   6
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK    0x000001C0U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT   9
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK    0x00000E00U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT   25
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK    0x0E000000U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT   22
#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK    0x01C00000U

/*
* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [
    * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
    * ccess [2] = '1'' : Instruction access
*/
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 
#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL  0x00000000
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT   22
#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK    0x01C00000U

/*
* TrustZone Classification for ADMA
*/
#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 
#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 
#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 
#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL                    
#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                     0
#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                      0x000000FFU

/*
* TrustZone Classification for GDMA
*/
#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL 
#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 
#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 
#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL                    
#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT                     0
#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK                      0x000000FFU
#undef SERDES_PLL_REF_SEL0_OFFSET 
#define SERDES_PLL_REF_SEL0_OFFSET                                                 0XFD410000
#undef SERDES_PLL_REF_SEL1_OFFSET 
#define SERDES_PLL_REF_SEL1_OFFSET                                                 0XFD410004
#undef SERDES_PLL_REF_SEL2_OFFSET 
#define SERDES_PLL_REF_SEL2_OFFSET                                                 0XFD410008
#undef SERDES_PLL_REF_SEL3_OFFSET 
#define SERDES_PLL_REF_SEL3_OFFSET                                                 0XFD41000C
#undef SERDES_L0_L0_REF_CLK_SEL_OFFSET 
#define SERDES_L0_L0_REF_CLK_SEL_OFFSET                                            0XFD402860
#undef SERDES_L0_L1_REF_CLK_SEL_OFFSET 
#define SERDES_L0_L1_REF_CLK_SEL_OFFSET                                            0XFD402864
#undef SERDES_L0_L2_REF_CLK_SEL_OFFSET 
#define SERDES_L0_L2_REF_CLK_SEL_OFFSET                                            0XFD402868
#undef SERDES_L0_L3_REF_CLK_SEL_OFFSET 
#define SERDES_L0_L3_REF_CLK_SEL_OFFSET                                            0XFD40286C
#undef SERDES_L2_TM_PLL_DIG_37_OFFSET 
#define SERDES_L2_TM_PLL_DIG_37_OFFSET                                             0XFD40A094
#undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET 
#define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40A368
#undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET 
#define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40A36C
#undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 
#define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40E368
#undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 
#define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40E36C
#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 
#define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD406368
#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 
#define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40636C
#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD406370
#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 
#define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD406374
#undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 
#define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD406378
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40637C
#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40A370
#undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET 
#define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40A374
#undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET 
#define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40A378
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40A37C
#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40E370
#undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET 
#define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40E374
#undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET 
#define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40E378
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40E37C
#undef SERDES_L2_TM_DIG_6_OFFSET 
#define SERDES_L2_TM_DIG_6_OFFSET                                                  0XFD40906C
#undef SERDES_L2_TX_DIG_TM_61_OFFSET 
#define SERDES_L2_TX_DIG_TM_61_OFFSET                                              0XFD4080F4
#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET 
#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET                                      0XFD40E360
#undef SERDES_L3_TM_DIG_6_OFFSET 
#define SERDES_L3_TM_DIG_6_OFFSET                                                  0XFD40D06C
#undef SERDES_L3_TX_DIG_TM_61_OFFSET 
#define SERDES_L3_TX_DIG_TM_61_OFFSET                                              0XFD40C0F4
#undef SERDES_L0_TM_AUX_0_OFFSET 
#define SERDES_L0_TM_AUX_0_OFFSET                                                  0XFD4010CC
#undef SERDES_L2_TM_AUX_0_OFFSET 
#define SERDES_L2_TM_AUX_0_OFFSET                                                  0XFD4090CC
#undef SERDES_L0_TM_DIG_8_OFFSET 
#define SERDES_L0_TM_DIG_8_OFFSET                                                  0XFD401074
#undef SERDES_L1_TM_DIG_8_OFFSET 
#define SERDES_L1_TM_DIG_8_OFFSET                                                  0XFD405074
#undef SERDES_L2_TM_DIG_8_OFFSET 
#define SERDES_L2_TM_DIG_8_OFFSET                                                  0XFD409074
#undef SERDES_L3_TM_DIG_8_OFFSET 
#define SERDES_L3_TM_DIG_8_OFFSET                                                  0XFD40D074
#undef SERDES_L0_TM_MISC2_OFFSET 
#define SERDES_L0_TM_MISC2_OFFSET                                                  0XFD40189C
#undef SERDES_L0_TM_IQ_ILL1_OFFSET 
#define SERDES_L0_TM_IQ_ILL1_OFFSET                                                0XFD4018F8
#undef SERDES_L0_TM_IQ_ILL2_OFFSET 
#define SERDES_L0_TM_IQ_ILL2_OFFSET                                                0XFD4018FC
#undef SERDES_L0_TM_ILL12_OFFSET 
#define SERDES_L0_TM_ILL12_OFFSET                                                  0XFD401990
#undef SERDES_L0_TM_E_ILL1_OFFSET 
#define SERDES_L0_TM_E_ILL1_OFFSET                                                 0XFD401924
#undef SERDES_L0_TM_E_ILL2_OFFSET 
#define SERDES_L0_TM_E_ILL2_OFFSET                                                 0XFD401928
#undef SERDES_L0_TM_IQ_ILL3_OFFSET 
#define SERDES_L0_TM_IQ_ILL3_OFFSET                                                0XFD401900
#undef SERDES_L0_TM_E_ILL3_OFFSET 
#define SERDES_L0_TM_E_ILL3_OFFSET                                                 0XFD40192C
#undef SERDES_L0_TM_ILL8_OFFSET 
#define SERDES_L0_TM_ILL8_OFFSET                                                   0XFD401980
#undef SERDES_L0_TM_IQ_ILL8_OFFSET 
#define SERDES_L0_TM_IQ_ILL8_OFFSET                                                0XFD401914
#undef SERDES_L0_TM_IQ_ILL9_OFFSET 
#define SERDES_L0_TM_IQ_ILL9_OFFSET                                                0XFD401918
#undef SERDES_L0_TM_E_ILL8_OFFSET 
#define SERDES_L0_TM_E_ILL8_OFFSET                                                 0XFD401940
#undef SERDES_L0_TM_E_ILL9_OFFSET 
#define SERDES_L0_TM_E_ILL9_OFFSET                                                 0XFD401944
#undef SERDES_L0_TM_ILL13_OFFSET 
#define SERDES_L0_TM_ILL13_OFFSET                                                  0XFD401994
#undef SERDES_L1_TM_ILL13_OFFSET 
#define SERDES_L1_TM_ILL13_OFFSET                                                  0XFD405994
#undef SERDES_L2_TM_MISC2_OFFSET 
#define SERDES_L2_TM_MISC2_OFFSET                                                  0XFD40989C
#undef SERDES_L2_TM_IQ_ILL1_OFFSET 
#define SERDES_L2_TM_IQ_ILL1_OFFSET                                                0XFD4098F8
#undef SERDES_L2_TM_IQ_ILL2_OFFSET 
#define SERDES_L2_TM_IQ_ILL2_OFFSET                                                0XFD4098FC
#undef SERDES_L2_TM_ILL12_OFFSET 
#define SERDES_L2_TM_ILL12_OFFSET                                                  0XFD409990
#undef SERDES_L2_TM_E_ILL1_OFFSET 
#define SERDES_L2_TM_E_ILL1_OFFSET                                                 0XFD409924
#undef SERDES_L2_TM_E_ILL2_OFFSET 
#define SERDES_L2_TM_E_ILL2_OFFSET                                                 0XFD409928
#undef SERDES_L2_TM_IQ_ILL3_OFFSET 
#define SERDES_L2_TM_IQ_ILL3_OFFSET                                                0XFD409900
#undef SERDES_L2_TM_E_ILL3_OFFSET 
#define SERDES_L2_TM_E_ILL3_OFFSET                                                 0XFD40992C
#undef SERDES_L2_TM_ILL8_OFFSET 
#define SERDES_L2_TM_ILL8_OFFSET                                                   0XFD409980
#undef SERDES_L2_TM_IQ_ILL8_OFFSET 
#define SERDES_L2_TM_IQ_ILL8_OFFSET                                                0XFD409914
#undef SERDES_L2_TM_IQ_ILL9_OFFSET 
#define SERDES_L2_TM_IQ_ILL9_OFFSET                                                0XFD409918
#undef SERDES_L2_TM_E_ILL8_OFFSET 
#define SERDES_L2_TM_E_ILL8_OFFSET                                                 0XFD409940
#undef SERDES_L2_TM_E_ILL9_OFFSET 
#define SERDES_L2_TM_E_ILL9_OFFSET                                                 0XFD409944
#undef SERDES_L2_TM_ILL13_OFFSET 
#define SERDES_L2_TM_ILL13_OFFSET                                                  0XFD409994
#undef SERDES_L3_TM_MISC2_OFFSET 
#define SERDES_L3_TM_MISC2_OFFSET                                                  0XFD40D89C
#undef SERDES_L3_TM_IQ_ILL1_OFFSET 
#define SERDES_L3_TM_IQ_ILL1_OFFSET                                                0XFD40D8F8
#undef SERDES_L3_TM_IQ_ILL2_OFFSET 
#define SERDES_L3_TM_IQ_ILL2_OFFSET                                                0XFD40D8FC
#undef SERDES_L3_TM_ILL12_OFFSET 
#define SERDES_L3_TM_ILL12_OFFSET                                                  0XFD40D990
#undef SERDES_L3_TM_E_ILL1_OFFSET 
#define SERDES_L3_TM_E_ILL1_OFFSET                                                 0XFD40D924
#undef SERDES_L3_TM_E_ILL2_OFFSET 
#define SERDES_L3_TM_E_ILL2_OFFSET                                                 0XFD40D928
#undef SERDES_L3_TM_ILL11_OFFSET 
#define SERDES_L3_TM_ILL11_OFFSET                                                  0XFD40D98C
#undef SERDES_L3_TM_IQ_ILL3_OFFSET 
#define SERDES_L3_TM_IQ_ILL3_OFFSET                                                0XFD40D900
#undef SERDES_L3_TM_E_ILL3_OFFSET 
#define SERDES_L3_TM_E_ILL3_OFFSET                                                 0XFD40D92C
#undef SERDES_L3_TM_ILL8_OFFSET 
#define SERDES_L3_TM_ILL8_OFFSET                                                   0XFD40D980
#undef SERDES_L3_TM_IQ_ILL8_OFFSET 
#define SERDES_L3_TM_IQ_ILL8_OFFSET                                                0XFD40D914
#undef SERDES_L3_TM_IQ_ILL9_OFFSET 
#define SERDES_L3_TM_IQ_ILL9_OFFSET                                                0XFD40D918
#undef SERDES_L3_TM_E_ILL8_OFFSET 
#define SERDES_L3_TM_E_ILL8_OFFSET                                                 0XFD40D940
#undef SERDES_L3_TM_E_ILL9_OFFSET 
#define SERDES_L3_TM_E_ILL9_OFFSET                                                 0XFD40D944
#undef SERDES_L3_TM_ILL13_OFFSET 
#define SERDES_L3_TM_ILL13_OFFSET                                                  0XFD40D994
#undef SERDES_L0_TM_DIG_10_OFFSET 
#define SERDES_L0_TM_DIG_10_OFFSET                                                 0XFD40107C
#undef SERDES_L1_TM_DIG_10_OFFSET 
#define SERDES_L1_TM_DIG_10_OFFSET                                                 0XFD40507C
#undef SERDES_L2_TM_DIG_10_OFFSET 
#define SERDES_L2_TM_DIG_10_OFFSET                                                 0XFD40907C
#undef SERDES_L3_TM_DIG_10_OFFSET 
#define SERDES_L3_TM_DIG_10_OFFSET                                                 0XFD40D07C
#undef SERDES_L0_TM_RST_DLY_OFFSET 
#define SERDES_L0_TM_RST_DLY_OFFSET                                                0XFD4019A4
#undef SERDES_L0_TM_ANA_BYP_15_OFFSET 
#define SERDES_L0_TM_ANA_BYP_15_OFFSET                                             0XFD401038
#undef SERDES_L0_TM_ANA_BYP_12_OFFSET 
#define SERDES_L0_TM_ANA_BYP_12_OFFSET                                             0XFD40102C
#undef SERDES_L1_TM_RST_DLY_OFFSET 
#define SERDES_L1_TM_RST_DLY_OFFSET                                                0XFD4059A4
#undef SERDES_L1_TM_ANA_BYP_15_OFFSET 
#define SERDES_L1_TM_ANA_BYP_15_OFFSET                                             0XFD405038
#undef SERDES_L1_TM_ANA_BYP_12_OFFSET 
#define SERDES_L1_TM_ANA_BYP_12_OFFSET                                             0XFD40502C
#undef SERDES_L2_TM_RST_DLY_OFFSET 
#define SERDES_L2_TM_RST_DLY_OFFSET                                                0XFD4099A4
#undef SERDES_L2_TM_ANA_BYP_15_OFFSET 
#define SERDES_L2_TM_ANA_BYP_15_OFFSET                                             0XFD409038
#undef SERDES_L2_TM_ANA_BYP_12_OFFSET 
#define SERDES_L2_TM_ANA_BYP_12_OFFSET                                             0XFD40902C
#undef SERDES_L3_TM_RST_DLY_OFFSET 
#define SERDES_L3_TM_RST_DLY_OFFSET                                                0XFD40D9A4
#undef SERDES_L3_TM_ANA_BYP_15_OFFSET 
#define SERDES_L3_TM_ANA_BYP_15_OFFSET                                             0XFD40D038
#undef SERDES_L3_TM_ANA_BYP_12_OFFSET 
#define SERDES_L3_TM_ANA_BYP_12_OFFSET                                             0XFD40D02C
#undef SERDES_L0_TM_MISC3_OFFSET 
#define SERDES_L0_TM_MISC3_OFFSET                                                  0XFD4019AC
#undef SERDES_L1_TM_MISC3_OFFSET 
#define SERDES_L1_TM_MISC3_OFFSET                                                  0XFD4059AC
#undef SERDES_L2_TM_MISC3_OFFSET 
#define SERDES_L2_TM_MISC3_OFFSET                                                  0XFD4099AC
#undef SERDES_L3_TM_MISC3_OFFSET 
#define SERDES_L3_TM_MISC3_OFFSET                                                  0XFD40D9AC
#undef SERDES_L0_TM_EQ11_OFFSET 
#define SERDES_L0_TM_EQ11_OFFSET                                                   0XFD401978
#undef SERDES_L1_TM_EQ11_OFFSET 
#define SERDES_L1_TM_EQ11_OFFSET                                                   0XFD405978
#undef SERDES_L2_TM_EQ11_OFFSET 
#define SERDES_L2_TM_EQ11_OFFSET                                                   0XFD409978
#undef SERDES_L3_TM_EQ11_OFFSET 
#define SERDES_L3_TM_EQ11_OFFSET                                                   0XFD40D978
#undef SIOU_ECO_0_OFFSET 
#define SIOU_ECO_0_OFFSET                                                          0XFD3D001C
#undef SERDES_ICM_CFG0_OFFSET 
#define SERDES_ICM_CFG0_OFFSET                                                     0XFD410010
#undef SERDES_ICM_CFG1_OFFSET 
#define SERDES_ICM_CFG1_OFFSET                                                     0XFD410014
#undef SERDES_L1_TXPMD_TM_45_OFFSET 
#define SERDES_L1_TXPMD_TM_45_OFFSET                                               0XFD404CB4
#undef SERDES_L1_TX_ANA_TM_118_OFFSET 
#define SERDES_L1_TX_ANA_TM_118_OFFSET                                             0XFD4041D8
#undef SERDES_L3_TX_ANA_TM_118_OFFSET 
#define SERDES_L3_TX_ANA_TM_118_OFFSET                                             0XFD40C1D8
#undef SERDES_L3_TM_CDR5_OFFSET 
#define SERDES_L3_TM_CDR5_OFFSET                                                   0XFD40DC14
#undef SERDES_L3_TM_CDR16_OFFSET 
#define SERDES_L3_TM_CDR16_OFFSET                                                  0XFD40DC40
#undef SERDES_L3_TM_EQ0_OFFSET 
#define SERDES_L3_TM_EQ0_OFFSET                                                    0XFD40D94C
#undef SERDES_L3_TM_EQ1_OFFSET 
#define SERDES_L3_TM_EQ1_OFFSET                                                    0XFD40D950
#undef SERDES_L1_TXPMD_TM_48_OFFSET 
#define SERDES_L1_TXPMD_TM_48_OFFSET                                               0XFD404CC0
#undef SERDES_L1_TX_ANA_TM_18_OFFSET 
#define SERDES_L1_TX_ANA_TM_18_OFFSET                                              0XFD404048
#undef SERDES_L3_TX_ANA_TM_18_OFFSET 
#define SERDES_L3_TX_ANA_TM_18_OFFSET                                              0XFD40C048

/*
* PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
    * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
    *  0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
    *  - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
    * eserved
*/
#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 
#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 
#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 
#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL                  0x0000000D
#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT                   0
#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK                    0x0000001FU

/*
* PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
    * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
    *  0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
    *  - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
    * eserved
*/
#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 
#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 
#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 
#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL                  0x00000008
#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT                   0
#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK                    0x0000001FU

/*
* PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
    * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
    *  0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
    *  - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
    * eserved
*/
#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 
#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 
#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 
#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL                  0x0000000F
#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT                   0
#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK                    0x0000001FU

/*
* PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1
    * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
    *  0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE
    *  - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
    * eserved
*/
#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 
#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 
#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 
#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL                  0x0000000E
#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT                   0
#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK                    0x0000001FU

/*
* Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp
    * ut. Set to 0 to select lane0 ref clock mux output.
*/
#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 
#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 
#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 
#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL     0x00000080
#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT      7
#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK       0x00000080U

/*
* Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp
    * ut. Set to 0 to select lane1 ref clock mux output.
*/
#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 
#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 
#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 
#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL     0x00000080
#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT      7
#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK       0x00000080U

/*
* Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli
    * cer output from ref clock network
*/
#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 
#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 
#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 
#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL       0x00000080
#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT        3
#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK         0x00000008U

/*
* Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp
    * ut. Set to 0 to select lane2 ref clock mux output.
*/
#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 
#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 
#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 
#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL     0x00000080
#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT      7
#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK       0x00000080U

/*
* Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp
    * ut. Set to 0 to select lane3 ref clock mux output.
*/
#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 
#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 
#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 
#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL     0x00000080
#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT      7
#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK       0x00000080U

/*
* Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli
    * cer output from ref clock network
*/
#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 
#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 
#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 
#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL       0x00000080
#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT        1
#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK         0x00000002U

/*
* Enable/Disable coarse code satureation limiting logic
*/
#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 
#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 
#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 
#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL  0x00000000
#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT  4
#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK  0x00000010U

/*
* Spread Spectrum No of Steps [7:0]
*/
#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL  0x00000000
#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT  0
#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK  0x000000FFU

/*
* Spread Spectrum No of Steps [10:8]
*/
#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL  0x00000000
#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT  0
#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK  0x00000007U

/*
* Spread Spectrum No of Steps [7:0]
*/
#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL  0x00000000
#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT  0
#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK  0x000000FFU

/*
* Spread Spectrum No of Steps [10:8]
*/
#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL  0x00000000
#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT  0
#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK  0x00000007U

/*
* Spread Spectrum No of Steps [7:0]
*/
#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL  0x00000000
#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT  0
#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK  0x000000FFU

/*
* Spread Spectrum No of Steps [10:8]
*/
#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL  0x00000000
#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT  0
#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK  0x00000007U

/*
* Step Size for Spread Spectrum [7:0]
*/
#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL  0x00000000
#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT  0
#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK  0x000000FFU

/*
* Step Size for Spread Spectrum [15:8]
*/
#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL     0x00000000
#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT      0
#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK       0x000000FFU

/*
* Step Size for Spread Spectrum [23:16]
*/
#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL     0x00000000
#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT      0
#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK       0x000000FFU

/*
* Step Size for Spread Spectrum [25:24]
*/
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL  0x00000000
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT  0
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK  0x00000003U

/*
* Enable/Disable test mode force on SS step size
*/
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL  0x00000000
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT  4
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK  0x00000010U

/*
* Enable/Disable test mode force on SS no of steps
*/
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL  0x00000000
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT  5
#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK  0x00000020U

/*
* Step Size for Spread Spectrum [7:0]
*/
#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL  0x00000000
#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT  0
#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK  0x000000FFU

/*
* Step Size for Spread Spectrum [15:8]
*/
#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL     0x00000000
#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT      0
#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK       0x000000FFU

/*
* Step Size for Spread Spectrum [23:16]
*/
#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL     0x00000000
#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT      0
#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK       0x000000FFU

/*
* Step Size for Spread Spectrum [25:24]
*/
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL  0x00000000
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT  0
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK  0x00000003U

/*
* Enable/Disable test mode force on SS step size
*/
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL  0x00000000
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT  4
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK  0x00000010U

/*
* Enable/Disable test mode force on SS no of steps
*/
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL  0x00000000
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT  5
#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK  0x00000020U

/*
* Step Size for Spread Spectrum [7:0]
*/
#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL  0x00000000
#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT  0
#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK  0x000000FFU

/*
* Step Size for Spread Spectrum [15:8]
*/
#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL     0x00000000
#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT      0
#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK       0x000000FFU

/*
* Step Size for Spread Spectrum [23:16]
*/
#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL     0x00000000
#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT      0
#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK       0x000000FFU

/*
* Step Size for Spread Spectrum [25:24]
*/
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL  0x00000000
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT  0
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK  0x00000003U

/*
* Enable/Disable test mode force on SS step size
*/
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL  0x00000000
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT  4
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK  0x00000010U

/*
* Enable/Disable test mode force on SS no of steps
*/
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL  0x00000000
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT  5
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK  0x00000020U

/*
* Enable test mode forcing on enable Spread Spectrum
*/
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 
#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL  0x00000000
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT  7
#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK   0x00000080U

/*
* Bypass Descrambler
*/
#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 
#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 
#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 
#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL               0x00000000
#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT                1
#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK                 0x00000002U

/*
* Enable Bypass for <1> TM_DIG_CTRL_6
*/
#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 
#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 
#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 
#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL         0x00000000
#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT          0
#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK           0x00000001U

/*
* Bypass scrambler signal
*/
#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 
#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 
#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 
#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL             0x00000000
#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT              1
#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK               0x00000002U

/*
* Enable/disable scrambler bypass signal
*/
#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 
#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 
#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 
#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL       0x00000000
#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT        0
#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK         0x00000001U

/*
* Enable test mode force on fractional mode enable
*/
#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 
#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 
#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 
#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL  0x00000000
#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT  6
#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK   0x00000040U

/*
* Bypass 8b10b decoder
*/
#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 
#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 
#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 
#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL               0x00000000
#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT                3
#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK                 0x00000008U

/*
* Enable Bypass for <3> TM_DIG_CTRL_6
*/
#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 
#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 
#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 
#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL             0x00000000
#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT              2
#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK               0x00000004U

/*
* Bypass Descrambler
*/
#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 
#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 
#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 
#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL               0x00000000
#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT                1
#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK                 0x00000002U

/*
* Enable Bypass for <1> TM_DIG_CTRL_6
*/
#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 
#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 
#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 
#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL         0x00000000
#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT          0
#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK           0x00000001U

/*
* Enable/disable encoder bypass signal
*/
#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 
#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 
#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 
#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL               0x00000000
#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT                3
#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK                 0x00000008U

/*
* Bypass scrambler signal
*/
#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 
#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 
#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 
#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL             0x00000000
#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT              1
#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK               0x00000002U

/*
* Enable/disable scrambler bypass signal
*/
#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 
#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 
#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 
#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL       0x00000000
#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT        0
#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK         0x00000001U

/*
* Spare- not used
*/
#undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 
#undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT 
#undef SERDES_L0_TM_AUX_0_BIT_2_MASK 
#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL                        0x00000000
#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT                         5
#define SERDES_L0_TM_AUX_0_BIT_2_MASK                          0x00000020U

/*
* Spare- not used
*/
#undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 
#undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT 
#undef SERDES_L2_TM_AUX_0_BIT_2_MASK 
#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL                        0x00000000
#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT                         5
#define SERDES_L2_TM_AUX_0_BIT_2_MASK                          0x00000020U

/*
* Enable Eye Surf
*/
#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 
#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 
#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 
#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL               0x00000000
#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT                4
#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK                 0x00000010U

/*
* Enable Eye Surf
*/
#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 
#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 
#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 
#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL               0x00000000
#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT                4
#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK                 0x00000010U

/*
* Enable Eye Surf
*/
#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 
#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 
#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 
#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL               0x00000000
#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT                4
#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK                 0x00000010U

/*
* Enable Eye Surf
*/
#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 
#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 
#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 
#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL               0x00000000
#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT                4
#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK                 0x00000010U

/*
* ILL calib counts BYPASSED with calcode bits
*/
#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 
#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 
#undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 
#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL        0x00000000
#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT         7
#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK          0x00000080U

/*
* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
    * USB3 : SS
*/
#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 
#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 
#undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 
#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL   0x00000000
#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT    0
#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK     0x000000FFU

/*
* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
*/
#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 
#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 
#undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 
#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL   0x00000000
#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT    0
#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK     0x000000FFU

/*
* G1A pll ctr bypass value
*/
#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 
#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 
#undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 
#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL          0x00000000
#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT           0
#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK            0x000000FFU

/*
* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
    * SB3 : SS
*/
#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 
#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 
#undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 
#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL     0x00000000
#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT      0
#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK       0x000000FFU

/*
* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
*/
#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 
#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 
#undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 
#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL     0x00000000
#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT      0
#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK       0x000000FFU

/*
* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
*/
#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 
#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 
#undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 
#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL   0x00000000
#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT    0
#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK     0x000000FFU

/*
* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
*/
#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 
#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 
#undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 
#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL     0x00000000
#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT      0
#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK       0x000000FFU

/*
* ILL calibration code change wait time
*/
#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 
#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 
#undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 
#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL             0x00000002
#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT              0
#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK               0x000000FFU

/*
* IQ ILL polytrim bypass value
*/
#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 
#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 
#undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 
#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL  0x00000000
#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT  0
#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK   0x000000FFU

/*
* bypass IQ polytrim
*/
#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 
#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 
#undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 
#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL      0x00000000
#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT       0
#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK        0x00000001U

/*
* E ILL polytrim bypass value
*/
#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 
#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 
#undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 
#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL   0x00000000
#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT    0
#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK     0x000000FFU

/*
* bypass E polytrim
*/
#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 
#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 
#undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 
#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL        0x00000000
#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT         0
#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK          0x00000001U

/*
* ILL cal idle val refcnt
*/
#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 
#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 
#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 
#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL      0x00000001
#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT       0
#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK        0x00000007U

/*
* ILL cal idle val refcnt
*/
#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 
#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 
#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 
#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL      0x00000001
#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT       0
#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK        0x00000007U

/*
* ILL calib counts BYPASSED with calcode bits
*/
#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 
#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 
#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 
#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL        0x00000000
#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT         7
#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK          0x00000080U

/*
* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
    * USB3 : SS
*/
#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 
#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 
#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 
#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL   0x00000000
#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT    0
#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK     0x000000FFU

/*
* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
*/
#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 
#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 
#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 
#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL   0x00000000
#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT    0
#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK     0x000000FFU

/*
* G1A pll ctr bypass value
*/
#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 
#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 
#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 
#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL          0x00000000
#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT           0
#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK            0x000000FFU

/*
* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
    * SB3 : SS
*/
#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 
#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 
#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 
#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL     0x00000000
#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT      0
#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK       0x000000FFU

/*
* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
*/
#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 
#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 
#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 
#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL     0x00000000
#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT      0
#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK       0x000000FFU

/*
* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
*/
#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 
#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 
#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 
#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL   0x00000000
#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT    0
#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK     0x000000FFU

/*
* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
*/
#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 
#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 
#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 
#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL     0x00000000
#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT      0
#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK       0x000000FFU

/*
* ILL calibration code change wait time
*/
#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 
#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 
#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 
#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL             0x00000002
#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT              0
#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK               0x000000FFU

/*
* IQ ILL polytrim bypass value
*/
#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 
#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 
#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 
#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL  0x00000000
#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT  0
#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK   0x000000FFU

/*
* bypass IQ polytrim
*/
#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 
#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 
#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 
#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL      0x00000000
#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT       0
#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK        0x00000001U

/*
* E ILL polytrim bypass value
*/
#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 
#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 
#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 
#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL   0x00000000
#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT    0
#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK     0x000000FFU

/*
* bypass E polytrim
*/
#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 
#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 
#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 
#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL        0x00000000
#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT         0
#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK          0x00000001U

/*
* ILL cal idle val refcnt
*/
#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 
#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 
#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 
#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL      0x00000001
#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT       0
#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK        0x00000007U

/*
* ILL calib counts BYPASSED with calcode bits
*/
#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 
#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 
#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 
#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL        0x00000000
#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT         7
#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK          0x00000080U

/*
* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
    * USB3 : SS
*/
#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 
#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 
#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 
#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL   0x00000000
#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT    0
#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK     0x000000FFU

/*
* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
*/
#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 
#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 
#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 
#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL   0x00000000
#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT    0
#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK     0x000000FFU

/*
* G1A pll ctr bypass value
*/
#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 
#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 
#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 
#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL          0x00000000
#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT           0
#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK            0x000000FFU

/*
* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
    * SB3 : SS
*/
#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 
#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 
#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 
#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL     0x00000000
#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT      0
#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK       0x000000FFU

/*
* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
*/
#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 
#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 
#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 
#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL     0x00000000
#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT      0
#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK       0x000000FFU

/*
* G2A_PCIe1 PLL ctr bypass value
*/
#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 
#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 
#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 
#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL  0x00000000
#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT  4
#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK  0x000000F0U

/*
* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
*/
#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 
#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 
#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 
#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL   0x00000000
#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT    0
#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK     0x000000FFU

/*
* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
*/
#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 
#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 
#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 
#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL     0x00000000
#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT      0
#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK       0x000000FFU

/*
* ILL calibration code change wait time
*/
#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 
#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 
#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 
#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL             0x00000002
#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT              0
#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK               0x000000FFU

/*
* IQ ILL polytrim bypass value
*/
#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 
#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 
#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 
#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL  0x00000000
#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT  0
#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK   0x000000FFU

/*
* bypass IQ polytrim
*/
#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 
#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 
#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 
#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL      0x00000000
#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT       0
#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK        0x00000001U

/*
* E ILL polytrim bypass value
*/
#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 
#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 
#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 
#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL   0x00000000
#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT    0
#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK     0x000000FFU

/*
* bypass E polytrim
*/
#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 
#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 
#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 
#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL        0x00000000
#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT         0
#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK          0x00000001U

/*
* ILL cal idle val refcnt
*/
#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 
#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 
#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 
#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL      0x00000001
#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT       0
#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK        0x00000007U

/*
* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
*/
#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 
#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 
#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 
#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL           0x00000001
#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT            0
#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK             0x0000000FU

/*
* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
*/
#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 
#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 
#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 
#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL           0x00000001
#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT            0
#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK             0x0000000FU

/*
* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
*/
#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 
#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 
#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 
#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL           0x00000001
#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT            0
#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK             0x0000000FU

/*
* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
*/
#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 
#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 
#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 
#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL           0x00000001
#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT            0
#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK             0x0000000FU

/*
* Delay apb reset by specified amount
*/
#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 
#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 
#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 
#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL                0x00000000
#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT                 0
#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK                  0x000000FFU

/*
* Enable Bypass for <7> of TM_ANA_BYPS_15
*/
#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 
#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 
#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 
#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL  0x00000000
#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT  6
#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK  0x00000040U

/*
* Enable Bypass for <7> of TM_ANA_BYPS_12
*/
#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 
#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 
#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 
#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL  0x00000000
#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT   6
#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK    0x00000040U

/*
* Delay apb reset by specified amount
*/
#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 
#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 
#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 
#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL                0x00000000
#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT                 0
#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK                  0x000000FFU

/*
* Enable Bypass for <7> of TM_ANA_BYPS_15
*/
#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 
#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 
#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 
#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL  0x00000000
#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT  6
#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK  0x00000040U

/*
* Enable Bypass for <7> of TM_ANA_BYPS_12
*/
#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 
#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 
#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 
#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL  0x00000000
#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT   6
#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK    0x00000040U

/*
* Delay apb reset by specified amount
*/
#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 
#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 
#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 
#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL                0x00000000
#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT                 0
#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK                  0x000000FFU

/*
* Enable Bypass for <7> of TM_ANA_BYPS_15
*/
#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 
#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 
#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 
#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL  0x00000000
#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT  6
#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK  0x00000040U

/*
* Enable Bypass for <7> of TM_ANA_BYPS_12
*/
#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 
#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 
#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 
#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL  0x00000000
#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT   6
#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK    0x00000040U

/*
* Delay apb reset by specified amount
*/
#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 
#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 
#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 
#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL                0x00000000
#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT                 0
#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK                  0x000000FFU

/*
* Enable Bypass for <7> of TM_ANA_BYPS_15
*/
#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 
#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 
#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 
#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL  0x00000000
#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT  6
#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK  0x00000040U

/*
* Enable Bypass for <7> of TM_ANA_BYPS_12
*/
#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 
#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 
#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 
#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL  0x00000000
#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT   6
#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK    0x00000040U

/*
* CDR fast phase lock control
*/
#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 
#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 
#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 
#define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL                   0x00000003
#define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT                    1
#define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK                     0x00000002U

/*
* CDR fast frequency lock control
*/
#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 
#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 
#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 
#define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL                   0x00000003
#define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT                    0
#define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK                     0x00000001U

/*
* CDR fast phase lock control
*/
#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 
#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 
#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 
#define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL                   0x00000003
#define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT                    1
#define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK                     0x00000002U

/*
* CDR fast frequency lock control
*/
#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 
#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 
#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 
#define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL                   0x00000003
#define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT                    0
#define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK                     0x00000001U

/*
* CDR fast phase lock control
*/
#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 
#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 
#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 
#define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL                   0x00000003
#define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT                    1
#define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK                     0x00000002U

/*
* CDR fast frequency lock control
*/
#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 
#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 
#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 
#define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL                   0x00000003
#define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT                    0
#define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK                     0x00000001U

/*
* CDR fast phase lock control
*/
#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 
#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 
#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 
#define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL                   0x00000003
#define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT                    1
#define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK                     0x00000002U

/*
* CDR fast frequency lock control
*/
#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 
#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 
#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 
#define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL                   0x00000003
#define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT                    0
#define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK                     0x00000001U

/*
* Force EQ offset correction algo off if not forced on
*/
#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 
#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 
#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 
#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL             0x00000000
#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT              4
#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK               0x00000010U

/*
* Force EQ offset correction algo off if not forced on
*/
#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 
#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 
#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 
#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL             0x00000000
#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT              4
#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK               0x00000010U

/*
* Force EQ offset correction algo off if not forced on
*/
#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 
#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 
#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 
#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL             0x00000000
#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT              4
#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK               0x00000010U

/*
* Force EQ offset correction algo off if not forced on
*/
#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 
#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 
#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 
#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL             0x00000000
#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT              4
#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK               0x00000010U

/*
* For future use
*/
#undef SIOU_ECO_0_FIELD_DEFVAL 
#undef SIOU_ECO_0_FIELD_SHIFT 
#undef SIOU_ECO_0_FIELD_MASK 
#define SIOU_ECO_0_FIELD_DEFVAL                                
#define SIOU_ECO_0_FIELD_SHIFT                                 0
#define SIOU_ECO_0_FIELD_MASK                                  0xFFFFFFFFU

/*
* Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0,
    *  2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused
*/
#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 
#undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 
#undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK 
#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL                      0x00000000
#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT                       0
#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK                        0x00000007U

/*
* Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
    * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused
*/
#undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 
#undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 
#undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK 
#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL                      0x00000000
#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT                       4
#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK                        0x00000070U

/*
* Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
    * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused
*/
#undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 
#undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 
#undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK 
#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL                      0x00000000
#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT                       0
#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK                        0x00000007U

/*
* Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3,
    * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused
*/
#undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 
#undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 
#undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK 
#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL                      0x00000000
#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT                       4
#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK                        0x00000070U

/*
* Enable/disable DP post2 path
*/
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL  0x00000000
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT  5
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK  0x00000020U

/*
* Override enable/disable of DP post2 path
*/
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL  0x00000000
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT  4
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK  0x00000010U

/*
* Override enable/disable of DP post1 path
*/
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL  0x00000000
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT  2
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK  0x00000004U

/*
* Enable/disable DP main path
*/
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL  0x00000000
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT  1
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK  0x00000002U

/*
* Override enable/disable of DP main path
*/
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 
#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL  0x00000000
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT  0
#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK  0x00000001U

/*
* Test register force for enabling/disablign TX deemphasis bits <17:0>
*/
#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 
#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 
#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 
#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL    0x00000000
#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT     0
#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK      0x00000001U

/*
* Test register force for enabling/disablign TX deemphasis bits <17:0>
*/
#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 
#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 
#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 
#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL    0x00000000
#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT     0
#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK      0x00000001U

/*
* FPHL FSM accumulate cycles
*/
#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 
#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 
#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 
#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL           0x00000000
#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT            5
#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK             0x000000E0U

/*
* FFL Phase0 int gain aka 2ol SD update rate
*/
#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 
#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 
#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 
#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL              0x00000000
#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT               0
#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK                0x0000001FU

/*
* FFL Phase0 prop gain aka 1ol SD update rate
*/
#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 
#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 
#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 
#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL            0x00000000
#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT             0
#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK              0x0000001FU

/*
* EQ stg 2 controls BYPASSED
*/
#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 
#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 
#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 
#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL               0x00000000
#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT                5
#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK                 0x00000020U

/*
* EQ STG2 RL PROG
*/
#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 
#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 
#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 
#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL                0x00000000
#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT                 0
#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK                  0x00000003U

/*
* EQ stg 2 preamp mode val
*/
#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 
#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 
#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 
#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL        0x00000000
#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT         2
#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK          0x00000004U

/*
* Margining factor value
*/
#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 
#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 
#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 
#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL  0x00000000
#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT  0
#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK  0x0000001FU

/*
* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
    * phasis, Others: reserved
*/
#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 
#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 
#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL       0x00000002
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT        0
#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK         0x000000FFU

/*
* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
    * phasis, Others: reserved
*/
#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 
#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 
#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 
#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL       0x00000002
#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT        0
#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK         0x000000FFU
#undef CRL_APB_RST_LPD_TOP_OFFSET 
#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
#undef CRL_APB_RST_LPD_TOP_OFFSET 
#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET 
#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
#undef SIOU_SATA_MISC_CTRL_OFFSET 
#define SIOU_SATA_MISC_CTRL_OFFSET                                                 0XFD3D0100
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
#undef DP_DP_PHY_RESET_OFFSET 
#define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 
#define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
#undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET 
#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET                                             0XFE20C200
#undef USB3_0_XHCI_GFLADJ_OFFSET 
#define USB3_0_XHCI_GFLADJ_OFFSET                                                  0XFE20C630
#undef USB3_0_XHCI_GUCTL1_OFFSET 
#define USB3_0_XHCI_GUCTL1_OFFSET                                                  0XFE20C11C
#undef USB3_0_XHCI_GUCTL_OFFSET 
#define USB3_0_XHCI_GUCTL_OFFSET                                                   0XFE20C12C
#undef PCIE_ATTRIB_ATTR_25_OFFSET 
#define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
#undef PCIE_ATTRIB_ATTR_7_OFFSET 
#define PCIE_ATTRIB_ATTR_7_OFFSET                                                  0XFD48001C
#undef PCIE_ATTRIB_ATTR_8_OFFSET 
#define PCIE_ATTRIB_ATTR_8_OFFSET                                                  0XFD480020
#undef PCIE_ATTRIB_ATTR_9_OFFSET 
#define PCIE_ATTRIB_ATTR_9_OFFSET                                                  0XFD480024
#undef PCIE_ATTRIB_ATTR_10_OFFSET 
#define PCIE_ATTRIB_ATTR_10_OFFSET                                                 0XFD480028
#undef PCIE_ATTRIB_ATTR_11_OFFSET 
#define PCIE_ATTRIB_ATTR_11_OFFSET                                                 0XFD48002C
#undef PCIE_ATTRIB_ATTR_12_OFFSET 
#define PCIE_ATTRIB_ATTR_12_OFFSET                                                 0XFD480030
#undef PCIE_ATTRIB_ATTR_13_OFFSET 
#define PCIE_ATTRIB_ATTR_13_OFFSET                                                 0XFD480034
#undef PCIE_ATTRIB_ATTR_14_OFFSET 
#define PCIE_ATTRIB_ATTR_14_OFFSET                                                 0XFD480038
#undef PCIE_ATTRIB_ATTR_15_OFFSET 
#define PCIE_ATTRIB_ATTR_15_OFFSET                                                 0XFD48003C
#undef PCIE_ATTRIB_ATTR_16_OFFSET 
#define PCIE_ATTRIB_ATTR_16_OFFSET                                                 0XFD480040
#undef PCIE_ATTRIB_ATTR_17_OFFSET 
#define PCIE_ATTRIB_ATTR_17_OFFSET                                                 0XFD480044
#undef PCIE_ATTRIB_ATTR_18_OFFSET 
#define PCIE_ATTRIB_ATTR_18_OFFSET                                                 0XFD480048
#undef PCIE_ATTRIB_ATTR_27_OFFSET 
#define PCIE_ATTRIB_ATTR_27_OFFSET                                                 0XFD48006C
#undef PCIE_ATTRIB_ATTR_50_OFFSET 
#define PCIE_ATTRIB_ATTR_50_OFFSET                                                 0XFD4800C8
#undef PCIE_ATTRIB_ATTR_105_OFFSET 
#define PCIE_ATTRIB_ATTR_105_OFFSET                                                0XFD4801A4
#undef PCIE_ATTRIB_ATTR_106_OFFSET 
#define PCIE_ATTRIB_ATTR_106_OFFSET                                                0XFD4801A8
#undef PCIE_ATTRIB_ATTR_107_OFFSET 
#define PCIE_ATTRIB_ATTR_107_OFFSET                                                0XFD4801AC
#undef PCIE_ATTRIB_ATTR_108_OFFSET 
#define PCIE_ATTRIB_ATTR_108_OFFSET                                                0XFD4801B0
#undef PCIE_ATTRIB_ATTR_109_OFFSET 
#define PCIE_ATTRIB_ATTR_109_OFFSET                                                0XFD4801B4
#undef PCIE_ATTRIB_ATTR_34_OFFSET 
#define PCIE_ATTRIB_ATTR_34_OFFSET                                                 0XFD480088
#undef PCIE_ATTRIB_ATTR_53_OFFSET 
#define PCIE_ATTRIB_ATTR_53_OFFSET                                                 0XFD4800D4
#undef PCIE_ATTRIB_ATTR_41_OFFSET 
#define PCIE_ATTRIB_ATTR_41_OFFSET                                                 0XFD4800A4
#undef PCIE_ATTRIB_ATTR_97_OFFSET 
#define PCIE_ATTRIB_ATTR_97_OFFSET                                                 0XFD480184
#undef PCIE_ATTRIB_ATTR_100_OFFSET 
#define PCIE_ATTRIB_ATTR_100_OFFSET                                                0XFD480190
#undef PCIE_ATTRIB_ATTR_101_OFFSET 
#define PCIE_ATTRIB_ATTR_101_OFFSET                                                0XFD480194
#undef PCIE_ATTRIB_ATTR_37_OFFSET 
#define PCIE_ATTRIB_ATTR_37_OFFSET                                                 0XFD480094
#undef PCIE_ATTRIB_ATTR_93_OFFSET 
#define PCIE_ATTRIB_ATTR_93_OFFSET                                                 0XFD480174
#undef PCIE_ATTRIB_ID_OFFSET 
#define PCIE_ATTRIB_ID_OFFSET                                                      0XFD480200
#undef PCIE_ATTRIB_SUBSYS_ID_OFFSET 
#define PCIE_ATTRIB_SUBSYS_ID_OFFSET                                               0XFD480204
#undef PCIE_ATTRIB_REV_ID_OFFSET 
#define PCIE_ATTRIB_REV_ID_OFFSET                                                  0XFD480208
#undef PCIE_ATTRIB_ATTR_24_OFFSET 
#define PCIE_ATTRIB_ATTR_24_OFFSET                                                 0XFD480060
#undef PCIE_ATTRIB_ATTR_25_OFFSET 
#define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
#undef PCIE_ATTRIB_ATTR_4_OFFSET 
#define PCIE_ATTRIB_ATTR_4_OFFSET                                                  0XFD480010
#undef PCIE_ATTRIB_ATTR_89_OFFSET 
#define PCIE_ATTRIB_ATTR_89_OFFSET                                                 0XFD480164
#undef PCIE_ATTRIB_ATTR_79_OFFSET 
#define PCIE_ATTRIB_ATTR_79_OFFSET                                                 0XFD48013C
#undef PCIE_ATTRIB_ATTR_43_OFFSET 
#define PCIE_ATTRIB_ATTR_43_OFFSET                                                 0XFD4800AC
#undef PCIE_ATTRIB_ATTR_48_OFFSET 
#define PCIE_ATTRIB_ATTR_48_OFFSET                                                 0XFD4800C0
#undef PCIE_ATTRIB_ATTR_46_OFFSET 
#define PCIE_ATTRIB_ATTR_46_OFFSET                                                 0XFD4800B8
#undef PCIE_ATTRIB_ATTR_47_OFFSET 
#define PCIE_ATTRIB_ATTR_47_OFFSET                                                 0XFD4800BC
#undef PCIE_ATTRIB_ATTR_44_OFFSET 
#define PCIE_ATTRIB_ATTR_44_OFFSET                                                 0XFD4800B0
#undef PCIE_ATTRIB_ATTR_45_OFFSET 
#define PCIE_ATTRIB_ATTR_45_OFFSET                                                 0XFD4800B4
#undef PCIE_ATTRIB_CB_OFFSET 
#define PCIE_ATTRIB_CB_OFFSET                                                      0XFD48031C
#undef PCIE_ATTRIB_ATTR_35_OFFSET 
#define PCIE_ATTRIB_ATTR_35_OFFSET                                                 0XFD48008C
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
#undef GPIO_MASK_DATA_1_LSW_OFFSET 
#define GPIO_MASK_DATA_1_LSW_OFFSET                                                0XFF0A0008
#undef SATA_AHCI_VENDOR_PP2C_OFFSET 
#define SATA_AHCI_VENDOR_PP2C_OFFSET                                               0XFD0C00AC
#undef SATA_AHCI_VENDOR_PP3C_OFFSET 
#define SATA_AHCI_VENDOR_PP3C_OFFSET                                               0XFD0C00B0
#undef SATA_AHCI_VENDOR_PP4C_OFFSET 
#define SATA_AHCI_VENDOR_PP4C_OFFSET                                               0XFD0C00B4
#undef SATA_AHCI_VENDOR_PP5C_OFFSET 
#define SATA_AHCI_VENDOR_PP5C_OFFSET                                               0XFD0C00B8

/*
* USB 0 reset for control registers
*/
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL              0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT               10
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                0x00000400U

/*
* USB 0 sleep circuit reset
*/
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL             0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT              8
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK               0x00000100U

/*
* USB 0 reset
*/
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL              0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT               6
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                0x00000040U

/*
* GEM 3 reset
*/
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                 0x0000000F
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                  3
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                   0x00000008U

/*
* Sata PM clock control select
*/
#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL 
#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 
#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 
#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL             
#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT              0
#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK               0x00000003U

/*
* Sata block level reset
*/
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                  0x000F9FFE
#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                   1
#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                    0x00000002U

/*
* PCIE config reset
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL              0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT               19
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                0x00080000U

/*
* PCIE bridge block level reset (AXI interface)
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL           0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT            18
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK             0x00040000U

/*
* Display Port block level reset (includes DPDMA)
*/
#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                    0x000F9FFE
#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                     16
#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                      0x00010000U

/*
* Set to '1' to hold the GT in reset. Clear to release.
*/
#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 
#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 
#undef DP_DP_PHY_RESET_GT_RESET_MASK 
#define DP_DP_PHY_RESET_GT_RESET_DEFVAL                        0x00010003
#define DP_DP_PHY_RESET_GT_RESET_SHIFT                         1
#define DP_DP_PHY_RESET_GT_RESET_MASK                          0x00000002U

/*
* Two bits per lane. When set to 11, moves the GT to power down mode. When
    *  set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
    * lane 1
*/
#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 
#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 
#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 
#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL               0x00000000
#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                0
#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                 0x0000000FU

/*
* USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc
    * ks. Specifies the response time for a MAC request to the Packet FIFO Con
    * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th
    * e required values for the minimum SoC bus frequency of 60 MHz. USB turna
    * round time is a critical certification criteria when using long cables a
    * nd five hub levels. The required values for this field: - 4'h5: When the
    *  MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
    * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim
    * e is not critical, this field can be set to a larger value. Note: This f
    * ield is valid only in device mode.
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL               0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT                10
#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK                 0x00003C00U

/*
* Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP
    * I Transceiver Select signal (for HS) and the assertion of the TxValid si
    * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima
    * tely 2.5 us) is introduced from the time when the Transceiver Select is
    * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the
    *  chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you
    *  enable the hibernation feature when the device core comes out of power-
    * off, you must re-initialize this bit with the appropriate value because
    * the core does not save and restore this bit value during hibernation. -
    * This bit is valid only in device mode.
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL                 0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT                  9
#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK                   0x00000200U

/*
* Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use
    * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th
    * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert
    * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s
    * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t
    * he external PHY. Note: This bit must be set high for Port0 if PHY is use
    * d. Note: In Device mode - Before issuing any device endpoint command whe
    * n operating in 2.0 speeds, disable this bit and enable it after the comm
    * and completes. Without disabling this bit, if a command is issued when t
    * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of
    * f, the command will not get completed.
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL                0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT                 8
#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK                  0x00000100U

/*
* USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T
    * he application uses this bit to select a high-speed PHY or a full-speed
    * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a
    * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans
    * ceiver. This bit is always 1, with Write Only access. If both interface
    * types are selected in coreConsultant (that is, parameters' values are no
    * t zero), the application uses this bit to select the active interface is
    *  active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv
    * er is not supported. This bit always reads as 1'b0.
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL                  0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT                   7
#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK                    0x00000080U

/*
* Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend
    *  mode if Suspend conditions are valid. For DRD/OTG configurations, it is
    *  recommended that this bit is set to 0 during coreConsultant configurati
    * on. If it is set to 1, then the application must clear this bit after po
    * wer-on reset. Application needs to set it to 1 after the core initializa
    * tion completes. For all other configurations, this bit can be set to 1 d
    * uring core configuration. Note: - In host mode, on reset, this bit is se
    * t to 1. Software can override this bit after reset. - In device mode, be
    * fore issuing any device endpoint command when operating in 2.0 speeds, d
    * isable this bit and enable it after the command completes. If you issue
    * a command without disabling this bit when the device is in L2 state and
    * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c
    * ompleted.
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL            0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT             6
#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK              0x00000040U

/*
* Full-Speed Serial Interface Select (FSIntf) The application uses this bi
    * t to select a unidirectional or bidirectional USB 1.1 full-speed serial
    * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in
    * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir
    * ectional full-speed serial interface. This bit is set to 0 with Read Onl
    * y access. Note: USB 1.1 full-speed serial interface is not supported. Th
    * is bit always reads as 1'b0.
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL                  0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT                   5
#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK                    0x00000020U

/*
* ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se
    * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int
    * erface This bit is writable only if UTMI+ and ULPI is specified for High
    * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_
    * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o
    * n the interface selected through DWC_USB3_HSPHY_INTERFACE.
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL           0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT            4
#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK             0x00000010U

/*
* PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi
    * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte
    * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en
    * abled 2.0 ports must have the same clock frequency as Port0 clock freque
    * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge
    * ther for different ports at the same time (that is, all the ports must b
    * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If
    *  any of the USB 2.0 ports is selected as ULPI port for operation, then a
    * ll the USB 2.0 ports must be operating at 60 MHz.
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL                   0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT                    3
#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK                     0x00000008U

/*
* HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat
    * ed by the application in this field, is multiplied by a bit-time factor;
    *  this factor is added to the high-speed/full-speed interpacket timeout d
    * uration in the core to account for additional delays introduced by the P
    * HY. This may be required, since the delay introduced by the PHY in gener
    * ating the linestate condition may vary among PHYs. The USB standard time
    * out value for high-speed operation is 736 to 816 (inclusive) bit times.
    * The USB standard timeout value for full-speed operation is 16 to 18 (inc
    * lusive) bit times. The application must program this field based on the
    * speed of connection. The number of bit times added per PHY clock are: Hi
    * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P
    * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.
    * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc
    * k = 0.25 bit times
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL                 0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT                  0
#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK                   0x00000007U

/*
* ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive
    *  5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char
    * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl
    * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3)
*/
#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 
#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 
#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 
#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL          0x00000000
#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT           17
#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK            0x00020000U

/*
* This field indicates the frame length adjustment to be applied when SOF/
    * ITP counter is running on the ref_clk. This register value is used to ad
    * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i
    * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must
    * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t
    * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows:
    *  FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe
    * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege
    * r value of the ref_clk period got by truncating the decimal (fractional)
    *  value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c
    * lk_period is the ref_clk period including the fractional value. Examples
    * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA
    * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin
    * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE
    * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2
    * 0.8333 = 5208 (ignoring the fractional value)
*/
#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 
#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 
#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL          0x00000000
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT           8
#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK            0x003FFF00U

/*
* When this bit is set to '0', termsel, xcvrsel will become 0 during end o
    * f resume while the opmode will become 0 once controller completes end of
    *  resume and enters U0 state (2 separate commandswill be issued). When th
    * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during
    * end of resume itself (only 1 command will be issued)
*/
#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 
#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 
#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 
#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL  0x00000000
#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT  10
#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK   0x00000400U

/*
* Reserved
*/
#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 
#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 
#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 
#define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL                   0x00000000
#define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT                    9
#define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK                     0x00000200U

/*
* Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th
    * e Auto Retry feature. For IN transfers (non-isochronous) that encounter
    * data packets with CRC errors or internal overrun scenarios, the auto ret
    * ry feature causes the Host core to reply to the device with a non-termin
    * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N
    * umP != 0). If the Auto Retry feature is disabled (default), the core wil
    * l respond with a terminating retry ACK (that is, an ACK transaction pack
    * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut
    * o Retry Enabled Note: This bit is also applicable to the device mode.
*/
#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 
#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 
#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 
#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL           0x00000000
#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT            14
#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK             0x00004000U

/*
* If TRUE Completion Timeout Disable is supported. This is required to be
    * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi
    * ce Capability 2 [4]; EP=0x0001; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 
#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 
#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 
#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL  0x00000905
#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT  9
#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK  0x00000200U

/*
* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
    *  to be implemented, set to 32'h00000000. Bits are defined as follows: Me
    * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
    * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
    * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
    * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
    * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
    * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
    * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
    *  EP=0x0004; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL 
#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 
#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 
#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL                    
#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT                     0
#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK                      0x0000FFFFU

/*
* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not
    *  to be implemented, set to 32'h00000000. Bits are defined as follows: Me
    * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (
    * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask
    * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w
    * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:
    * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator (
    * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B
    * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.;
    *  EP=0xFFF0; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL 
#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 
#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 
#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL                    
#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT                     0
#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK                      0x0000FFFFU

/*
* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
    * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
    * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
    * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
    * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
    * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
    *  [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
    * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
    *  in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
    * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
    *  to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
    * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL 
#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 
#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 
#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL                    
#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT                     0
#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK                      0x0000FFFFU

/*
* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3
    * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA
    * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri
    * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi
    * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac
    * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit)
    *  [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
    * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size
    *  in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t
    * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set
    *  to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t
    * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL 
#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 
#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 
#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL                   
#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT                    0
#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK                     0x0000FFFFU

/*
* For an endpoint, specifies mask/settings for Base Address Register (BAR)
    *  2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
    * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
    * et to 32'h00000000. See BAR1 description if this functions as the upper
    * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
    * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
    * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
    * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
    * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
    * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
    *  63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
    * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
    * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
    * es.; EP=0x0004; RP=0xFFFF
*/
#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL 
#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 
#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 
#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL                   
#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT                    0
#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK                     0x0000FFFFU

/*
* For an endpoint, specifies mask/settings for Base Address Register (BAR)
    *  2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA
    * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
    * et to 32'h00000000. See BAR1 description if this functions as the upper
    * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF
    * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u
    * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
    * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
    * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
    * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
    *  63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat
    * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
    * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
    * es.; EP=0xFFF0; RP=0x00FF
*/
#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL 
#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 
#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 
#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL                   
#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT                    0
#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK                     0x0000FFFFU

/*
* For an endpoint, specifies mask/settings for Base Address Register (BAR)
    *  3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
    * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
    * et to 32'h00000000. See BAR2 description if this functions as the upper
    * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
    * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
    * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
    * t decode For an endpoint, bits are defined as follows: Memory Space BAR
    * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
    * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
    * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
    * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
    * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
    * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
    *  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
    * in bytes.; EP=0xFFFF; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL 
#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 
#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 
#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL                   
#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT                    0
#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK                     0x0000FFFFU

/*
* For an endpoint, specifies mask/settings for Base Address Register (BAR)
    *  3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA
    * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
    * et to 32'h00000000. See BAR2 description if this functions as the upper
    * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00
    * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R
    * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi
    * t decode For an endpoint, bits are defined as follows: Memory Space BAR
    * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty
    * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:
    * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi
    * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp
    * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I
    * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable
    *  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size
    * in bytes.; EP=0xFFFF; RP=0xFFFF
*/
#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL 
#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 
#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 
#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL                   
#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT                    0
#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK                     0x0000FFFFU

/*
* For an endpoint, specifies mask/settings for Base Address Register (BAR)
    *  4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
    * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
    * et to 32'h00000000. See BAR3 description if this functions as the upper
    * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
    * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
    * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
    * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
    * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
    * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
    *  63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
    * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
    * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
    * es.; EP=0x0004; RP=0xFFF0
*/
#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL 
#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 
#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 
#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL                   
#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT                    0
#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK                     0x0000FFFFU

/*
* For an endpoint, specifies mask/settings for Base Address Register (BAR)
    *  4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA
    * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
    * et to 32'h00000000. See BAR3 description if this functions as the upper
    * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF
    * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u
    * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie
    * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M
    * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to
    * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost
    *  63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat
    * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits
    * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt
    * es.; EP=0xFFF0; RP=0xFFF0
*/
#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL 
#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 
#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 
#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL                   
#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT                    0
#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK                     0x0000FFFFU

/*
* For an endpoint, specifies mask/settings for Base Address Register (BAR)
    *  5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
    * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
    * et to 32'h00000000. See BAR4 description if this functions as the upper
    * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
    * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
    * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
    * refetchable Memory Limit/Base implemented For an endpoint, bits are defi
    * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
    * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
    *  lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
    * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
    * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
    * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
    * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
    * ; RP=0xFFF1
*/
#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL 
#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 
#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 
#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL                   
#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT                    0
#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK                     0x0000FFFFU

/*
* For an endpoint, specifies mask/settings for Base Address Register (BAR)
    *  5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA
    * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s
    * et to 32'h00000000. See BAR4 description if this functions as the upper
    * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00
    * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0
    * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P
    * refetchable Memory Limit/Base implemented For an endpoint, bits are defi
    * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac
    * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be
    *  lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f
    * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory
    * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1)
    * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up
    * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF
    * ; RP=0xFFF1
*/
#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL 
#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 
#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 
#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL                   
#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT                    0
#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK                     0x0000FFFFU

/*
* Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1
    * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa
    * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo
    * rted; EP=0x0001; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 
#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 
#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 
#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL  0x00002138
#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT  8
#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK  0x00000700U

/*
* Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca
    * n withstand on transitions from L1 state to L0 (if L1 state supported).
    * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to
    * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For
    * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 
#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 
#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 
#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL  0x00002138
#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT  3
#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK  0x00000038U

/*
* Identifies the type of device/port as follows: 0000b PCI Express Endpoin
    * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P
    * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110
    * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X
    *  Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre
    * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM
    * _FACING settings.; EP=0x0000; RP=0x0004
*/
#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 
#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 
#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 
#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL  0x00009C02
#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT  4
#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK  0x000000F0U

/*
* PCIe Capability's Next Capability Offset pointer to the next item in the
    *  capabilities list, or 00h if this is the final capability.; EP=0x009C;
    * RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 
#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 
#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 
#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL       0x00009C02
#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT        8
#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK         0x0000FF00U

/*
* Number of credits that should be advertised for Completion data received
    *  on Virtual Channel 0. The bytes advertised must be less than or equal t
    * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
*/
#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL 
#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 
#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 
#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL  
#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT   0
#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK    0x000007FFU

/*
* Number of credits that should be advertised for Completion headers recei
    * ved on Virtual Channel 0. The sum of the posted, non posted, and complet
    * ion header credits must be <= 80; EP=0x0048; RP=0x0024
*/
#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 
#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 
#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 
#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL  0x00000248
#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT   0
#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK    0x0000007FU

/*
* Number of credits that should be advertised for Non-Posted headers recei
    * ved on Virtual Channel 0. The number of non posted data credits advertis
    * ed by the block is equal to the number of non posted header credits. The
    *  sum of the posted, non posted, and completion header credits must be <=
    *  80; EP=0x0004; RP=0x000C
*/
#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 
#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 
#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 
#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL  0x00000248
#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT  7
#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK   0x00003F80U

/*
* Number of credits that should be advertised for Non-Posted data received
    *  on Virtual Channel 0. The number of non posted data credits advertised
    * by the block is equal to two times the number of non posted header credi
    * ts if atomic operations are supported or is equal to the number of non p
    * osted header credits if atomic operations are not supported. The bytes a
    * dvertised must be less than or equal to the bram bytes available. See VC
    * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
*/
#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL 
#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 
#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 
#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL  
#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT  0
#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK   0x000007FFU

/*
* Number of credits that should be advertised for Posted data received on
    * Virtual Channel 0. The bytes advertised must be less than or equal to th
    * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
*/
#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL 
#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 
#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 
#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL  
#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT   0
#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK    0x000007FFU

/*
* Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_
    * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 
#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 
#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 
#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL          0x00007E04
#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT           15
#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK            0x00008000U

/*
* Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim
    *  TRUE == trim.; EP=0x0001; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 
#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 
#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 
#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL        0x00007E04
#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT         14
#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK          0x00004000U

/*
* Enables ECRC check on received TLP's 0 == don't check 1 == always check
    * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP=
    * 0x0003; RP=0x0003
*/
#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 
#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 
#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 
#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL             0x00007E04
#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT              12
#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK               0x00003000U

/*
* Index of last packet buffer used by TX TLM (i.e. number of buffers - 1).
    *  Calculated from max payload size supported and the number of brams conf
    * igured for transmit; EP=0x001C; RP=0x001C
*/
#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 
#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 
#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 
#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL     0x00007E04
#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT      7
#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK       0x00000F80U

/*
* Number of credits that should be advertised for Posted headers received
    * on Virtual Channel 0. The sum of the posted, non posted, and completion
    * header credits must be <= 80; EP=0x0004; RP=0x0020
*/
#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 
#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 
#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 
#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL  0x00007E04
#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT   0
#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK    0x0000007FU

/*
* Specifies values to be transferred to Header Type register. Bit 7 should
    *  be set to '0' indicating single-function device. Bit 0 identifies heade
    * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000;
    * RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 
#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 
#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 
#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL            0x00000100
#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT             0
#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK              0x000000FFU

/*
* PM Capability's Next Capability Offset pointer to the next item in the c
    * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP
    * =0x0060
*/
#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 
#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 
#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 
#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL         0x00003D48
#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT          0
#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK           0x000000FFU

/*
* MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont
    * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure;
    *  EP=0x0000; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL  0x00000160
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT  9
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK  0x00000200U

/*
* Indicates that the MSI structures exists. If this is FALSE, then the MSI
    *  structure cannot be accessed via either the link or the management port
    * .; EP=0x0001; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL             0x00000160
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT              8
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK               0x00000100U

/*
* MSI Capability's Next Capability Offset pointer to the next item in the
    * capabilities list, or 00h if this is the final capability.; EP=0x0060; R
    * P=0x0000
*/
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL        0x00000160
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT         0
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK          0x000000FFU

/*
* Indicates that the MSI structures exists. If this is FALSE, then the MSI
    *  structure cannot be accessed via either the link or the management port
    * .; EP=0x0001; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 
#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL             0x00000160
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT              8
#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK               0x00000100U

/*
* Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b
    * x4, 001000b x8.; EP=0x0004; RP=0x0004
*/
#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 
#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 
#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 
#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL  0x00000104
#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT  0
#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK  0x0000003FU

/*
* Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1
    * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004
*/
#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 
#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 
#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 
#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL   0x00000104
#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT    6
#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK     0x00000FC0U

/*
* TRUE specifies upstream-facing port. FALSE specifies downstream-facing p
    * ort.; EP=0x0001; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 
#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 
#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 
#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL       0x000000F0
#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT        6
#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK         0x00000040U

/*
* Enable the routing of message TLPs to the user through the TRN RX interf
    * ace. A bit value of 1 enables routing of the message TLP to the user. Me
    * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1
    *  - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I
    * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit
    *  10 PME_Turn_Off; EP=0x0000; RP=0x07FF
*/
#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 
#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 
#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 
#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL      0x00000000
#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT       5
#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK        0x0000FFE0U

/*
* Disable BAR filtering. Does not change the behavior of the bar hit outpu
    * ts; EP=0x0000; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 
#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 
#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 
#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL  0x00000000
#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT  1
#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK   0x00000002U

/*
* Link Bandwidth notification capability. Indicates support for the link b
    * andwidth notification status and interrupt mechanism. Required for Root.
    * ; EP=0x0000; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 
#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 
#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL  0x000009FF
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT  9
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK  0x00000200U

/*
* Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op
    * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001
    * ; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 
#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 
#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL  0x000009FF
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT  14
#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK  0x00004000U

/*
* Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value
    *  (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU
    * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 
#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 
#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 
#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL   0x00000000
#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT    15
#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK     0x00008000U

/*
* Sets a user-defined timeout for the Replay Timer to force cause the retr
    * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_
    * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att
    * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.;
    *  EP=0x0000; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 
#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 
#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 
#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL      0x00000000
#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT       0
#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK        0x00007FFFU

/*
* Device ID for the the PCIe Cap Structure Device ID field
*/
#undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 
#undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 
#undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 
#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL                       0x10EE7024
#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT                        0
#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK                         0x0000FFFFU

/*
* Vendor ID for the PCIe Cap Structure Vendor ID field
*/
#undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 
#undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 
#undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 
#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL                      0x10EE7024
#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT                       16
#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK                        0xFFFF0000U

/*
* Subsystem ID for the the PCIe Cap Structure Subsystem ID field
*/
#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 
#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 
#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 
#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL             0x10EE0007
#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT              0
#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK               0x0000FFFFU

/*
* Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
*/
#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 
#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 
#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 
#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL        0x10EE0007
#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT         16
#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK          0xFFFF0000U

/*
* Revision ID for the the PCIe Cap Structure
*/
#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL 
#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 
#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 
#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL                   
#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT                    0
#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK                     0x000000FFU

/*
* Code identifying basic function, subclass and applicable programming int
    * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000
*/
#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL 
#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 
#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 
#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL             
#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT              0
#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK               0x0000FFFFU

/*
* Code identifying basic function, subclass and applicable programming int
    * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006
*/
#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 
#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 
#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 
#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL             0x00000905
#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT              0
#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK               0x000000FFU

/*
* INTX Interrupt Generation Capable. If FALSE, this will cause Command[10]
    *  to be hardwired to 0.; EP=0x0001; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 
#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 
#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 
#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL   0x00000905
#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT    8
#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK     0x00000100U

/*
* Indicates that the AER structures exists. If this is FALSE, then the AER
    *  structure cannot be accessed via either the link or the management port
    * , and AER will be considered to not be present for error management task
    * s (such as what types of error messages are sent if an error is detected
    * ).; EP=0x0001; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 
#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 
#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 
#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL              0x00001000
#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT               12
#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK                0x00001000U

/*
* Indicates that the AER structures exists. If this is FALSE, then the AER
    *  structure cannot be accessed via either the link or the management port
    * , and AER will be considered to not be present for error management task
    * s (such as what types of error messages are sent if an error is detected
    * ).; EP=0x0001; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 
#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 
#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 
#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL              0x00001000
#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT               12
#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK                0x00001000U

/*
* VSEC's Next Capability Offset pointer to the next item in the capabiliti
    * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140
*/
#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 
#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 
#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 
#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL       0x00002281
#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT        1
#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK         0x00001FFEU

/*
* CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the
    *  Root Capabilities register.; EP=0x0000; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 
#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 
#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 
#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL  0x00000000
#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT  5
#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK  0x00000020U

/*
* Indicates that the MSIX structures exists. If this is FALSE, then the MS
    * IX structure cannot be accessed via either the link or the management po
    * rt.; EP=0x0001; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 
#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 
#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL            0x00000100
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT             8
#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK              0x00000100U

/*
* MSI-X Table Size. This value is transferred to the MSI-X Message Control
    * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does
    * not implement the table; that must be implemented in user logic.; EP=0x0
    * 003; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL 
#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 
#undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 
#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL    
#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT     0
#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK      0x000007FFU

/*
* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
    * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL 
#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 
#undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 
#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL  
#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT   0
#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK    0x0000FFFFU

/*
* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset
    * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL 
#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 
#undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 
#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL  
#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT   0
#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK    0x00001FFFU

/*
* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
    * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 
#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 
#undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 
#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL    
#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT     0
#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK      0x0000FFFFU

/*
* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB
    * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000
*/
#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 
#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 
#undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 
#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL    0x00008000
#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT     3
#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK      0x0000FFF8U

/*
* DT837748 Enable
*/
#undef PCIE_ATTRIB_CB_CB1_DEFVAL 
#undef PCIE_ATTRIB_CB_CB1_SHIFT 
#undef PCIE_ATTRIB_CB_CB1_MASK 
#define PCIE_ATTRIB_CB_CB1_DEFVAL                              0x00000001
#define PCIE_ATTRIB_CB_CB1_SHIFT                               1
#define PCIE_ATTRIB_CB_CB1_MASK                                0x00000002U

/*
* Active State PM Support. Indicates the level of active state power manag
    * ement supported by the selected PCI Express Link, encoded as follows: 0
    * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte
    * d.; EP=0x0001; RP=0x0001
*/
#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 
#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 
#undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 
#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL  0x00001FFD
#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT   12
#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK    0x00003000U

/*
* PCIE control block level reset
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL             0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT              17
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK               0x00020000U

/*
* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
*/
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 
#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL                 0x00000000
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT                  16
#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK                   0xFFFF0000U

/*
* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW]
*/
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 
#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL                 0x00000000
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT                  0
#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK                   0x0000FFFFU

/*
* Status Read value of PLL Lock
*/
#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL  0x00000001
#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT  4
#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK  0x00000010U
#define SERDES_L0_PLL_STATUS_READ_1_OFFSET                                         0XFD4023E4

/*
* Status Read value of PLL Lock
*/
#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL  0x00000001
#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT  4
#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK  0x00000010U
#define SERDES_L1_PLL_STATUS_READ_1_OFFSET                                         0XFD4063E4

/*
* Status Read value of PLL Lock
*/
#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL  0x00000001
#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT  4
#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK  0x00000010U
#define SERDES_L2_PLL_STATUS_READ_1_OFFSET                                         0XFD40A3E4

/*
* Status Read value of PLL Lock
*/
#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL  0x00000001
#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT  4
#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK  0x00000010U
#define SERDES_L3_PLL_STATUS_READ_1_OFFSET                                         0XFD40E3E4

/*
* CIBGMN: COMINIT Burst Gap Minimum.
*/
#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 
#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 
#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 
#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL                    0x28184D1B
#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT                     0
#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK                      0x000000FFU

/*
* CIBGMX: COMINIT Burst Gap Maximum.
*/
#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 
#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 
#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 
#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL                    0x28184D1B
#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT                     8
#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK                      0x0000FF00U

/*
* CIBGN: COMINIT Burst Gap Nominal.
*/
#undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 
#undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 
#undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 
#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL                     0x28184D1B
#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT                      16
#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK                       0x00FF0000U

/*
* CINMP: COMINIT Negate Minimum Period.
*/
#undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 
#undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 
#undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK 
#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL                     0x28184D1B
#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT                      24
#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK                       0xFF000000U

/*
* CWBGMN: COMWAKE Burst Gap Minimum.
*/
#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 
#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 
#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 
#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL                    0x0E081906
#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT                     0
#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK                      0x000000FFU

/*
* CWBGMX: COMWAKE Burst Gap Maximum.
*/
#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 
#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 
#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 
#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL                    0x0E081906
#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT                     8
#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK                      0x0000FF00U

/*
* CWBGN: COMWAKE Burst Gap Nominal.
*/
#undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 
#undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 
#undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 
#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL                     0x0E081906
#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT                      16
#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK                       0x00FF0000U

/*
* CWNMP: COMWAKE Negate Minimum Period.
*/
#undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 
#undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 
#undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 
#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL                     0x0E081906
#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT                      24
#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK                       0xFF000000U

/*
* BMX: COM Burst Maximum.
*/
#undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 
#undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 
#undef SATA_AHCI_VENDOR_PP4C_BMX_MASK 
#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL                       0x064A0813
#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT                        0
#define SATA_AHCI_VENDOR_PP4C_BMX_MASK                         0x000000FFU

/*
* BNM: COM Burst Nominal.
*/
#undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 
#undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 
#undef SATA_AHCI_VENDOR_PP4C_BNM_MASK 
#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL                       0x064A0813
#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT                        8
#define SATA_AHCI_VENDOR_PP4C_BNM_MASK                         0x0000FF00U

/*
* SFD: Signal Failure Detection, if the signal detection de-asserts for a
    * time greater than this then the OOB detector will determine this is a li
    * ne idle and cause the PhyInit state machine to exit the Phy Ready State.
    *  A value of zero disables the Signal Failure Detector. The value is base
    * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving
    * a nominal time of 500ns based on a 150MHz PMCLK.
*/
#undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 
#undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 
#undef SATA_AHCI_VENDOR_PP4C_SFD_MASK 
#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL                       0x064A0813
#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT                        16
#define SATA_AHCI_VENDOR_PP4C_SFD_MASK                         0x00FF0000U

/*
* PTST: Partial to Slumber timer value, specific delay the controller shou
    * ld apply while in partial before entering slumber. The value is bases on
    *  the system clock divided by 128, total delay = (Sys Clock Period) * PTS
    * T * 128
*/
#undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 
#undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 
#undef SATA_AHCI_VENDOR_PP4C_PTST_MASK 
#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL                      0x064A0813
#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT                       24
#define SATA_AHCI_VENDOR_PP4C_PTST_MASK                        0xFF000000U

/*
* RIT: Retry Interval Timer. The calculated value divided by two, the lowe
    * r digit of precision is not needed.
*/
#undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 
#undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 
#undef SATA_AHCI_VENDOR_PP5C_RIT_MASK 
#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL                       0x3FFC96A4
#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT                        0
#define SATA_AHCI_VENDOR_PP5C_RIT_MASK                         0x000FFFFFU

/*
* RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev
    * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a
    * fast SERDES it is suggested that this value be 54.2us / 4
*/
#undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 
#undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 
#undef SATA_AHCI_VENDOR_PP5C_RCT_MASK 
#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL                       0x3FFC96A4
#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT                        20
#define SATA_AHCI_VENDOR_PP5C_RCT_MASK                         0xFFF00000U
#undef CRL_APB_RST_LPD_TOP_OFFSET 
#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
#undef CRL_APB_RST_LPD_IOU0_OFFSET 
#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 
#define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
#undef DP_DP_PHY_RESET_OFFSET 
#define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100

/*
* USB 0 reset for control registers
*/
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL              0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT               10
#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                0x00000400U

/*
* USB 0 sleep circuit reset
*/
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL             0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT              8
#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK               0x00000100U

/*
* USB 0 reset
*/
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL              0x00188FDF
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT               6
#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                0x00000040U

/*
* GEM 3 reset
*/
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                 0x0000000F
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                  3
#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                   0x00000008U

/*
* Sata block level reset
*/
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                  0x000F9FFE
#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                   1
#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                    0x00000002U

/*
* PCIE config reset
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL              0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT               19
#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                0x00080000U

/*
* PCIE control block level reset
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL             0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT              17
#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK               0x00020000U

/*
* PCIE bridge block level reset (AXI interface)
*/
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL           0x000F9FFE
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT            18
#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK             0x00040000U

/*
* Two bits per lane. When set to 11, moves the GT to power down mode. When
    *  set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
    * lane 1
*/
#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 
#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 
#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 
#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL               0x00000000
#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                0
#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                 0x0000000FU

/*
* Set to '1' to hold the GT in reset. Clear to release.
*/
#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 
#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 
#undef DP_DP_PHY_RESET_GT_RESET_MASK 
#define DP_DP_PHY_RESET_GT_RESET_DEFVAL                        0x00010003
#define DP_DP_PHY_RESET_GT_RESET_SHIFT                         1
#define DP_DP_PHY_RESET_GT_RESET_MASK                          0x00000002U

/*
* Display Port block level reset (includes DPDMA)
*/
#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                    0x000F9FFE
#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                     16
#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                      0x00010000U
#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET                                         0XFFD80118
#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 
#define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET                                           0XFFD80120

/*
* Power-up Request Interrupt Enable for PL
*/
#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 
#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 
#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL                  0x00000000
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT                   23
#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK                    0x00800000U

/*
* Power-up Request Trigger for PL
*/
#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 
#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 
#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL                    0x00000000
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT                     23
#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK                      0x00800000U

/*
* Power-up Request Status for PL
*/
#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 
#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 
#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL                  0x00000000
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT                   23
#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK                    0x00800000U
#define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET                                         0XFFD80110
#undef CRF_APB_RST_FPD_TOP_OFFSET 
#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
#undef CRL_APB_RST_LPD_TOP_OFFSET 
#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
#undef FPD_SLCR_AFI_FS_OFFSET 
#define FPD_SLCR_AFI_FS_OFFSET                                                     0XFD615000

/*
* AF_FM0 block level reset
*/
#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL               0x000F9FFE
#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT                7
#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK                 0x00000080U

/*
* AF_FM1 block level reset
*/
#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL               0x000F9FFE
#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT                8
#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK                 0x00000100U

/*
* AF_FM2 block level reset
*/
#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL               0x000F9FFE
#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT                9
#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK                 0x00000200U

/*
* AF_FM3 block level reset
*/
#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL               0x000F9FFE
#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT                10
#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK                 0x00000400U

/*
* AF_FM4 block level reset
*/
#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL               0x000F9FFE
#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT                11
#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK                 0x00000800U

/*
* AF_FM5 block level reset
*/
#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 
#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 
#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 
#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL               0x000F9FFE
#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT                12
#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK                 0x00001000U

/*
* AFI FM 6
*/
#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 
#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 
#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 
#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL               0x00188FDF
#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT                19
#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK                 0x00080000U

/*
* Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit
    *  AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
    *  width 11: reserved
*/
#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 
#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 
#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 
#define FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL                      0x00000A00
#define FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT                       8
#define FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK                        0x00000300U

/*
* Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit
    *  AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data
    *  width 11: reserved
*/
#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 
#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 
#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 
#define FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL                      0x00000A00
#define FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT                       10
#define FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK                        0x00000C00U
#undef GPIO_MASK_DATA_5_MSW_OFFSET 
#define GPIO_MASK_DATA_5_MSW_OFFSET                                                0XFF0A002C
#undef GPIO_DIRM_5_OFFSET 
#define GPIO_DIRM_5_OFFSET                                                         0XFF0A0344
#undef GPIO_OEN_5_OFFSET 
#define GPIO_OEN_5_OFFSET                                                          0XFF0A0348
#undef GPIO_DATA_5_OFFSET 
#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
#undef GPIO_DATA_5_OFFSET 
#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
#undef GPIO_DATA_5_OFFSET 
#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054

/*
* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
*/
#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 
#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 
#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 
#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL                 0x00000000
#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT                  16
#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK                   0xFFFF0000U

/*
* Operation is the same as DIRM_0[DIRECTION_0]
*/
#undef GPIO_DIRM_5_DIRECTION_5_DEFVAL 
#undef GPIO_DIRM_5_DIRECTION_5_SHIFT 
#undef GPIO_DIRM_5_DIRECTION_5_MASK 
#define GPIO_DIRM_5_DIRECTION_5_DEFVAL                         
#define GPIO_DIRM_5_DIRECTION_5_SHIFT                          0
#define GPIO_DIRM_5_DIRECTION_5_MASK                           0xFFFFFFFFU

/*
* Operation is the same as OEN_0[OP_ENABLE_0]
*/
#undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL 
#undef GPIO_OEN_5_OP_ENABLE_5_SHIFT 
#undef GPIO_OEN_5_OP_ENABLE_5_MASK 
#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL                          
#define GPIO_OEN_5_OP_ENABLE_5_SHIFT                           0
#define GPIO_OEN_5_OP_ENABLE_5_MASK                            0xFFFFFFFFU

/*
* Output Data
*/
#undef GPIO_DATA_5_DATA_5_DEFVAL 
#undef GPIO_DATA_5_DATA_5_SHIFT 
#undef GPIO_DATA_5_DATA_5_MASK 
#define GPIO_DATA_5_DATA_5_DEFVAL                              
#define GPIO_DATA_5_DATA_5_SHIFT                               0
#define GPIO_DATA_5_DATA_5_MASK                                0xFFFFFFFFU

/*
* Output Data
*/
#undef GPIO_DATA_5_DATA_5_DEFVAL 
#undef GPIO_DATA_5_DATA_5_SHIFT 
#undef GPIO_DATA_5_DATA_5_MASK 
#define GPIO_DATA_5_DATA_5_DEFVAL                              
#define GPIO_DATA_5_DATA_5_SHIFT                               0
#define GPIO_DATA_5_DATA_5_MASK                                0xFFFFFFFFU

/*
* Output Data
*/
#undef GPIO_DATA_5_DATA_5_DEFVAL 
#undef GPIO_DATA_5_DATA_5_SHIFT 
#undef GPIO_DATA_5_DATA_5_MASK 
#define GPIO_DATA_5_DATA_5_DEFVAL                              
#define GPIO_DATA_5_DATA_5_SHIFT                               0
#define GPIO_DATA_5_DATA_5_MASK                                0xFFFFFFFFU
#ifdef __cplusplus
extern "C" {
#endif
 int psu_init (); 
 unsigned long psu_ps_pl_isolation_removal_data(); 
 unsigned long psu_ps_pl_reset_config_data(); 
 int psu_protection(); 
 int psu_fpd_protection(); 
 int psu_ocm_protection(); 
 int psu_ddr_protection(); 
 int psu_lpd_protection(); 
 int psu_protection_lock(); 
 unsigned long psu_ddr_qos_init_data(void); 
 unsigned long psu_apply_master_tz(); 
#ifdef __cplusplus
}
#endif