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pigweed / third_party / github / FreeRTOS / FreeRTOS-Kernel / 9c0c37ab9b56f2c90085b78df2f58b5833e473db / . / FreeRTOS / Demo / CORTEX_MB9B500_IAR_Keil / Fujitu_source / mb9bf506n.h
blob: fa2a724f1bee39eae6a70c1f893d3028cf960208 [file] [log] [blame]
/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
/* */
/* Header File for Device MB9BF506N */
/* Version V1.00 */
/* Date 2011-01-21 */
/* */
/************************************************************************/
#ifndef _MB9BF506N_H_
#define _MB9BF506N_H_
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
* Configuration of the Cortex-M3 Processor and Core Peripherals
******************************************************************************/
#define __MPU_PRESENT 1 /* FM3 provide an MPU */
#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
/******************************************************************************
* Interrupt Number Definition
******************************************************************************/
typedef enum IRQn
{
NMI_IRQn = -14, /* 2 Non Maskable */
HardFault_IRQn = -13, /* 3 Hard Fault */
MemManage_IRQn = -12, /* 4 Memory Management */
BusFault_IRQn = -11, /* 5 Bus Fault */
UsageFault_IRQn = -10, /* 6 Usage Fault */
SVC_IRQn = -5, /* 11 SV Call */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor */
PendSVC_IRQn = -2, /* 14 Pend SV */
SysTick_IRQn = -1, /* 15 System Tick */
CSV_IRQn = 0, /* Clock Super Visor */
SWDT_IRQn = 1, /* Software Watchdog Timer */
LVD_IRQn = 2, /* Low Voltage Detector */
WFG_IRQn = 3, /* Wave Form Generator */
EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */
EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */
DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */
MFS0RX_IRQn = 7, /* MultiFunction Serial ch.0 */
MFS0TX_IRQn = 8, /* MultiFunction Serial ch.0 */
MFS1RX_IRQn = 9, /* MultiFunction Serial ch.1 */
MFS1TX_IRQn = 10, /* MultiFunction Serial ch.1 */
MFS2RX_IRQn = 11, /* MultiFunction Serial ch.2 */
MFS2TX_IRQn = 12, /* MultiFunction Serial ch.2 */
MFS3RX_IRQn = 13, /* MultiFunction Serial ch.3 */
MFS3TX_IRQn = 14, /* MultiFunction Serial ch.3 */
MFS4RX_IRQn = 15, /* MultiFunction Serial ch.4 */
MFS4TX_IRQn = 16, /* MultiFunction Serial ch.4 */
MFS5RX_IRQn = 17, /* MultiFunction Serial ch.5 */
MFS5TX_IRQn = 18, /* MultiFunction Serial ch.5 */
MFS6RX_IRQn = 19, /* MultiFunction Serial ch.6 */
MFS6TX_IRQn = 20, /* MultiFunction Serial ch.6 */
MFS7RX_IRQn = 21, /* MultiFunction Serial ch.7 */
MFS7TX_IRQn = 22, /* MultiFunction Serial ch.7 */
PPG_IRQn = 23, /* PPG */
OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */
ADC0_IRQn = 25, /* ADC0 */
ADC1_IRQn = 26, /* ADC1 */
ADC2_IRQn = 27, /* ADC2 */
FRTIM_IRQn = 28, /* Free-run Timer */
INCAP_IRQn = 29, /* Input Capture */
OUTCOMP_IRQn = 30, /* Output Compare */
BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */
CAN0_IRQn = 32, /* CAN ch.0 */
CAN1_IRQn = 33, /* CAN ch.1 */
USBF_IRQn = 34, /* USB Function */
USBF_USBH_IRQn = 35, /* USB Function / USB HOST */
/* Reserved = 36, */
/* Reserved = 37, */
DMAC0_IRQn = 38, /* DMAC ch.0 */
DMAC1_IRQn = 39, /* DMAC ch.1 */
DMAC2_IRQn = 40, /* DMAC ch.2 */
DMAC3_IRQn = 41, /* DMAC ch.3 */
DMAC4_IRQn = 42, /* DMAC ch.4 */
DMAC5_IRQn = 43, /* DMAC ch.5 */
DMAC6_IRQn = 44, /* DMAC ch.6 */
DMAC7_IRQn = 45, /* DMAC ch.7 */
/* Reserved = 46, */
/* Reserved = 47, */
} IRQn_Type;
#include "core_cm3.h"
#include "system_mb9bf50x.h"
#include <stdint.h>
#define SUCCESS 0
#define ERROR -1
#ifndef NULL
#define NULL 0
#endif
/******************************************************************************/
/* Device Specific Peripheral Registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* Flash_IF_MODULE
******************************************************************************/
/* Flash interface registers */
typedef struct
{
__IO uint32_t FASZR;
__IO uint32_t FRWTR;
__IO uint32_t FSTR;
uint8_t RESERVED0[4];
__IO uint32_t FSYNDN;
uint8_t RESERVED1[236];
__IO uint32_t CRTRMM;
}FM3_FIF_TypeDef;
/******************************************************************************
* Clock_Reset_MODULE
******************************************************************************/
/* Clock and reset registers */
typedef struct
{
__IO uint8_t SCM_CTL;
uint8_t RESERVED0[3];
__IO uint8_t SCM_STR;
uint8_t RESERVED1[3];
__IO uint32_t STB_CTL;
__IO uint16_t RST_STR;
uint8_t RESERVED2[2];
__IO uint8_t BSC_PSR;
uint8_t RESERVED3[3];
__IO uint8_t APBC0_PSR;
uint8_t RESERVED4[3];
__IO uint8_t APBC1_PSR;
uint8_t RESERVED5[3];
__IO uint8_t APBC2_PSR;
uint8_t RESERVED6[3];
__IO uint8_t SWC_PSR;
uint8_t RESERVED7[7];
__IO uint8_t TTC_PSR;
uint8_t RESERVED8[7];
__IO uint8_t CSW_TMR;
uint8_t RESERVED9[3];
__IO uint8_t PSW_TMR;
uint8_t RESERVED10[3];
__IO uint8_t PLL_CTL1;
uint8_t RESERVED11[3];
__IO uint8_t PLL_CTL2;
uint8_t RESERVED12[3];
__IO uint16_t CSV_CTL;
uint8_t RESERVED13[2];
__IO uint8_t CSV_STR;
uint8_t RESERVED14[3];
__IO uint16_t FCSWH_CTL;
uint8_t RESERVED15[2];
__IO uint16_t FCSWL_CTL;
uint8_t RESERVED16[2];
__IO uint16_t FCSWD_CTL;
uint8_t RESERVED17[2];
__IO uint8_t DBWDT_CTL;
uint8_t RESERVED18[11];
__IO uint8_t INT_ENR;
uint8_t RESERVED19[3];
__IO uint8_t INT_STR;
uint8_t RESERVED20[3];
__IO uint8_t INT_CLR;
}FM3_CRG_TypeDef;
/******************************************************************************
* HWWDT_MODULE
******************************************************************************/
/* Hardware watchdog registers */
typedef struct
{
__IO uint32_t WDG_LDR;
__IO uint32_t WDG_VLR;
__IO uint8_t WDG_CTL;
uint8_t RESERVED0[3];
__IO uint8_t WDG_ICL;
uint8_t RESERVED1[3];
__IO uint8_t WDG_RIS;
uint8_t RESERVED2[3055];
__IO uint32_t WDG_LCK;
}FM3_HWWDT_TypeDef;
/******************************************************************************
* SWWDT_MODULE
******************************************************************************/
/* Software watchdog registers */
typedef struct
{
__IO uint32_t WDOGLOAD;
__IO uint32_t WDOGVALUE;
__IO uint8_t WDOGCONTROL;
uint8_t RESERVED0[3];
__IO uint32_t WDOGINTCLR;
__IO uint8_t WDOGRIS;
uint8_t RESERVED1[3055];
__IO uint32_t WDOGLOCK;
}FM3_SWWDT_TypeDef;
/******************************************************************************
* DTIM_MODULE
******************************************************************************/
/* Dual timer 1/2 registers */
typedef struct
{
__IO uint32_t TIMER1LOAD;
__IO uint32_t TIMER1VALUE;
__IO uint32_t TIMER1CONTROL;
__IO uint32_t TIMER1INTCLR;
__IO uint32_t TIMER1RIS;
__IO uint32_t TIMER1MIS;
__IO uint32_t TIMER1BGLOAD;
uint8_t RESERVED0[4];
__IO uint32_t TIMER2LOAD;
__IO uint32_t TIMER2VALUE;
__IO uint32_t TIMER2CONTROL;
__IO uint32_t TIMER2INTCLR;
__IO uint32_t TIMER2RIS;
__IO uint32_t TIMER2MIS;
__IO uint32_t TIMER2BGLOAD;
}FM3_DTIM_TypeDef;
/******************************************************************************
* MFT_FRT_MODULE
******************************************************************************/
/* Multifunction Timer unit 0 Free Running Timer registers */
typedef struct
{
uint8_t RESERVED0[40];
__IO uint16_t TCCP0;
uint8_t RESERVED1[2];
__IO uint16_t TCDT0;
uint8_t RESERVED2[2];
__IO uint16_t TCSA0;
uint8_t RESERVED3[2];
__IO uint16_t TCSB0;
uint8_t RESERVED4[2];
__IO uint16_t TCCP1;
uint8_t RESERVED5[2];
__IO uint16_t TCDT1;
uint8_t RESERVED6[2];
__IO uint16_t TCSA1;
uint8_t RESERVED7[2];
__IO uint16_t TCSB1;
uint8_t RESERVED8[2];
__IO uint16_t TCCP2;
uint8_t RESERVED9[2];
__IO uint16_t TCDT2;
uint8_t RESERVED10[2];
__IO uint16_t TCSA2;
uint8_t RESERVED11[2];
__IO uint16_t TCSB2;
}FM3_MFT_FRT_TypeDef;
/******************************************************************************
* MFT_OCU_MODULE
******************************************************************************/
/* Multifunction Timer unit 0 Output Compare Unit registers */
typedef struct
{
__IO uint16_t OCCP0;
uint8_t RESERVED0[2];
__IO uint16_t OCCP1;
uint8_t RESERVED1[2];
__IO uint16_t OCCP2;
uint8_t RESERVED2[2];
__IO uint16_t OCCP3;
uint8_t RESERVED3[2];
__IO uint16_t OCCP4;
uint8_t RESERVED4[2];
__IO uint16_t OCCP5;
uint8_t RESERVED5[2];
__IO uint8_t OCSA10;
__IO uint8_t OCSB10;
uint8_t RESERVED6[2];
__IO uint8_t OCSA32;
__IO uint8_t OCSB32;
uint8_t RESERVED7[2];
__IO uint8_t OCSA54;
__IO uint8_t OCSB54;
uint8_t RESERVED8[3];
__IO uint8_t OCSC;
uint8_t RESERVED9[50];
__IO uint8_t OCFS10;
__IO uint8_t OCFS32;
uint8_t RESERVED10[2];
__IO uint8_t OCFS54;
}FM3_MFT_OCU_TypeDef;
/******************************************************************************
* MFT_WFG_MODULE
******************************************************************************/
/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
typedef struct
{
uint8_t RESERVED0[128];
__IO uint16_t WFTM10;
uint8_t RESERVED1[2];
__IO uint16_t WFTM32;
uint8_t RESERVED2[2];
__IO uint16_t WFTM54;
uint8_t RESERVED3[2];
__IO uint16_t WFSA10;
uint8_t RESERVED4[2];
__IO uint16_t WFSA32;
uint8_t RESERVED5[2];
__IO uint16_t WFSA54;
uint8_t RESERVED6[2];
__IO uint16_t WFIR;
uint8_t RESERVED7[2];
__IO uint16_t NZCL;
}FM3_MFT_WFG_TypeDef;
/******************************************************************************
* MFT_ICU_MODULE
******************************************************************************/
/* Multifunction Timer unit 0 Input Capture Unit registers */
typedef struct
{
uint8_t RESERVED0[96];
__IO uint8_t ICFS10;
__IO uint8_t ICFS32;
uint8_t RESERVED1[6];
__IO uint16_t ICCP0;
uint8_t RESERVED2[2];
__IO uint16_t ICCP1;
uint8_t RESERVED3[2];
__IO uint16_t ICCP2;
uint8_t RESERVED4[2];
__IO uint16_t ICCP3;
uint8_t RESERVED5[2];
__IO uint8_t ICSA10;
__IO uint8_t ICSB10;
uint8_t RESERVED6[2];
__IO uint8_t ICSA32;
__IO uint8_t ICSB32;
}FM3_MFT_ICU_TypeDef;
/******************************************************************************
* MFT_ADCMP_MODULE
******************************************************************************/
/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
typedef struct
{
uint8_t RESERVED0[160];
__IO uint16_t ACCP0;
uint8_t RESERVED1[2];
__IO uint16_t ACCPDN0;
uint8_t RESERVED2[2];
__IO uint16_t ACCP1;
uint8_t RESERVED3[2];
__IO uint16_t ACCPDN1;
uint8_t RESERVED4[2];
__IO uint16_t ACCP2;
uint8_t RESERVED5[2];
__IO uint16_t ACCPDN2;
uint8_t RESERVED6[2];
__IO uint8_t ACSB;
uint8_t RESERVED7[3];
__IO uint16_t ACSA;
uint8_t RESERVED8[2];
__IO uint16_t ATSA;
}FM3_MFT_ADCMP_TypeDef;
/******************************************************************************
* MFT_PPG_MODULE
******************************************************************************/
/* Multifunction Timer PPG registers */
typedef struct
{
uint8_t RESERVED0;
__IO uint8_t TTCR0;
uint8_t RESERVED1[7];
__IO uint8_t COMP0;
uint8_t RESERVED2[2];
__IO uint8_t COMP2;
uint8_t RESERVED3[4];
__IO uint8_t COMP4;
uint8_t RESERVED4[2];
__IO uint8_t COMP6;
uint8_t RESERVED5[12];
__IO uint8_t TTCR1;
uint8_t RESERVED6[7];
__IO uint8_t COMP1;
uint8_t RESERVED7[2];
__IO uint8_t COMP3;
uint8_t RESERVED8[4];
__IO uint8_t COMP5;
uint8_t RESERVED9[2];
__IO uint8_t COMP7;
uint8_t RESERVED10[203];
__IO uint16_t TRG;
uint8_t RESERVED11[2];
__IO uint16_t REVC;
uint8_t RESERVED12[250];
__IO uint8_t PPGC1;
__IO uint8_t PPGC0;
uint8_t RESERVED13[2];
__IO uint8_t PPGC3;
__IO uint8_t PPGC2;
uint8_t RESERVED14[2];
union {
__IO uint16_t PRL0;
struct {
__IO uint8_t PRLL0;
__IO uint8_t PRLH0;
};
};
uint8_t RESERVED15[2];
union {
__IO uint16_t PRL1;
struct {
__IO uint8_t PRLL1;
__IO uint8_t PRLH1;
};
};
uint8_t RESERVED16[2];
union {
__IO uint16_t PRL2;
struct {
__IO uint8_t PRLL2;
__IO uint8_t PRLH2;
};
};
uint8_t RESERVED17[2];
union {
__IO uint16_t PRL3;
struct {
__IO uint8_t PRLL3;
__IO uint8_t PRLH3;
};
};
uint8_t RESERVED18[2];
__IO uint8_t GATEC0;
uint8_t RESERVED19[39];
__IO uint8_t PPGC5;
__IO uint8_t PPGC4;
uint8_t RESERVED20[2];
__IO uint8_t PPGC7;
__IO uint8_t PPGC6;
uint8_t RESERVED21[2];
union {
__IO uint16_t PRL4;
struct {
__IO uint8_t PRLL4;
__IO uint8_t PRLH4;
};
};
uint8_t RESERVED22[2];
union {
__IO uint16_t PRL5;
struct {
__IO uint8_t PRLL5;
__IO uint8_t PRLH5;
};
};
uint8_t RESERVED23[2];
union {
__IO uint16_t PRL6;
struct {
__IO uint8_t PRLL6;
__IO uint8_t PRLH6;
};
};
uint8_t RESERVED24[2];
union {
__IO uint16_t PRL7;
struct {
__IO uint8_t PRLL7;
__IO uint8_t PRLH7;
};
};
uint8_t RESERVED25[2];
__IO uint8_t GATEC4;
uint8_t RESERVED26[39];
__IO uint8_t PPGC9;
__IO uint8_t PPGC8;
uint8_t RESERVED27[2];
__IO uint8_t PPGC11;
__IO uint8_t PPGC10;
uint8_t RESERVED28[2];
union {
__IO uint16_t PRL8;
struct {
__IO uint8_t PRLL8;
__IO uint8_t PRLH8;
};
};
uint8_t RESERVED29[2];
union {
__IO uint16_t PRL9;
struct {
__IO uint8_t PRLL9;
__IO uint8_t PRLH9;
};
};
uint8_t RESERVED30[2];
union {
__IO uint16_t PRL10;
struct {
__IO uint8_t PRLL10;
__IO uint8_t PRLH10;
};
};
uint8_t RESERVED31[2];
union {
__IO uint16_t PRL11;
struct {
__IO uint8_t PRLL11;
__IO uint8_t PRLH11;
};
};
uint8_t RESERVED32[2];
__IO uint8_t GATEC8;
uint8_t RESERVED33[39];
__IO uint8_t PPGC13;
__IO uint8_t PPGC12;
uint8_t RESERVED34[2];
__IO uint8_t PPGC15;
__IO uint8_t PPGC14;
uint8_t RESERVED35[2];
union {
__IO uint16_t PRL12;
struct {
__IO uint8_t PRLL12;
__IO uint8_t PRLH12;
};
};
uint8_t RESERVED36[2];
union {
__IO uint16_t PRL13;
struct {
__IO uint8_t PRLL13;
__IO uint8_t PRLH13;
};
};
uint8_t RESERVED37[2];
union {
__IO uint16_t PRL14;
struct {
__IO uint8_t PRLL14;
__IO uint8_t PRLH14;
};
};
uint8_t RESERVED38[2];
union {
__IO uint16_t PRL15;
struct {
__IO uint8_t PRLL15;
__IO uint8_t PRLH15;
};
};
uint8_t RESERVED39[2];
__IO uint8_t GATEC12;
}FM3_MFT_PPG_TypeDef;
/******************************************************************************
* BT_PPG_MODULE
******************************************************************************/
/* Base Timer 0 PPG registers */
typedef struct
{
__IO uint16_t PRLL;
uint8_t RESERVED0[2];
__IO uint16_t PRLH;
uint8_t RESERVED1[2];
__IO uint16_t TMR;
uint8_t RESERVED2[2];
__IO uint16_t TMCR;
uint8_t RESERVED3[2];
__IO uint8_t STC;
__IO uint8_t TMCR2;
}FM3_BT_PPG_TypeDef;
/******************************************************************************
* BT_PWM_MODULE
******************************************************************************/
/* Base Timer 0 PWM registers */
typedef struct
{
__IO uint16_t PCSR;
uint8_t RESERVED0[2];
__IO uint16_t PDUT;
uint8_t RESERVED1[2];
__IO uint16_t TMR;
uint8_t RESERVED2[2];
__IO uint16_t TMCR;
uint8_t RESERVED3[2];
__IO uint8_t STC;
__IO uint8_t TMCR2;
}FM3_BT_PWM_TypeDef;
/******************************************************************************
* BT_RT_MODULE
******************************************************************************/
/* Base Timer 0 RT registers */
typedef struct
{
__IO uint16_t PCSR;
uint8_t RESERVED0[6];
__IO uint16_t TMR;
uint8_t RESERVED1[2];
__IO uint16_t TMCR;
uint8_t RESERVED2[2];
__IO uint8_t STC;
__IO uint8_t TMCR2;
}FM3_BT_RT_TypeDef;
/******************************************************************************
* BT_PWC_MODULE
******************************************************************************/
/* Base Timer 0 PWC registers */
typedef struct
{
uint8_t RESERVED0[4];
__IO uint16_t DTBF;
uint8_t RESERVED1[6];
__IO uint16_t TMCR;
uint8_t RESERVED2[2];
__IO uint8_t STC;
__IO uint8_t TMCR2;
}FM3_BT_PWC_TypeDef;
/******************************************************************************
* BTIOSEL03_MODULE
******************************************************************************/
/* Base Timer I/O selector channel 0 - channel 3 registers */
typedef struct
{
uint8_t RESERVED0;
__IO uint8_t BTSEL0123;
}FM3_BTIOSEL03_TypeDef;
/******************************************************************************
* BTIOSEL47_MODULE
******************************************************************************/
/* Base Timer I/O selector channel 4 - channel 7 registers */
typedef struct
{
uint8_t RESERVED0;
__IO uint8_t BTSEL4567;
}FM3_BTIOSEL47_TypeDef;
/******************************************************************************
* SBSSR_MODULE
******************************************************************************/
/* Software based Simulation Startup (Base Timer) register */
typedef struct
{
__IO uint16_t BTSSSR;
}FM3_SBSSR_TypeDef;
/******************************************************************************
* QPRC_MODULE
******************************************************************************/
/* Quad position and revolution counter channel 0 registers */
typedef struct
{
__IO uint16_t QPCR;
uint8_t RESERVED0[2];
__IO uint16_t QRCR;
uint8_t RESERVED1[2];
__IO uint16_t QPCCR;
uint8_t RESERVED2[2];
__IO uint16_t QPRCR;
uint8_t RESERVED3[2];
__IO uint16_t QMPR;
uint8_t RESERVED4[2];
union {
__IO uint16_t QICR;
struct {
__IO uint8_t QICRL;
__IO uint8_t QICRH;
};
};
uint8_t RESERVED5[2];
union {
__IO uint16_t QCR;
struct {
__IO uint8_t QCRL;
__IO uint8_t QCRH;
};
};
uint8_t RESERVED6[2];
__IO uint16_t QECR;
}FM3_QPRC_TypeDef;
/******************************************************************************
* ADC12_MODULE
******************************************************************************/
/* 12-bit ADC unit 0 registers */
typedef struct
{
__IO uint8_t ADSR;
__IO uint8_t ADCR;
uint8_t RESERVED0[6];
__IO uint8_t SFNS;
__IO uint8_t SCCR;
uint8_t RESERVED1[2];
union {
__IO uint32_t SCFD;
struct {
__IO uint16_t SCFDL;
__IO uint16_t SCFDH;
};
};
union {
__IO uint16_t SCIS23;
struct {
__IO uint8_t SCIS2;
__IO uint8_t SCIS3;
};
};
uint8_t RESERVED2[2];
union {
__IO uint16_t SCIS01;
struct {
__IO uint8_t SCIS0;
__IO uint8_t SCIS1;
};
};
uint8_t RESERVED3[2];
__IO uint8_t PFNS;
__IO uint8_t PCCR;
uint8_t RESERVED4[2];
union {
__IO uint32_t PCFD;
struct {
__IO uint16_t PCFDL;
__IO uint16_t PCFDH;
};
};
__IO uint8_t PCIS;
uint8_t RESERVED5[3];
__IO uint8_t CMPCR;
uint8_t RESERVED6;
__IO uint16_t CMPD;
union {
__IO uint16_t ADSS23;
struct {
__IO uint8_t ADSS2;
__IO uint8_t ADSS3;
};
};
uint8_t RESERVED7[2];
union {
__IO uint16_t ADSS01;
struct {
__IO uint8_t ADSS0;
__IO uint8_t ADSS1;
};
};
uint8_t RESERVED8[2];
union {
__IO uint16_t ADST01;
struct {
__IO uint8_t ADST1;
__IO uint8_t ADST0;
};
};
uint8_t RESERVED9[2];
__IO uint8_t ADCT;
uint8_t RESERVED10[3];
__IO uint8_t PRTSL;
__IO uint8_t SCTSL;
uint8_t RESERVED11[2];
__IO uint8_t ADCEN;
}FM3_ADC_TypeDef;
/******************************************************************************
* CRTRIM_MODULE
******************************************************************************/
/* CR trimming registers */
typedef struct
{
__IO uint8_t MCR_PSR;
uint8_t RESERVED0[3];
__IO uint16_t MCR_FTRM;
uint8_t RESERVED1[6];
__IO uint32_t MCR_RLR;
}FM3_CRTRIM_TypeDef;
/******************************************************************************
* EXTI_MODULE
******************************************************************************/
/* External interrupt registers */
typedef struct
{
__IO uint16_t ENIR;
uint8_t RESERVED0[2];
__IO uint16_t EIRR;
uint8_t RESERVED1[2];
__IO uint16_t EICL;
uint8_t RESERVED2[2];
__IO uint32_t ELVR;
uint8_t RESERVED3[4];
__IO uint8_t NMIRR;
uint8_t RESERVED4[3];
__IO uint8_t NMICL;
}FM3_EXTI_TypeDef;
/******************************************************************************
* INTREQ_MODULE
******************************************************************************/
/* Interrupt request read registers */
typedef struct
{
__IO uint32_t DRQSEL;
uint8_t RESERVED0[12];
__IO uint32_t EXC02MON;
__IO uint32_t IRQ00MON;
__IO uint32_t IRQ01MON;
__IO uint32_t IRQ02MON;
__IO uint32_t IRQ03MON;
__IO uint32_t IRQ04MON;
__IO uint32_t IRQ05MON;
__IO uint32_t IRQ06MON;
__IO uint32_t IRQ07MON;
__IO uint32_t IRQ08MON;
__IO uint32_t IRQ09MON;
__IO uint32_t IRQ10MON;
__IO uint32_t IRQ11MON;
__IO uint32_t IRQ12MON;
__IO uint32_t IRQ13MON;
__IO uint32_t IRQ14MON;
__IO uint32_t IRQ15MON;
__IO uint32_t IRQ16MON;
__IO uint32_t IRQ17MON;
__IO uint32_t IRQ18MON;
__IO uint32_t IRQ19MON;
__IO uint32_t IRQ20MON;
__IO uint32_t IRQ21MON;
__IO uint32_t IRQ22MON;
__IO uint32_t IRQ23MON;
__IO uint32_t IRQ24MON;
__IO uint32_t IRQ25MON;
__IO uint32_t IRQ26MON;
__IO uint32_t IRQ27MON;
__IO uint32_t IRQ28MON;
__IO uint32_t IRQ29MON;
__IO uint32_t IRQ30MON;
__IO uint32_t IRQ31MON;
__IO uint32_t IRQ32MON;
__IO uint32_t IRQ33MON;
__IO uint32_t IRQ34MON;
__IO uint32_t IRQ35MON;
__IO uint32_t IRQ36MON;
__IO uint32_t IRQ37MON;
__IO uint32_t IRQ38MON;
__IO uint32_t IRQ39MON;
__IO uint32_t IRQ40MON;
__IO uint32_t IRQ41MON;
__IO uint32_t IRQ42MON;
__IO uint32_t IRQ43MON;
__IO uint32_t IRQ44MON;
__IO uint32_t IRQ45MON;
__IO uint32_t IRQ46MON;
__IO uint32_t IRQ47MON;
}FM3_INTREQ_TypeDef;
/******************************************************************************
* GPIO_MODULE
******************************************************************************/
/* General purpose I/O registers */
typedef struct
{
__IO uint32_t PFR0;
__IO uint32_t PFR1;
__IO uint32_t PFR2;
__IO uint32_t PFR3;
__IO uint32_t PFR4;
__IO uint32_t PFR5;
__IO uint32_t PFR6;
uint8_t RESERVED0[4];
__IO uint32_t PFR8;
uint8_t RESERVED1[220];
__IO uint32_t PCR0;
__IO uint32_t PCR1;
__IO uint32_t PCR2;
__IO uint32_t PCR3;
__IO uint32_t PCR4;
__IO uint32_t PCR5;
__IO uint32_t PCR6;
uint8_t RESERVED2[228];
__IO uint32_t DDR0;
__IO uint32_t DDR1;
__IO uint32_t DDR2;
__IO uint32_t DDR3;
__IO uint32_t DDR4;
__IO uint32_t DDR5;
__IO uint32_t DDR6;
uint8_t RESERVED3[4];
__IO uint32_t DDR8;
uint8_t RESERVED4[220];
__IO uint32_t PDIR0;
__IO uint32_t PDIR1;
__IO uint32_t PDIR2;
__IO uint32_t PDIR3;
__IO uint32_t PDIR4;
__IO uint32_t PDIR5;
__IO uint32_t PDIR6;
uint8_t RESERVED5[4];
__IO uint32_t PDIR8;
uint8_t RESERVED6[220];
__IO uint32_t PDOR0;
__IO uint32_t PDOR1;
__IO uint32_t PDOR2;
__IO uint32_t PDOR3;
__IO uint32_t PDOR4;
__IO uint32_t PDOR5;
__IO uint32_t PDOR6;
uint8_t RESERVED7[4];
__IO uint32_t PDOR8;
uint8_t RESERVED8[220];
__IO uint32_t ADE;
uint8_t RESERVED9[124];
__IO uint32_t SPSR;
uint8_t RESERVED10[124];
__IO uint32_t EPFR00;
__IO uint32_t EPFR01;
__IO uint32_t EPFR02;
uint8_t RESERVED11[4];
__IO uint32_t EPFR04;
__IO uint32_t EPFR05;
__IO uint32_t EPFR06;
__IO uint32_t EPFR07;
__IO uint32_t EPFR08;
__IO uint32_t EPFR09;
__IO uint32_t EPFR10;
}FM3_GPIO_TypeDef;
/******************************************************************************
* LVD_MODULE
******************************************************************************/
/* Low voltage detection registers */
typedef struct
{
__IO uint8_t LVD_CTL;
uint8_t RESERVED0[3];
__IO uint8_t LVD_STR;
uint8_t RESERVED1[3];
__IO uint8_t LVD_CLR;
uint8_t RESERVED2[3];
__IO uint32_t LVD_RLR;
__IO uint8_t LVD_STR2;
}FM3_LVD_TypeDef;
/******************************************************************************
* USBCLK
******************************************************************************/
/* USB clock registers */
typedef struct
{
__IO uint8_t UCCR;
uint8_t RESERVED0[3];
__IO uint8_t UPCR1;
uint8_t RESERVED1[3];
__IO uint8_t UPCR2;
uint8_t RESERVED2[3];
__IO uint8_t UPCR3;
uint8_t RESERVED3[3];
__IO uint8_t UPCR4;
uint8_t RESERVED4[3];
__IO uint8_t UP_STR;
uint8_t RESERVED5[3];
__IO uint8_t UPINT_ENR;
uint8_t RESERVED6[3];
__IO uint8_t UPINT_CLR;
uint8_t RESERVED7[3];
__IO uint8_t UPINT_STR;
uint8_t RESERVED8[15];
__IO uint8_t USBEN;
}FM3_USBCLK_TypeDef;
/******************************************************************************
* CANPRE_MODULE
******************************************************************************/
/* CAN prescaler register */
typedef struct
{
__IO uint8_t CANPRE;
}FM3_CANPRE_TypeDef;
/******************************************************************************
* MFS03_UART_MODULE
******************************************************************************/
/* UART asynchronous channel 0 registers */
typedef struct
{
__IO uint8_t SMR;
__IO uint8_t SCR;
uint8_t RESERVED0[2];
__IO uint8_t ESCR;
__IO uint8_t SSR;
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
__IO uint16_t TDR;
};
uint8_t RESERVED2[2];
union {
__IO uint16_t BGR;
struct {
__IO uint8_t BGR0;
__IO uint8_t BGR1;
};
};
}FM3_MFS03_UART_TypeDef;
/******************************************************************************
* MFS03_CSIO_MODULE
******************************************************************************/
/* UART synchronous channel 0 registers */
typedef struct
{
__IO uint8_t SMR;
__IO uint8_t SCR;
uint8_t RESERVED0[2];
__IO uint8_t ESCR;
__IO uint8_t SSR;
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
__IO uint16_t TDR;
};
uint8_t RESERVED2[2];
union {
__IO uint16_t BGR;
struct {
__IO uint8_t BGR0;
__IO uint8_t BGR1;
};
};
}FM3_MFS03_CSIO_TypeDef;
/******************************************************************************
* MFS03_LIN_MODULE
******************************************************************************/
/* UART LIN channel 0 registers */
typedef struct
{
__IO uint8_t SMR;
__IO uint8_t SCR;
uint8_t RESERVED0[2];
__IO uint8_t ESCR;
__IO uint8_t SSR;
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
__IO uint16_t TDR;
};
uint8_t RESERVED2[2];
union {
__IO uint16_t BGR;
struct {
__IO uint8_t BGR0;
__IO uint8_t BGR1;
};
};
}FM3_MFS03_LIN_TypeDef;
/******************************************************************************
* MFS03_I2C_MODULE
******************************************************************************/
/* I2C channel 0 registers */
typedef struct
{
__IO uint8_t SMR;
__IO uint8_t IBCR;
uint8_t RESERVED0[2];
__IO uint8_t IBSR;
__IO uint8_t SSR;
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
__IO uint16_t TDR;
};
uint8_t RESERVED2[2];
union {
__IO uint16_t BGR;
struct {
__IO uint8_t BGR0;
__IO uint8_t BGR1;
};
};
uint8_t RESERVED3[2];
__IO uint8_t ISBA;
__IO uint8_t ISMK;
}FM3_MFS03_I2C_TypeDef;
/******************************************************************************
* MFS47_UART_MODULE
******************************************************************************/
/* UART asynchronous channel 4 registers */
typedef struct
{
__IO uint8_t SMR;
__IO uint8_t SCR;
uint8_t RESERVED0[2];
__IO uint8_t ESCR;
__IO uint8_t SSR;
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
__IO uint16_t TDR;
};
uint8_t RESERVED2[2];
union {
__IO uint16_t BGR;
struct {
__IO uint8_t BGR0;
__IO uint8_t BGR1;
};
};
uint8_t RESERVED3[6];
union {
__IO uint16_t FCR;
struct {
__IO uint8_t FCR0;
__IO uint8_t FCR1;
};
};
uint8_t RESERVED4[2];
union {
__IO uint16_t FBYTE;
struct {
__IO uint8_t FBYTE1;
__IO uint8_t FBYTE2;
};
};
}FM3_MFS47_UART_TypeDef;
/******************************************************************************
* MFS47_CSIO_MODULE
******************************************************************************/
/* UART synchronous channel 4 registers */
typedef struct
{
__IO uint8_t SMR;
__IO uint8_t SCR;
uint8_t RESERVED0[2];
__IO uint8_t ESCR;
__IO uint8_t SSR;
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
__IO uint16_t TDR;
};
uint8_t RESERVED2[2];
union {
__IO uint16_t BGR;
struct {
__IO uint8_t BGR0;
__IO uint8_t BGR1;
};
};
uint8_t RESERVED3[6];
union {
__IO uint16_t FCR;
struct {
__IO uint8_t FCR0;
__IO uint8_t FCR1;
};
};
uint8_t RESERVED4[2];
union {
__IO uint16_t FBYTE;
struct {
__IO uint8_t FBYTE1;
__IO uint8_t FBYTE2;
};
};
}FM3_MFS47_CSIO_TypeDef;
/******************************************************************************
* MFS47_LIN_MODULE
******************************************************************************/
/* UART LIN channel 4 registers */
typedef struct
{
__IO uint8_t SMR;
__IO uint8_t SCR;
uint8_t RESERVED0[2];
__IO uint8_t ESCR;
__IO uint8_t SSR;
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
__IO uint16_t TDR;
};
uint8_t RESERVED2[2];
union {
__IO uint16_t BGR;
struct {
__IO uint8_t BGR0;
__IO uint8_t BGR1;
};
};
uint8_t RESERVED3[6];
union {
__IO uint16_t FCR;
struct {
__IO uint8_t FCR0;
__IO uint8_t FCR1;
};
};
uint8_t RESERVED4[2];
union {
__IO uint16_t FBYTE;
struct {
__IO uint8_t FBYTE1;
__IO uint8_t FBYTE2;
};
};
}FM3_MFS47_LIN_TypeDef;
/******************************************************************************
* MFS47_I2C_MODULE
******************************************************************************/
/* I2C channel 4 registers */
typedef struct
{
__IO uint8_t SMR;
__IO uint8_t IBCR;
uint8_t RESERVED0[2];
__IO uint8_t IBSR;
__IO uint8_t SSR;
uint8_t RESERVED1[2];
union {
__IO uint16_t RDR;
__IO uint16_t TDR;
};
uint8_t RESERVED2[2];
union {
__IO uint16_t BGR;
struct {
__IO uint8_t BGR0;
__IO uint8_t BGR1;
};
};
uint8_t RESERVED3[2];
__IO uint8_t ISBA;
__IO uint8_t ISMK;
uint8_t RESERVED4[2];
union {
__IO uint16_t FCR;
struct {
__IO uint8_t FCR0;
__IO uint8_t FCR1;
};
};
uint8_t RESERVED5[2];
union {
__IO uint16_t FBYTE;
struct {
__IO uint8_t FBYTE1;
__IO uint8_t FBYTE2;
};
};
}FM3_MFS47_I2C_TypeDef;
/******************************************************************************
* CRC_MODULE
******************************************************************************/
/* CRC registers */
typedef struct
{
__IO uint8_t CRCCR;
uint8_t RESERVED0[3];
__IO uint32_t CRCINIT;
union {
__IO uint32_t CRCIN;
struct {
union {
__IO uint16_t CRCINL;
struct {
__IO uint8_t CRCINLL;
__IO uint8_t CRCINLH;
};
};
union {
__IO uint16_t CRCINH;
struct {
__IO uint8_t CRCINHL;
__IO uint8_t CRCINHH;
};
};
};
};
__IO uint32_t CRCR;
}FM3_CRC_TypeDef;
/******************************************************************************
* WC_MODULE
******************************************************************************/
/* Watch counter registers */
typedef struct
{
__IO uint8_t WCRD;
__IO uint8_t WCRL;
__IO uint8_t WCCR;
uint8_t RESERVED0[13];
__IO uint16_t CLK_SEL;
uint8_t RESERVED1[2];
__IO uint8_t CLK_EN;
}FM3_WC_TypeDef;
/******************************************************************************
* EXBUS_MODULE
******************************************************************************/
/* External bus interface registers */
typedef struct
{
__IO uint32_t MODE0;
__IO uint32_t MODE1;
__IO uint32_t MODE2;
__IO uint32_t MODE3;
uint8_t RESERVED0[12];
__IO uint32_t MODE7;
__IO uint32_t TIM0;
__IO uint32_t TIM1;
__IO uint32_t TIM2;
__IO uint32_t TIM3;
uint8_t RESERVED1[12];
__IO uint32_t TIM7;
__IO uint32_t AREA0;
__IO uint32_t AREA1;
__IO uint32_t AREA2;
__IO uint32_t AREA3;
uint8_t RESERVED2[12];
__IO uint32_t AREA7;
}FM3_EXBUS_TypeDef;
/******************************************************************************
* USB_MODULE
******************************************************************************/
/* USB channel 0 registers */
typedef struct
{
union {
__IO uint16_t HCNT;
struct {
__IO uint8_t HCNT0;
__IO uint8_t HCNT1;
};
};
uint8_t RESERVED0[2];
__IO uint8_t HIRQ;
__IO uint8_t HERR;
uint8_t RESERVED1[2];
__IO uint8_t HSTATE;
__IO uint8_t HFCOMP;
uint8_t RESERVED2[2];
union {
__IO uint16_t HRTIMER;
struct {
__IO uint8_t HRTIMER0;
__IO uint8_t HRTIMER1;
};
};
uint8_t RESERVED3[2];
__IO uint8_t HRTIMER2;
__IO uint8_t HADR;
uint8_t RESERVED4[2];
union {
__IO uint16_t HEOF;
struct {
__IO uint8_t HEOF0;
__IO uint8_t HEOF1;
};
};
uint8_t RESERVED5[2];
union {
__IO uint16_t HFRAME;
struct {
__IO uint8_t HFRAME0;
__IO uint8_t HFRAME1;
};
};
uint8_t RESERVED6[2];
__IO uint8_t HTOKEN;
uint8_t RESERVED7[3];
__IO uint16_t UDCC;
uint8_t RESERVED8[2];
__IO uint16_t EP0C;
uint8_t RESERVED9[2];
__IO uint16_t EP1C;
uint8_t RESERVED10[2];
__IO uint16_t EP2C;
uint8_t RESERVED11[2];
__IO uint16_t EP3C;
uint8_t RESERVED12[2];
__IO uint16_t EP4C;
uint8_t RESERVED13[2];
__IO uint16_t EP5C;
uint8_t RESERVED14[2];
__IO uint16_t TMSP;
uint8_t RESERVED15[2];
__IO uint8_t UDCS;
__IO uint8_t UDCIE;
uint8_t RESERVED16[2];
__IO uint16_t EP0IS;
uint8_t RESERVED17[2];
__IO uint16_t EP0OS;
uint8_t RESERVED18[2];
__IO uint16_t EP1S;
uint8_t RESERVED19[2];
__IO uint16_t EP2S;
uint8_t RESERVED20[2];
__IO uint16_t EP3S;
uint8_t RESERVED21[2];
__IO uint16_t EP4S;
uint8_t RESERVED22[2];
__IO uint16_t EP5S;
uint8_t RESERVED23[2];
union {
__IO uint16_t EP0DT;
struct {
__IO uint8_t EP0DTL;
__IO uint8_t EP0DTH;
};
};
uint8_t RESERVED24[2];
union {
__IO uint16_t EP1DT;
struct {
__IO uint8_t EP1DTL;
__IO uint8_t EP1DTH;
};
};
uint8_t RESERVED25[2];
union {
__IO uint16_t EP2DT;
struct {
__IO uint8_t EP2DTL;
__IO uint8_t EP2DTH;
};
};
uint8_t RESERVED26[2];
union {
__IO uint16_t EP3DT;
struct {
__IO uint8_t EP3DTL;
__IO uint8_t EP3DTH;
};
};
uint8_t RESERVED27[2];
union {
__IO uint16_t EP4DT;
struct {
__IO uint8_t EP4DTL;
__IO uint8_t EP4DTH;
};
};
uint8_t RESERVED28[2];
union {
__IO uint16_t EP5DT;
struct {
__IO uint8_t EP5DTL;
__IO uint8_t EP5DTH;
};
};
}FM3_USB_TypeDef;
/******************************************************************************
* DMAC_MODULE
******************************************************************************/
/* DMA controller */
typedef struct
{
__IO uint32_t DMACR;
uint8_t RESERVED0[12];
__IO uint32_t DMACA0;
__IO uint32_t DMACB0;
__IO uint32_t DMACSA0;
__IO uint32_t DMACDA0;
__IO uint32_t DMACA1;
__IO uint32_t DMACB1;
__IO uint32_t DMACSA1;
__IO uint32_t DMACDA1;
__IO uint32_t DMACA2;
__IO uint32_t DMACB2;
__IO uint32_t DMACSA2;
__IO uint32_t DMACDA2;
__IO uint32_t DMACA3;
__IO uint32_t DMACB3;
__IO uint32_t DMACSA3;
__IO uint32_t DMACDA3;
__IO uint32_t DMACA4;
__IO uint32_t DMACB4;
__IO uint32_t DMACSA4;
__IO uint32_t DMACDA4;
__IO uint32_t DMACA5;
__IO uint32_t DMACB5;
__IO uint32_t DMACSA5;
__IO uint32_t DMACDA5;
__IO uint32_t DMACA6;
__IO uint32_t DMACB6;
__IO uint32_t DMACSA6;
__IO uint32_t DMACDA6;
__IO uint32_t DMACA7;
__IO uint32_t DMACB7;
__IO uint32_t DMACSA7;
__IO uint32_t DMACDA7;
}FM3_DMAC_TypeDef;
/******************************************************************************
* CAN_MODULE
******************************************************************************/
/* CAN channel 0 registers */
typedef struct
{
__IO uint16_t CTRLR;
__IO uint16_t STATR;
__IO uint16_t ERRCNT;
__IO uint16_t BTR;
__IO uint16_t INTR;
__IO uint16_t TESTR;
__IO uint16_t BRPER;
uint8_t RESERVED0[2];
__IO uint16_t IF1CREQ;
__IO uint16_t IF1CMSK;
union {
__IO uint32_t IF1MSK;
struct {
__IO uint16_t IF1MSK1;
__IO uint16_t IF1MSK2;
};
};
union {
__IO uint32_t IF1ARB;
struct {
__IO uint16_t IF1ARB1;
__IO uint16_t IF1ARB2;
};
};
__IO uint16_t IF1MCTR;
uint8_t RESERVED1[2];
union {
__IO uint32_t IF1DTA_L;
struct {
__IO uint16_t IF1DTA1_L;
__IO uint16_t IF1DTA2_L;
};
};
union {
__IO uint32_t IF1DTB_L;
struct {
__IO uint16_t IF1DTB1_L;
__IO uint16_t IF1DTB2_L;
};
};
uint8_t RESERVED2[8];
union {
__IO uint32_t IF1DTA_B;
struct {
__IO uint16_t IF1DTA2_B;
__IO uint16_t IF1DTA1_B;
};
};
union {
__IO uint32_t IF1DTB_B;
struct {
__IO uint16_t IF1DTB2_B;
__IO uint16_t IF1DTB1_B;
};
};
uint8_t RESERVED3[8];
__IO uint16_t IF2CREQ;
__IO uint16_t IF2CMSK;
union {
__IO uint32_t IF2MSK;
struct {
__IO uint16_t IF2MSK1;
__IO uint16_t IF2MSK2;
};
};
union {
__IO uint32_t IF2ARB;
struct {
__IO uint16_t IF2ARB1;
__IO uint16_t IF2ARB2;
};
};
__IO uint16_t IF2MCTR;
uint8_t RESERVED4[2];
union {
__IO uint32_t IF2DTA_L;
struct {
__IO uint16_t IF2DTA1_L;
__IO uint16_t IF2DTA2_L;
};
};
union {
__IO uint32_t IF2DTB_L;
struct {
__IO uint16_t IF2DTB1_L;
__IO uint16_t IF2DTB2_L;
};
};
uint8_t RESERVED5[8];
union {
__IO uint32_t IF2DTA_B;
struct {
__IO uint16_t IF2DTA2_B;
__IO uint16_t IF2DTA1_B;
};
};
union {
__IO uint32_t IF2DTB_B;
struct {
__IO uint16_t IF2DTB2_B;
__IO uint16_t IF2DTB1_B;
};
};
uint8_t RESERVED6[24];
union {
__IO uint32_t TREQR;
struct {
__IO uint16_t TREQR1;
__IO uint16_t TREQR2;
};
};
uint8_t RESERVED7[12];
union {
__IO uint32_t NEWDT;
struct {
__IO uint16_t NEWDT1;
__IO uint16_t NEWDT2;
};
};
uint8_t RESERVED8[12];
union {
__IO uint32_t INTPND;
struct {
__IO uint16_t INTPND1;
__IO uint16_t INTPND2;
};
};
uint8_t RESERVED9[12];
union {
__IO uint32_t MSGVAL;
struct {
__IO uint16_t MSGVAL1;
__IO uint16_t MSGVAL2;
};
};
}FM3_CAN_TypeDef;
/******************************************************************************
* Peripheral memory map
******************************************************************************/
#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */
#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */
#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */
#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */
#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */
#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */
#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */
#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */
#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */
#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */
#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */
#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */
#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */
#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */
#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */
#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */
#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */
#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */
#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */
#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */
#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */
#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */
#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */
#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */
#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */
#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */
#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */
#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */
#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */
#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */
#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */
#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */
#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */
#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */
#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */
#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */
#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */
#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */
#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */
#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */
#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */
#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */
#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */
#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */
#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */
#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */
#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */
#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */
#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */
#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */
#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */
#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */
#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */
#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */
#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */
#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */
#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */
#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */
#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */
#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */
#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */
#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */
#define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */
#define FM3_CANPRES_BASE (FM3_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */
#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */
#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */
#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */
#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */
#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */
#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */
#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */
#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */
#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */
#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */
#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */
#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */
#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */
#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */
#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */
#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */
#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */
#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */
#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */
#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */
#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */
#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */
#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */
#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */
#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */
#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */
#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */
#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */
#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */
#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */
#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */
#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */
#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */
#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */
#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */
#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */
#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */
#define FM3_CAN0_BASE (FM3_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */
#define FM3_CAN1_BASE (FM3_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */
/******************************************************************************
* Peripheral declaration
******************************************************************************/
#define FM3_FLASH_IF ((FM3_FIF_TypeDef *)FM3_FLASH_IF_BASE)
#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE)
#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)
#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)
#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE)
#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE)
#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE)
#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE)
#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE)
#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE)
#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE)
#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE)
#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE)
#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE)
#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE)
#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE)
#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE)
#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE)
#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE)
#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE)
#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE)
#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE)
#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE)
#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE)
#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE)
#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE)
#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE)
#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE)
#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE)
#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE)
#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE)
#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE)
#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE)
#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE)
#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE)
#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE)
#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE)
#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE)
#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE)
#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE)
#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE)
#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE)
#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE)
#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE)
#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE)
#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE)
#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE)
#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE)
#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE)
#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE)
#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE)
#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE)
#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE)
#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE)
#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE)
#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE)
#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE)
#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE)
#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE)
#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE)
#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE)
#define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE)
#define FM3_CANPRES ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE)
#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE)
#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE)
#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE)
#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE)
#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE)
#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE)
#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE)
#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE)
#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE)
#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE)
#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE)
#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE)
#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE)
#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE)
#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE)
#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE)
#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE)
#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE)
#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE)
#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE)
#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE)
#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE)
#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE)
#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE)
#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE)
#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE)
#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE)
#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE)
#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE)
#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE)
#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE)
#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE)
#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE)
#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE)
#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE)
#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE)
#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE)
#define FM3_CAN0 ((FM3_CAN_TypeDef *)FM3_CAN0_BASE)
#define FM3_CAN1 ((FM3_CAN_TypeDef *)FM3_CAN1_BASE)
/******************************************************************************
* Peripheral Bit Band Alias declaration
******************************************************************************/
/* Flash interface registers */
#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL))
#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL))
#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL))
#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL))
#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL))
#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL))
#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL))
#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL))
#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL))
#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL))
#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL))
#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL))
#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL))
#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL))
#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL))
#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL))
#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL))
#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL))
#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL))
/* Clock and reset registers */
#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL))
#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL))
#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL))
#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL))
#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL))
#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL))
#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL))
#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL))
#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL))
#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL))
#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL))
#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL))
#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL))
#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL))
#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL))
#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL))
#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL))
#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL))
#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL))
#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL))
#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL))
#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL))
#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL))
#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL))
#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL))
#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL))
#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL))
#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL))
#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL))
#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL))
#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL))
#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL))
#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL))
#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL))
#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL))
#define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL))
#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL))
#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL))
#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL))
#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL))
#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL))
#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL))
#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL))
#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL))
#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL))
#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL))
#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL))
#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL))
#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL))
#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL))
#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL))
#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL))
#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL))
#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL))
#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL))
#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL))
#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL))
#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL))
#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL))
#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL))
#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL))
#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL))
#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL))
#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL))
#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL))
#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL))
#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL))
#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL))
#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL))
#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL))
#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL))
#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL))
#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL))
#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL))
#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL))
#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL))
#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL))
#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL))
#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL))
#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL))
#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL))
#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL))
#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL))
/* Hardware watchdog registers */
#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL))
#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL))
#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL))
/* Software watchdog registers */
#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL))
#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL))
#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL))
/* Dual timer 1/2 registers */
#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL))
#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL))
#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL))
#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL))
#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL))
#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL))
#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL))
#define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL))
#define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL))
#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL))
#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL))
#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL))
#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL))
#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL))
#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL))
#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL))
#define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL))
#define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL))
/* Multifunction Timer unit 0 Free Running Timer registers */
#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL))
#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL))
#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL))
#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL))
#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL))
#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL))
#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL))
#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL))
#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL))
#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL))
#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL))
#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL))
#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL))
#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL))
#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL))
#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL))
#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL))
#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL))
#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL))
#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL))
#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL))
#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL))
#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL))
#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL))
#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL))
#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL))
#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL))
#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL))
#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL))
#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL))
#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL))
#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL))
#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL))
#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL))
#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL))
#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL))
#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL))
#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL))
#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL))
#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL))
#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL))
#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL))
#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL))
#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL))
#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL))
#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL))
#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL))
#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL))
/* Multifunction Timer unit 0 Output Compare Unit registers */
#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL))
#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL))
#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL))
#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL))
#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL))
#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL))
#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL))
#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL))
#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL))
#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL))
#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL))
#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL))
#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL))
#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL))
#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL))
#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL))
#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL))
#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL))
#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL))
#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL))
#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL))
#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL))
#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL))
#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL))
#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL))
#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL))
#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL))
#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL))
#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL))
#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL))
#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL))
#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL))
#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL))
#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL))
#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL))
#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL))
#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL))
#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL))
#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL))
#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL))
#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL))
#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL))
#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL))
#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL))
#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL))
#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL))
#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL))
#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL))
#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL))
#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL))
#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL))
#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL))
#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL))
#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL))
#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL))
#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL))
#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL))
#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL))
#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL))
#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL))
#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL))
#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL))
#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL))
#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL))
#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL))
#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL))
#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL))
#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL))
#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL))
/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL))
#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL))
#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL))
#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL))
#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL))
#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL))
#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL))
#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL))
#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL))
#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL))
#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL))
#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL))
#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL))
#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL))
#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL))
#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL))
#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL))
#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL))
#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL))
#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL))
#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL))
#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL))
#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL))
#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL))
#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL))
#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL))
#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL))
#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL))
#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL))
#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL))
#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL))
#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL))
#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL))
#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL))
#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL))
#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL))
#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL))
#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL))
#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL))
#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL))
#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL))
#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL))
#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL))
#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL))
#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL))
#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL))
#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL))
#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL))
#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL))
#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL))
#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL))
#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL))
#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL))
#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL))
#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL))
#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL))
#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL))
#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL))
/* Multifunction Timer unit 0 Input Capture Unit registers */
#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL))
#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL))
#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL))
#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL))
#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL))
#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL))
#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL))
#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL))
#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL))
#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL))
#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL))
#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL))
#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL))
#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL))
#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL))
#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL))
#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL))
#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL))
#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL))
#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL))
#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL))
#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL))
#define bFM3_MFT0_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42400F18UL))
#define bFM3_MFT0_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42400F1CUL))
#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL))
#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL))
#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL))
#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL))
#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL))
#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL))
#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL))
#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL))
#define bFM3_MFT0_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42400F98UL))
#define bFM3_MFT0_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42400F9CUL))
#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL))
#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL))
/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL))
#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL))
#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL))
#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL))
#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL))
#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL))
#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL))
#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL))
#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL))
#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL))
#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL))
#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL))
#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL))
#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL))
#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL))
#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL))
#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL))
#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL))
#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL))
#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL))
#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL))
#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL))
#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL))
#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL))
#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL))
#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL))
#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL))
#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL))
#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL))
#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL))
/* Multifunction Timer unit 1 Free Running Timer registers */
#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL))
#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL))
#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL))
#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL))
#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL))
#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL))
#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL))
#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL))
#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL))
#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL))
#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL))
#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL))
#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL))
#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL))
#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL))
#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL))
#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL))
#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL))
#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL))
#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL))
#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL))
#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL))
#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL))
#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL))
#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL))
#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL))
#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL))
#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL))
#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL))
#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL))
#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL))
#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL))
#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL))
#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL))
#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL))
#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL))
#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL))
#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL))
#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL))
#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL))
#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL))
#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL))
#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL))
#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL))
#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL))
#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL))
#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL))
#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL))
/* Multifunction Timer unit 1 Output Compare Unit registers */
#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL))
#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL))
#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL))
#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL))
#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL))
#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL))
#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL))
#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL))
#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL))
#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL))
#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL))
#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL))
#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL))
#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL))
#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL))
#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL))
#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL))
#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL))
#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL))
#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL))
#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL))
#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL))
#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL))
#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL))
#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL))
#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL))
#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL))
#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL))
#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL))
#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL))
#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL))
#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL))
#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL))
#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL))
#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL))
#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL))
#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL))
#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL))
#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL))
#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL))
#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL))
#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL))
#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL))
#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL))
#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL))
#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL))
#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL))
#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL))
#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL))
#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL))
#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL))
#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL))
#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL))
#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL))
#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL))
#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL))
#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL))
#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL))
#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL))
#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL))
#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL))
#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL))
#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL))
#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL))
#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL))
#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL))
#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL))
#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL))
#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL))
/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL))
#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL))
#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL))
#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL))
#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL))
#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL))
#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL))
#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL))
#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL))
#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL))
#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL))
#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL))
#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL))
#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL))
#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL))
#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL))
#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL))
#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL))
#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL))
#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL))
#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL))
#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL))
#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL))
#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL))
#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL))
#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL))
#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL))
#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL))
#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL))
#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL))
#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL))
#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL))
#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL))
#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL))
#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL))
#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL))
#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL))
#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL))
#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL))
#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL))
#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL))
#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL))
#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL))
#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL))
#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL))
#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL))
#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL))
#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL))
#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL))
#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL))
#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL))
#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL))
#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL))
#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL))
#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL))
#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL))
#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL))
#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL))
/* Multifunction Timer unit 1 Input Capture Unit registers */
#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL))
#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL))
#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL))
#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL))
#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL))
#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL))
#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL))
#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL))
#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL))
#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL))
#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL))
#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL))
#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL))
#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL))
#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL))
#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL))
#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL))
#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL))
#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL))
#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL))
#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL))
#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL))
#define bFM3_MFT1_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42420F18UL))
#define bFM3_MFT1_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42420F1CUL))
#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL))
#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL))
#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL))
#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL))
#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL))
#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL))
#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL))
#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL))
#define bFM3_MFT1_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42420F98UL))
#define bFM3_MFT1_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42420F9CUL))
#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL))
#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL))
/* Multifunction Timer unit 1 ADC Start Compare Unit registers */
#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL))
#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL))
#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL))
#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL))
#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL))
#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL))
#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL))
#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL))
#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL))
#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL))
#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL))
#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL))
#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL))
#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL))
#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL))
#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL))
#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL))
#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL))
#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL))
#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL))
#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL))
#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL))
#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL))
#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL))
#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL))
#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL))
#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL))
#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL))
#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL))
#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL))
/* Multifunction Timer PPG registers */
#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL))
#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL))
#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL))
#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL))
#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL))
#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL))
#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL))
#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL))
#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL))
#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL))
#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL))
#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL))
#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL))
#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL))
#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL))
#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL))
#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL))
#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL))
#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL))
#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL))
#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL))
#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL))
#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL))
#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL))
#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL))
#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL))
#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL))
#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL))
#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL))
#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL))
#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL))
#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL))
#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL))
#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL))
#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL))
#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL))