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pigweed / third_party / github / FreeRTOS / FreeRTOS-Kernel / 9c0c37ab9b56f2c90085b78df2f58b5833e473db / . / FreeRTOS / Demo / CORTEX_R5_UltraScale_MPSoC / ZynqMP_ZCU102_hw_platform / psu_init_gpl.c
blob: d75ebacb3c47f3e6669d36eacef8b9a2c764c81c [file] [log] [blame]
/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
#include <xil_io.h>
#include <sleep.h>
#include "psu_init_gpl.h"
#define DPLL_CFG_LOCK_DLY 63
#define DPLL_CFG_LOCK_CNT 625
#define DPLL_CFG_LFHF 3
#define DPLL_CFG_CP 3
#define DPLL_CFG_RES 2
static int mask_pollOnValue(u32 add, u32 mask, u32 value);
static int mask_poll(u32 add, u32 mask);
static void mask_delay(u32 delay);
static u32 mask_read(u32 add, u32 mask);
static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly,
int d_lock_cnt, int d_lfhf, int d_cp, int d_res);
static
void PSU_Mask_Write(unsigned long offset, unsigned long mask,
unsigned long val)
{
unsigned long RegVal = 0x0;
RegVal = Xil_In32(offset);
RegVal &= ~(mask);
RegVal |= (val & mask);
Xil_Out32(offset, RegVal);
}
static
void prog_reg(unsigned long addr, unsigned long mask,
unsigned long shift,
unsigned long value)
{
int rdata = 0;
rdata = Xil_In32(addr);
rdata = rdata & (~mask);
rdata = rdata | (value << shift);
Xil_Out32(addr, rdata);
}
unsigned long psu_pll_init_data(void)
{
/*
* RPLL INIT
*/
/*
* Register : RPLL_CFG @ 0XFF5E0034
* PLL loop filter resistor control
* PSU_CRL_APB_RPLL_CFG_RES 0xc
* PLL charge pump control
* PSU_CRL_APB_RPLL_CFG_CP 0x3
* PLL loop filter high frequency capacitor control
* PSU_CRL_APB_RPLL_CFG_LFHF 0x3
* Lock circuit counter setting
* PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339
* Lock circuit configuration settings for lock windowsize
* PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU)
*/
PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E672C6CU);
/*##################################################################### */
/*
* UPDATE FB_DIV
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
* PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
* The integer portion of the feedback divider to the PLL
* PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00012D00U);
/*##################################################################### */
/*
* BY PASS PLL
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRL_APB_RPLL_CTRL_BYPASS 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
/*##################################################################### */
/*
* ASSERT RESET
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRL_APB_RPLL_CTRL_RESET 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
/*##################################################################### */
/*
* DEASSERT RESET
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRL_APB_RPLL_CTRL_RESET 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
/*##################################################################### */
/*
* CHECK PLL STATUS
*/
/*
* Register : PLL_STATUS @ 0XFF5E0040
* RPLL is locked
* PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1
* (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U)
*/
mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U);
/*##################################################################### */
/*
* REMOVE PLL BY PASS
*/
/*
* Register : RPLL_CTRL @ 0XFF5E0030
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRL_APB_RPLL_CTRL_BYPASS 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U)
*/
PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
/*##################################################################### */
/*
* Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048
* Divisor value for this clock.
* PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2
* Control for a clock that will be generated in the LPD, but used in the F
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U)
*/
PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET,
0x00003F00U, 0x00000200U);
/*##################################################################### */
/*
* RPLL FRAC CFG
*/
/*
* IOPLL INIT
*/
/*
* Register : IOPLL_CFG @ 0XFF5E0024
* PLL loop filter resistor control
* PSU_CRL_APB_IOPLL_CFG_RES 0x2
* PLL charge pump control
* PSU_CRL_APB_IOPLL_CFG_CP 0x4
* PLL loop filter high frequency capacitor control
* PSU_CRL_APB_IOPLL_CFG_LFHF 0x3
* Lock circuit counter setting
* PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258
* Lock circuit configuration settings for lock windowsize
* PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U);
/*##################################################################### */
/*
* UPDATE FB_DIV
*/
/*
* Register : IOPLL_CTRL @ 0XFF5E0020
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
* PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0
* The integer portion of the feedback divider to the PLL
* PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U);
/*##################################################################### */
/*
* BY PASS PLL
*/
/*
* Register : IOPLL_CTRL @ 0XFF5E0020
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRL_APB_IOPLL_CTRL_BYPASS 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
/*##################################################################### */
/*
* ASSERT RESET
*/
/*
* Register : IOPLL_CTRL @ 0XFF5E0020
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRL_APB_IOPLL_CTRL_RESET 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
/*##################################################################### */
/*
* DEASSERT RESET
*/
/*
* Register : IOPLL_CTRL @ 0XFF5E0020
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRL_APB_IOPLL_CTRL_RESET 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
/*##################################################################### */
/*
* CHECK PLL STATUS
*/
/*
* Register : PLL_STATUS @ 0XFF5E0040
* IOPLL is locked
* PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1
* (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U)
*/
mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U);
/*##################################################################### */
/*
* REMOVE PLL BY PASS
*/
/*
* Register : IOPLL_CTRL @ 0XFF5E0020
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRL_APB_IOPLL_CTRL_BYPASS 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
/*##################################################################### */
/*
* Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044
* Divisor value for this clock.
* PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3
* Control for a clock that will be generated in the LPD, but used in the F
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U)
*/
PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET,
0x00003F00U, 0x00000300U);
/*##################################################################### */
/*
* IOPLL FRAC CFG
*/
/*
* APU_PLL INIT
*/
/*
* Register : APLL_CFG @ 0XFD1A0024
* PLL loop filter resistor control
* PSU_CRF_APB_APLL_CFG_RES 0x2
* PLL charge pump control
* PSU_CRF_APB_APLL_CFG_CP 0x3
* PLL loop filter high frequency capacitor control
* PSU_CRF_APB_APLL_CFG_LFHF 0x3
* Lock circuit counter setting
* PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258
* Lock circuit configuration settings for lock windowsize
* PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)
*/
PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
/*##################################################################### */
/*
* UPDATE FB_DIV
*/
/*
* Register : APLL_CTRL @ 0XFD1A0020
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
* PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0
* The integer portion of the feedback divider to the PLL
* PSU_CRF_APB_APLL_CTRL_FBDIV 0x48
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRF_APB_APLL_CTRL_DIV2 0x1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U)
*/
PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U);
/*##################################################################### */
/*
* BY PASS PLL
*/
/*
* Register : APLL_CTRL @ 0XFD1A0020
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRF_APB_APLL_CTRL_BYPASS 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U)
*/
PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
/*##################################################################### */
/*
* ASSERT RESET
*/
/*
* Register : APLL_CTRL @ 0XFD1A0020
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRF_APB_APLL_CTRL_RESET 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U)
*/
PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
/*##################################################################### */
/*
* DEASSERT RESET
*/
/*
* Register : APLL_CTRL @ 0XFD1A0020
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRF_APB_APLL_CTRL_RESET 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
/*##################################################################### */
/*
* CHECK PLL STATUS
*/
/*
* Register : PLL_STATUS @ 0XFD1A0044
* APLL is locked
* PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1
* (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U)
*/
mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U);
/*##################################################################### */
/*
* REMOVE PLL BY PASS
*/
/*
* Register : APLL_CTRL @ 0XFD1A0020
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRF_APB_APLL_CTRL_BYPASS 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U)
*/
PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
/*##################################################################### */
/*
* Register : APLL_TO_LPD_CTRL @ 0XFD1A0048
* Divisor value for this clock.
* PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3
* Control for a clock that will be generated in the FPD, but used in the L
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U)
*/
PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET,
0x00003F00U, 0x00000300U);
/*##################################################################### */
/*
* APLL FRAC CFG
*/
/*
* DDR_PLL INIT
*/
/*
* Register : DPLL_CFG @ 0XFD1A0030
* PLL loop filter resistor control
* PSU_CRF_APB_DPLL_CFG_RES 0x2
* PLL charge pump control
* PSU_CRF_APB_DPLL_CFG_CP 0x3
* PLL loop filter high frequency capacitor control
* PSU_CRF_APB_DPLL_CFG_LFHF 0x3
* Lock circuit counter setting
* PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258
* Lock circuit configuration settings for lock windowsize
* PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)
*/
PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
/*##################################################################### */
/*
* UPDATE FB_DIV
*/
/*
* Register : DPLL_CTRL @ 0XFD1A002C
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
* PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0
* The integer portion of the feedback divider to the PLL
* PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRF_APB_DPLL_CTRL_DIV2 0x1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U)
*/
PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U);
/*##################################################################### */
/*
* BY PASS PLL
*/
/*
* Register : DPLL_CTRL @ 0XFD1A002C
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRF_APB_DPLL_CTRL_BYPASS 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U)
*/
PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
/*##################################################################### */
/*
* ASSERT RESET
*/
/*
* Register : DPLL_CTRL @ 0XFD1A002C
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRF_APB_DPLL_CTRL_RESET 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U)
*/
PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
/*##################################################################### */
/*
* DEASSERT RESET
*/
/*
* Register : DPLL_CTRL @ 0XFD1A002C
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRF_APB_DPLL_CTRL_RESET 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
/*##################################################################### */
/*
* CHECK PLL STATUS
*/
/*
* Register : PLL_STATUS @ 0XFD1A0044
* DPLL is locked
* PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1
* (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U)
*/
mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U);
/*##################################################################### */
/*
* REMOVE PLL BY PASS
*/
/*
* Register : DPLL_CTRL @ 0XFD1A002C
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRF_APB_DPLL_CTRL_BYPASS 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U)
*/
PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
/*##################################################################### */
/*
* Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C
* Divisor value for this clock.
* PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2
* Control for a clock that will be generated in the FPD, but used in the L
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U)
*/
PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET,
0x00003F00U, 0x00000200U);
/*##################################################################### */
/*
* DPLL FRAC CFG
*/
/*
* VIDEO_PLL INIT
*/
/*
* Register : VPLL_CFG @ 0XFD1A003C
* PLL loop filter resistor control
* PSU_CRF_APB_VPLL_CFG_RES 0x2
* PLL charge pump control
* PSU_CRF_APB_VPLL_CFG_CP 0x4
* PLL loop filter high frequency capacitor control
* PSU_CRF_APB_VPLL_CFG_LFHF 0x3
* Lock circuit counter setting
* PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258
* Lock circuit configuration settings for lock windowsize
* PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f
* Helper data. Values are to be looked up in a table from Data Sheet
* (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U)
*/
PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U);
/*##################################################################### */
/*
* UPDATE FB_DIV
*/
/*
* Register : VPLL_CTRL @ 0XFD1A0038
* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
* s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
* ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
* PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0
* The integer portion of the feedback divider to the PLL
* PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a
* This turns on the divide by 2 that is inside of the PLL. This does not c
* hange the VCO frequency, just the output frequency
* PSU_CRF_APB_VPLL_CTRL_DIV2 0x1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U)
*/
PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U);
/*##################################################################### */
/*
* BY PASS PLL
*/
/*
* Register : VPLL_CTRL @ 0XFD1A0038
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRF_APB_VPLL_CTRL_BYPASS 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U)
*/
PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U);
/*##################################################################### */
/*
* ASSERT RESET
*/
/*
* Register : VPLL_CTRL @ 0XFD1A0038
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRF_APB_VPLL_CTRL_RESET 1
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U)
*/
PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U);
/*##################################################################### */
/*
* DEASSERT RESET
*/
/*
* Register : VPLL_CTRL @ 0XFD1A0038
* Asserts Reset to the PLL. When asserting reset, the PLL must already be
* in BYPASS.
* PSU_CRF_APB_VPLL_CTRL_RESET 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U);
/*##################################################################### */
/*
* CHECK PLL STATUS
*/
/*
* Register : PLL_STATUS @ 0XFD1A0044
* VPLL is locked
* PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1
* (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U)
*/
mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U);
/*##################################################################### */
/*
* REMOVE PLL BY PASS
*/
/*
* Register : VPLL_CTRL @ 0XFD1A0038
* Bypasses the PLL clock. The usable clock will be determined from the POS
* T_SRC field. (This signal may only be toggled after 4 cycles of the old
* clock and 4 cycles of the new clock. This is not usually an issue, but d
* esigners must be aware.)
* PSU_CRF_APB_VPLL_CTRL_BYPASS 0
* PLL Basic Control
* (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U)
*/
PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U);
/*##################################################################### */
/*
* Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050
* Divisor value for this clock.
* PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3
* Control for a clock that will be generated in the FPD, but used in the L
* PD as a clock source for the peripheral clock muxes.
* (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U)
*/
PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET,
0x00003F00U, 0x00000300U);
/*##################################################################### */
/*
* VIDEO FRAC CFG
*/
return 1;
}
unsigned long psu_clock_init_data(void)
{
/*
* CLOCK CONTROL SLCR REGISTER
*/
/*
* Register : GEM3_REF_CTRL @ 0XFF5E005C
* Clock active for the RX channel
* PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U)
*/
PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET,
0x063F3F07U, 0x06010C00U);
/*##################################################################### */
/*
* Register : GEM_TSU_REF_CTRL @ 0XFF5E0100
* 6 bit divider
* PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0
* 6 bit divider
* PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U)
*/
PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010600U);
/*##################################################################### */
/*
* Register : USB0_BUS_REF_CTRL @ 0XFF5E0060
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U)
*/
PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET,
0x023F3F07U, 0x02010600U);
/*##################################################################### */
/*
* Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3
* 6 bit divider
* PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19
* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U)
*/
PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET,
0x023F3F07U, 0x02031900U);
/*##################################################################### */
/*
* Register : QSPI_REF_CTRL @ 0XFF5E0068
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U)
*/
PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010C00U);
/*##################################################################### */
/*
* Register : SDIO1_REF_CTRL @ 0XFF5E0070
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8
* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U)
*/
PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010800U);
/*##################################################################### */
/*
* Register : SDIO_CLK_CTRL @ 0XFF18030C
* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
* [51] 1: MIO [76]
* PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0
* SoC Debug Clock Control
* (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET,
0x00020000U, 0x00000000U);
/*##################################################################### */
/*
* Register : UART0_REF_CTRL @ 0XFF5E0074
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U)
*/
PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
/*##################################################################### */
/*
* Register : UART1_REF_CTRL @ 0XFF5E0078
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U)
*/
PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
/*##################################################################### */
/*
* Register : I2C0_REF_CTRL @ 0XFF5E0120
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U)
*/
PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
/*##################################################################### */
/*
* Register : I2C1_REF_CTRL @ 0XFF5E0124
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U)
*/
PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
/*##################################################################### */
/*
* Register : CAN1_REF_CTRL @ 0XFF5E0088
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U)
*/
PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
/*##################################################################### */
/*
* Register : CPU_R5_CTRL @ 0XFF5E0090
* Turing this off will shut down the OCM, some parts of the APM, and preve
* nt transactions going from the FPD to the LPD and could lead to system h
* ang
* PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U)
*/
PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U);
/*##################################################################### */
/*
* Register : IOU_SWITCH_CTRL @ 0XFF5E009C
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U)
*/
PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET,
0x01003F07U, 0x01000602U);
/*##################################################################### */
/*
* Register : PCAP_CTRL @ 0XFF5E00A4
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U)
*/
PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U);
/*##################################################################### */
/*
* Register : LPD_SWITCH_CTRL @ 0XFF5E00A8
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U)
*/
PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET,
0x01003F07U, 0x01000302U);
/*##################################################################### */
/*
* Register : LPD_LSBUS_CTRL @ 0XFF5E00AC
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U)
*/
PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET,
0x01003F07U, 0x01000F02U);
/*##################################################################### */
/*
* Register : DBG_LPD_CTRL @ 0XFF5E00B0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U)
*/
PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET,
0x01003F07U, 0x01000602U);
/*##################################################################### */
/*
* Register : ADMA_REF_CTRL @ 0XFF5E00B8
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U)
*/
PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET,
0x01003F07U, 0x01000302U);
/*##################################################################### */
/*
* Register : PL0_REF_CTRL @ 0XFF5E00C0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf
* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)
*/
PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F00U);
/*##################################################################### */
/*
* Register : AMS_REF_CTRL @ 0XFF5E0108
* 6 bit divider
* PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e
* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
* ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U)
*/
PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET,
0x013F3F07U, 0x01011E02U);
/*##################################################################### */
/*
* Register : DLL_REF_CTRL @ 0XFF5E0104
* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
* of the old clock and 4 cycles of the new clock. This is not usually an
* issue, but designers must be aware.)
* PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U)
*/
PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET,
0x00000007U, 0x00000000U);
/*##################################################################### */
/*
* Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128
* 6 bit divider
* PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf
* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
* only be toggled after 4 cycles of the old clock and 4 cycles of the new
* clock. This is not usually an issue, but designers must be aware.)
* PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U)
*/
PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET,
0x01003F07U, 0x01000F00U);
/*##################################################################### */
/*
* Register : SATA_REF_CTRL @ 0XFD1A00A0
* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
* is not usually an issue, but designers must be aware.)
* PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U)
*/
PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET,
0x01003F07U, 0x01000200U);
/*##################################################################### */
/*
* Register : PCIE_REF_CTRL @ 0XFD1A00B4
* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only
* be toggled after 4 cycles of the old clock and 4 cycles of the new cloc
* k. This is not usually an issue, but designers must be aware.)
* PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1
* 6 bit divider
* PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U)
*/
PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET,
0x01003F07U, 0x01000200U);
/*##################################################################### */
/*
* Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070
* 6 bit divider
* PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
* his signal may only be toggled after 4 cycles of the old clock and 4 cyc
* les of the new clock. This is not usually an issue, but designers must b
* e aware.)
* PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U)
*/
PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010500U);
/*##################################################################### */
/*
* Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074
* 6 bit divider
* PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
* his signal may only be toggled after 4 cycles of the old clock and 4 cyc
* les of the new clock. This is not usually an issue, but designers must b
* e aware.)
* PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U)
*/
PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010F03U);
/*##################################################################### */
/*
* Register : DP_STC_REF_CTRL @ 0XFD1A007C
* 6 bit divider
* PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1
* 6 bit divider
* PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe
* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
* led after 4 cycles of the old clock and 4 cycles of the new clock. This
* is not usually an issue, but designers must be aware.)
* PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U)
*/
PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET,
0x013F3F07U, 0x01010E03U);
/*##################################################################### */
/*
* Register : ACPU_CTRL @ 0XFD1A0060
* 6 bit divider
* PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1
* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft
* er 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock. For the half spee
* d APU Clock
* PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1
* Clock active signal. Switch to 0 to disable the clock. For the full spee
* d ACPUX Clock. This will shut off the high speed clock to the entire APU
* PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U)
*/
PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U);
/*##################################################################### */
/*
* Register : DBG_FPD_CTRL @ 0XFD1A0068
* 6 bit divider
* PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2
* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
* is not usually an issue, but designers must be aware.)
* PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U)
*/
PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET,
0x01003F07U, 0x01000200U);
/*##################################################################### */
/*
* Register : DDR_CTRL @ 0XFD1A0080
* 6 bit divider
* PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2
* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles
* of the old clock and 4 cycles of the new clock. This is not usually an i
* ssue, but designers must be aware.)
* PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U)
*/
PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U);
/*##################################################################### */
/*
* Register : GPU_REF_CTRL @ 0XFD1A0084
* 6 bit divider
* PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1
* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
* is not usually an issue, but designers must be aware.)
* PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock, which will stop c
* lock for GPU (and both Pixel Processors).
* PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1
* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
* k only to this Pixel Processor
* PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1
* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
* k only to this Pixel Processor
* PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U)
*/
PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET,
0x07003F07U, 0x07000100U);
/*##################################################################### */
/*
* Register : GDMA_REF_CTRL @ 0XFD1A00B8
* 6 bit divider
* PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
* er 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U)
*/
PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET,
0x01003F07U, 0x01000200U);
/*##################################################################### */
/*
* Register : DPDMA_REF_CTRL @ 0XFD1A00BC
* 6 bit divider
* PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
* er 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U)
*/
PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET,
0x01003F07U, 0x01000200U);
/*##################################################################### */
/*
* Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0
* 6 bit divider
* PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2
* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
* er 4 cycles of the old clock and 4 cycles of the new clock. This is not
* usually an issue, but designers must be aware.)
* PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U)
*/
PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET,
0x01003F07U, 0x01000203U);
/*##################################################################### */
/*
* Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4
* 6 bit divider
* PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5
* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
* is not usually an issue, but designers must be aware.)
* PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2
* Clock active signal. Switch to 0 to disable the clock
* PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U)
*/
PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET,
0x01003F07U, 0x01000502U);
/*##################################################################### */
/*
* Register : DBG_TSTMP_CTRL @ 0XFD1A00F8
* 6 bit divider
* PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2
* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
* gled after 4 cycles of the old clock and 4 cycles of the new clock. This
* is not usually an issue, but designers must be aware.)
* PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0
* This register controls this reference clock
* (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U)
*/
PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET,
0x00003F07U, 0x00000200U);
/*##################################################################### */
/*
* Register : IOU_TTC_APB_CLK @ 0XFF180380
* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se
* lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
* clock for the APB interface of TTC0
* PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0
* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se
* lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
* clock for the APB interface of TTC1
* PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0
* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se
* lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
* clock for the APB interface of TTC2
* PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0
* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se
* lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
* clock for the APB interface of TTC3
* PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0
* TTC APB clock select
* (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET,
0x000000FFU, 0x00000000U);
/*##################################################################### */
/*
* Register : WDT_CLK_SEL @ 0XFD610100
* System watchdog timer clock source selection: 0: Internal APB clock 1: E
* xternal (PL clock via EMIO or Pinout clock via MIO)
* PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0
* SWDT clock source select
* (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET,
0x00000001U, 0x00000000U);
/*##################################################################### */
/*
* Register : WDT_CLK_SEL @ 0XFF180300
* System watchdog timer clock source selection: 0: internal clock APB cloc
* k 1: external clock from PL via EMIO, or from pinout via MIO
* PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0
* SWDT clock source select
* (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET,
0x00000001U, 0x00000000U);
/*##################################################################### */
/*
* Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050
* System watchdog timer clock source selection: 0: internal clock APB cloc
* k 1: external clock pss_ref_clk
* PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0
* SWDT clock source select
* (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U)
*/
PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET,
0x00000001U, 0x00000000U);
/*##################################################################### */
return 1;
}
unsigned long psu_ddr_init_data(void)
{
/*
* DDR INITIALIZATION
*/
/*
* DDR CONTROLLER RESET
*/
/*
* Register : RST_DDR_SS @ 0XFD1A0108
* DDR block level reset inside of the DDR Sub System
* PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1
* DDR sub system block level reset
* (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U)
*/
PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U);
/*##################################################################### */
/*
* Register : MSTR @ 0XFD070000
* Indicates the configuration of the device used in the system. - 00 - x4
* device - 01 - x8 device - 10 - x16 device - 11 - x32 device
* PSU_DDRC_MSTR_DEVICE_CONFIG 0x1
* Choose which registers are used. - 0 - Original registers - 1 - Shadow r
* egisters
* PSU_DDRC_MSTR_FREQUENCY_MODE 0x0
* Only present for multi-rank configurations. Each bit represents one rank
* . For two-rank configurations, only bits[25:24] are present. - 1 - popul
* ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow
* ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others -
* Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
* k - 0011 - Two ranks - 1111 - Four ranks
* PSU_DDRC_MSTR_ACTIVE_RANKS 0x1
* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for
* mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur
* st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other
* values are reserved. This controls the burst size used to access the SDR
* AM. This must match the burst length mode register setting in the SDRAM.
* (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100)
* Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
* is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
* PSU_DDRC_MSTR_BURST_RDWR 0x4
* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low
* frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for
* normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC
* TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
* s bit must be set to '0'.
* PSU_DDRC_MSTR_DLL_OFF_MODE 0x0
* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full
* DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter
* DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is
* only supported when the SDRAM bus width is a multiple of 16, and quarter
* bus width mode is only supported when the SDRAM bus width is a multiple
* of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
* th refers to DQ bus width (excluding any ECC width).
* PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0
* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D
* RAM in normal mode (1N). This register can be changed, only when the Con
* troller is in self-refresh mode. This signal must be set the same value
* as MR3 bit A3. Note: Geardown mode is not supported if the configuration
* parameter MEMC_CMD_RTN2IDLE is set
* PSU_DDRC_MSTR_GEARDOWN_MODE 0x0
* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin
* g, all command signals (except chip select) are held for 2 clocks on the
* SDRAM bus. Chip select is asserted on the second cycle of the command N
* ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti
* ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
* s set Note: 2T timing is not supported in DDR4 geardown mode.
* PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0
* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci
* sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full
* bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer
* cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is
* disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl
* ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
* , and this bit must be set to '0'
* PSU_DDRC_MSTR_BURSTCHOP 0x0
* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
* evice in use Present only in designs configured to support LPDDR4.
* PSU_DDRC_MSTR_LPDDR4 0x0
* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
* in use Present only in designs configured to support DDR4.
* PSU_DDRC_MSTR_DDR4 0x1
* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
* evice in use Present only in designs configured to support LPDDR3.
* PSU_DDRC_MSTR_LPDDR3 0x0
* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
* evice in use Present only in designs configured to support LPDDR2.
* PSU_DDRC_MSTR_LPDDR2 0x0
* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
* vice in use Only present in designs that support DDR3.
* PSU_DDRC_MSTR_DDR3 0x0
* Master Register
* (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U)
*/
PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x41040010U);
/*##################################################################### */
/*
* Register : MRCTRL0 @ 0XFD070010
* Setting this register bit to 1 triggers a mode register read or write op
* eration. When the MR operation is complete, the uMCTL2 automatically cle
* ars this bit. The other register fields of this register must be written
* in a separate APB transaction, before setting this mr_wr bit. It is rec
* ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
* ating modes.
* PSU_DDRC_MRCTRL0_MR_WR 0x0
* Address of the mode register that is to be written to. - 0000 - MR0 - 00
* 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR
* 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data
* for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als
* o used for writing to control words of RDIMMs. In that case, it correspo
* nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[
* 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a
* s the bit[2:0] must be set to an appropriate value which is considered b
* oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
* DIMMs.
* PSU_DDRC_MRCTRL0_MR_ADDR 0x0
* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire
* d to access all ranks, so all bits should be set to 1. However, for mult
* i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess
* ary to access ranks individually. Examples (assume uMCTL2 is configured
* for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x
* 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
* ks 0, 1, 2 and 3
* PSU_DDRC_MRCTRL0_MR_RANK 0x3
* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b
* efore automatic SDRAM initialization routine or not. For DDR4, this bit
* can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init
* ialization. For LPDDR4, this bit can be used to program additional mode
* registers before automatic SDRAM initialization if necessary. Note: This
* must be cleared to 0 after completing Software operation. Otherwise, SD
* RAM initialization routine will not re-start. - 0 - Software interventio
* n is not allowed - 1 - Software intervention is allowed
* PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0
* Indicates whether the mode register operation is MRS in PDA mode or not
* - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
* PSU_DDRC_MRCTRL0_PDA_EN 0x0
* Indicates whether the mode register operation is MRS or WR/RD for MPR (o
* nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
* PSU_DDRC_MRCTRL0_MPR_EN 0x0
* Indicates whether the mode register operation is read or write. Only use
* d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
* PSU_DDRC_MRCTRL0_MR_TYPE 0x0
* Mode Register Read/Write Control Register 0. Note: Do not enable more th
* an one of the following fields simultaneously: - sw_init_int - pda_en -
* mpr_en
* (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U)
*/
PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U);
/*##################################################################### */
/*
* Register : DERATEEN @ 0XFD070020
* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us
* es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d
* esigns configured to support LPDDR4. The required number of cycles for d
* erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
* eriod, and rounding up the next integer.
* PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2
* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/
* LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
* ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
* PSU_DDRC_DERATEEN_DERATE_BYTE 0x0
* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl
* y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all
* LPDDR2 speed grades as derating value of +1.875 ns is less than a core_
* ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
* 75 ns is less than a core_ddrc_core_clk period or not.
* PSU_DDRC_DERATEEN_DERATE_VALUE 0x0
* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin
* g parameter derating is enabled using MR4 read value. Present only in de
* signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
* to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
* PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0
* Temperature Derate Enable Register
* (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U)
*/
PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U);
/*##################################################################### */
/*
* Register : DERATEINT @ 0XFD070024
* Interval between two MR4 reads, used to derate the timing parameters. Pr
* esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
* egister must not be set to zero
* PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000
* Temperature Derate Interval Register
* (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U)
*/
PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U);
/*##################################################################### */
/*
* Register : PWRCTL @ 0XFD070030
* Self refresh state is an intermediate state to enter to Self refresh pow
* er down state or exit Self refresh power down state for LPDDR4. This reg
* ister controls transition from the Self refresh state. - 1 - Prohibit tr
* ansition from Self refresh state - 0 - Allow transition from Self refres
* h state
* PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0
* A value of 1 to this register causes system to move to Self Refresh stat
* e immediately, as long as it is not in INIT or DPD/MPSM operating_mode.
* This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
* re Entry to Self Refresh - 0 - Software Exit from Self Refresh
* PSU_DDRC_PWRCTL_SELFREF_SW 0x0
* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode
* when the transaction store is empty. This register must be reset to '0'
* to bring uMCTL2 out of maximum power saving mode. Present only in desig
* ns configured to support DDR4. For non-DDR4, this register should not be
* set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if
* the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
* equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
* PSU_DDRC_PWRCTL_MPSM_EN 0x0
* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req
* uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted.
* Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only
* be asserted in Self Refresh. In DDR4, can be asserted in following: - i
* n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca
* n be asserted in following: - in Self Refresh - in Power Down - in Deep
* Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse
* rted in following: - in Self Refresh Power Down - in Power Down - during
* Normal operation (Clock Stop)
* PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0
* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the
* transaction store is empty. This register must be reset to '0' to bring
* uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM
* initialization on deep power-down exit. Present only in designs configu
* red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
* DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
* PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0
* If true then the uMCTL2 goes into power-down after a programmable number
* of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_
* x32). This register bit may be re-programmed during the course of normal
* operation.
* PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0
* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program
* mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.
* selfref_to_x32)'. This register bit may be re-programmed during the cour
* se of normal operation.
* PSU_DDRC_PWRCTL_SELFREF_EN 0x0
* Low Power Control Register
* (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U)
*/
PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U);
/*##################################################################### */
/*
* Register : PWRTMG @ 0XFD070034
* After this many clocks of NOP or deselect the uMCTL2 automatically puts
* the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
* en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
* PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40
* Minimum deep power-down time. For mDDR, value from the JEDEC specificati
* on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL
* .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE
* C specification is 500us. Unit: Multiples of 4096 clocks. Present only i
* n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
* ONLY.
* PSU_DDRC_PWRTMG_T_DPD_X4096 0x84
* After this many clocks of NOP or deselect the uMCTL2 automatically puts
* the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
* en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
* PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10
* Low Power Timing Register
* (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U)
*/
PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U);
/*##################################################################### */
/*
* Register : RFSHCTL0 @ 0XFD070050
* Threshold value in number of clock cycles before the critical refresh or
* page timer expires. A critical refresh is to be issued before this thre
* shold is reached. It is recommended that this not be changed from the de
* fault value, currently shown as 0x2. It must always be less than interna
* lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u
* sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i
* s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n
* om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
* cks.
* PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2
* If the refresh timer (tRFCnom, also known as tREFI) has expired at least
* once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then
* a speculative refresh may be performed. A speculative refresh is a refr
* esh performed at a time when refresh would be useful, but before it is a
* bsolutely required. When the SDRAM bus is idle for a period of time dete
* rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired
* at least once since the last refresh, then a speculative refresh is per
* formed. Speculative refreshes continues successively until there are no
* refreshes pending or until new reads or writes are issued to the uMCTL2.
* FOR PERFORMANCE ONLY.
* PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10
* The programmed value + 1 is the number of refresh timeouts that is allow
* ed to accumulate before traffic is blocked and the refreshes are forced
* to execute. Closing pages to perform a refresh is a one-time penalty tha
* t must be paid for each group of refreshes. Therefore, performing refres
* hes in a burst reduces the per-refresh penalty of these page closings. H
* igher numbers for RFSHCTL.refresh_burst slightly increases utilization;
* lower numbers decreases the worst-case latency associated with refreshes
* . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh
* For information on burst refresh feature refer to section 3.9 of DDR2 J
* EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe
* r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF
* I cycles using the burst refresh feature. In DDR4 mode, according to Fin
* e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre
* shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda
* tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens
* ure that tRFCmax is not violated due to a PHY-initiated update occurring
* shortly before a refresh burst was due. In this situation, the refresh
* burst will be delayed until the PHY-initiated update is complete.
* PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0
* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
* traffic to flow to other banks. Per bank refresh is not supported by all
* LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
* esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
* PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0
* Refresh Control Register 0
* (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U)
*/
PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U);
/*##################################################################### */
/*
* Register : RFSHCTL1 @ 0XFD070054
* Refresh timer start for rank 1 (only present in multi-rank configuration
* s). This is useful in staggering the refreshes to multiple ranks to help
* traffic to proceed. This is explained in Refresh Controls section of ar
* chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
* PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0
* Refresh timer start for rank 0 (only present in multi-rank configuration
* s). This is useful in staggering the refreshes to multiple ranks to help
* traffic to proceed. This is explained in Refresh Controls section of ar
* chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
* PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0
* Refresh Control Register 1
* (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U)
*/
PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U);
/*##################################################################### */
/*
* Register : RFSHCTL3 @ 0XFD070060
* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix
* ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11
* 0 - Enable on the fly 4x (not supported) - Everything else - reserved No
* te: The on-the-fly modes is not supported in this version of the uMCTL2.
* Note: This must be set up while the Controller is in reset or while the
* Controller is in self-refresh mode. Changing this during normal operati
* on is not allowed. Making this a dynamic register will be supported in f
* uture version of the uMCTL2.
* PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0
* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
* the refresh register(s) have been updated. The value is automatically up
* dated when exiting reset, so it does not need to be toggled initially.
* PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0
* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres
* h is disabled, the SoC core must generate refreshes using the registers
* reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a
* nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1
* , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4
* CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
* isable auto-refresh is not supported, and this bit must be set to '0'. T
* his register field is changeable on the fly.
* PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1
* Refresh Control Register 3
* (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U)
*/
PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U);
/*##################################################################### */
/*
* Register : RFSHTMG @ 0XFD070064
* tREFI: Average time interval between refreshes per rank (Specification:
* 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2,
* LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre
* shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE
* FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
* register should be set to tREFIpb For configurations with MEMC_FREQ_RAT
* IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val
* ue is different depending on the refresh mode. The user should program t
* he appropriate value from the spec based on the value programmed in the
* refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea
* ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
* an 0x1. Unit: Multiples of 32 clocks.
* PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81
* Used only when LPDDR3 memory type is connected. Should only be changed w
* hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r
* equired by some LPDDR3 devices which comply with earlier versions of the
* LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
* - tREFBW parameter used
* PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1
* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F
* REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t
* CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro
* undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using
* all-bank refreshes, the tRFCmin value in the above equations is equal to
* tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq
* uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
* equations is different depending on the refresh mode (fixed 1X,2X,4X) an
* d the device density. The user should program the appropriate value from
* the spec based on the 'refresh_mode' and the device density that is use
* d. Unit: Clocks.
* PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b
* Refresh Timing Register
* (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU)
*/
PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x0081808BU);
/*##################################################################### */
/*
* Register : ECCCFG0 @ 0XFD070070
* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
* SE_RMW is defined
* PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1
* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
* er 1 beat - all other settings are reserved for future use
* PSU_DDRC_ECCCFG0_ECC_MODE 0x0
* ECC Configuration Register 0
* (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U)
*/
PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U);
/*##################################################################### */
/*
* Register : ECCCFG1 @ 0XFD070074
* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da
* ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
* a_poison_en=1
* PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0
* Enable ECC data poisoning - introduces ECC errors on writes to address s
* pecified by the ECCPOISONADDR0/1 registers
* PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0
* ECC Configuration Register 1
* (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U)
*/
PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U);
/*##################################################################### */
/*
* Register : CRCPARCTL1 @ 0XFD0700C4
* The maximum number of DFI PHY clock cycles allowed from the assertion of
* the dfi_rddata_en signal to the assertion of each of the corresponding
* bits of the dfi_rddata_valid signal. This corresponds to the DFI timing
* parameter tphy_rdlat. Refer to PHY specification for correct value. This
* value it only used for detecting read data timeout when DDR4 retry is e
* nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value:
* - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r
* dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1
* : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d
* fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
* rdlat < 'd114 Unit: DFI Clocks
* PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10
* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa
* re has an option to read the mode registers in the DRAM before the hardw
* are begins the retry process - 1: Wait for software to read/write the mo
* de registers before hardware begins the retry. After software is done wi
* th its operations, it will clear the alert interrupt register bit - 0: H
* ardware can begin the retry right away after the dfi_alert_n pulse goes
* away. The value on this register is valid only when retry is enabled (PA
* RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t
* he software doesn't clear the interrupt register after handling the pari
* ty/CRC error, then the hardware will not begin the retry process and the
* system will hang. In the case of Parity/CRC error, there are two possib
* ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten
* t parity' mode register bit is NOT set: the commands sent during retry a
* nd normal operation are executed without parity checking. The value in t
* he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent
* parity' mode register bit is SET: Parity checking is done for commands s
* ent during retry and normal operation. If multiple errors occur before M
* R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
* t care'.
* PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1
* - 1: Enable command retry mechanism in case of C/A Parity or CRC error -
* 0: Disable command retry mechanism when C/A Parity or CRC features are
* enabled. Note that retry functionality is not supported if burst chop is
* enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF
* SHCTL3.dis_auto_refresh = 1)
* PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0
* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no
* t includes DM signal Present only in designs configured to support DDR4.
* PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0
* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio
* n of CRC The setting of this register should match the CRC mode register
* setting in the DRAM.
* PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0
* C/A Parity enable register - 1: Enable generation of C/A parity and dete
* ction of C/A parity error - 0: Disable generation of C/A parity and disa
* ble detection of C/A parity error If RCD's parity error detection or SDR
* AM's parity detection is enabled, this register should be 1.
* PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0
* CRC Parity Control Register1
* (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U)
*/
PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U);
/*##################################################################### */
/*
* Register : CRCPARCTL2 @ 0XFD0700C8
* Value from the DRAM spec indicating the maximum width of the dfi_alert_n
* pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M
* AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT
* _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i
* llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
* PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40
* Value from the DRAM spec indicating the maximum width of the dfi_alert_n
* pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX
* For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW
* .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille
* gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
* PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5
* Indicates the maximum duration in number of DRAM clock cycles for which
* a command should be held in the Command Retry FIFO before it is popped o
* ut. Every location in the Command Retry FIFO has an associated down coun
* ting timer that will use this register as the start value. The down coun
* ting starts when a command is loaded into the FIFO. The timer counts dow
* n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe
* d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err
* or occurs before the counter reaches zero. The counter is reset to 0, af
* ter all the commands in the FIFO are retried. Recommended(minimum) value
* s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK)
* + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten
* cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable
* d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R
* DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
* + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be
* in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n
* ) should be considered. Note 3: Use the worst case(longer) value for PHY
* Latencies/Board delay Note 4: The Recommended values are minimum value
* to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max
* value can be set to this register is defined below: - MEMC_BURST_LENGTH
* == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2
* Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b
* us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod
* e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C
* RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC=
* ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16
* Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full
* bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod
* e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC
* =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF
* ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma
* x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal
* .
* PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f
* CRC Parity Control Register2
* (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)
*/
PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU);
/*##################################################################### */
/*
* Register : INIT0 @ 0XFD0700D0
* If lower bit is enabled the SDRAM initialization routine is skipped. The
* upper bit decides what state the controller starts up in when reset is
* removed - 00 - SDRAM Intialization routine is run after power-up - 01 -
* SDRAM Intialization routine is skipped after power-up. Controller starts
* up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p
* ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ
* ation routine is run after power-up. Note: The only 2'b00 is supported f
* or LPDDR4 in this version of the uMCTL2.
* PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0
* Cycles to wait after driving CKE high to start the SDRAM initialization
* sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req
* uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD
* R3 typically requires this to be programmed for a delay of 200 us. LPDDR
* 4 typically requires this to be programmed for a delay of 2 us. For conf
* igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi
* ded by 2, and round it up to next integer value.
* PSU_DDRC_INIT0_POST_CKE_X1024 0x2
* Cycles to wait after reset before driving CKE high to start the SDRAM in
* itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi
* cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD
* DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati
* ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by
* 2, and round it up to next integer value.
* PSU_DDRC_INIT0_PRE_CKE_X1024 0x106
* SDRAM Initialization Register 0
* (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)
*/
PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U);
/*##################################################################### */
/*
* Register : INIT1 @ 0XFD0700D4
* Number of cycles to assert SDRAM reset signal during init sequence. This
* is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo
* r use with a DDR PHY, this should be set to a minimum of 1
* PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2
* Cycles to wait after completing the SDRAM initialization sequence before
* starting the dynamic scheduler. Unit: Counts of a global timer that pul
* ses every 32 clock cycles. There is no known specific requirement for th
* is; it may be set to zero.
* PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0
* Wait period before driving the OCD complete command to SDRAM. Unit: Coun
* ts of a global timer that pulses every 32 clock cycles. There is no know
* n specific requirement for this; it may be set to zero.
* PSU_DDRC_INIT1_PRE_OCD_X32 0x0
* SDRAM Initialization Register 1
* (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)
*/
PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U);
/*##################################################################### */
/*
* Register : INIT2 @ 0XFD0700D8
* Idle time after the reset command, tINIT4. Present only in designs confi
* gured to support LPDDR2. Unit: 32 clock cycles.
* PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23
* Time to wait after the first CKE high, tINIT2. Present only in designs c
* onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t
* ypically requires 5 x tCK delay.
* PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5
* SDRAM Initialization Register 2
* (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U)
*/
PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U);
/*##################################################################### */
/*
* Register : INIT3 @ 0XFD0700DC
* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he
* re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value
* loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP
* DDR3/LPDDR4 - Value to write to MR1 register
* PSU_DDRC_INIT3_MR 0x730
* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti
* ng in this register is ignored. The uMCTL2 sets those bits appropriately
* . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu
* ation mode training is enabled, this bit is set appropriately by the uMC
* TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/
* LPDDR3/LPDDR4 - Value to write to MR2 register
* PSU_DDRC_INIT3_EMR 0x301
* SDRAM Initialization Register 3
* (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U)
*/
PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U);
/*##################################################################### */
/*
* Register : INIT4 @ 0XFD0700E0
* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2
* register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus
* ed
* PSU_DDRC_INIT4_EMR2 0x20
* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3
* register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis
* ter
* PSU_DDRC_INIT4_EMR3 0x200
* SDRAM Initialization Register 4
* (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)
*/
PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U);
/*##################################################################### */
/*
* Register : INIT5 @ 0XFD0700E4
* ZQ initial calibration, tZQINIT. Present only in designs configured to s
* upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica
* lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir
* es 1 us.
* PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21
* Maximum duration of the auto initialization, tINIT5. Present only in des
* igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir
* es 10 us.
* PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4
* SDRAM Initialization Register 5
* (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U)
*/
PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U);
/*##################################################################### */
/*
* Register : INIT6 @ 0XFD0700E8
* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs
* only.
* PSU_DDRC_INIT6_MR4 0x0
* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs
* only.
* PSU_DDRC_INIT6_MR5 0x6c0
* SDRAM Initialization Register 6
* (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)
*/
PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U);
/*##################################################################### */
/*
* Register : INIT7 @ 0XFD0700EC
* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs
* only.
* PSU_DDRC_INIT7_MR6 0x819
* SDRAM Initialization Register 7
* (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U)
*/
PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U);
/*##################################################################### */
/*
* Register : DIMMCTL @ 0XFD0700F0
* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
* BG1 are NOT swapped even if Address Mirroring is enabled. This will be r
* equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp
* ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled.
* PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0
* Enable for BG1 bit of MRS command. BG1 bit of the mode register address
* is specified as RFU (Reserved for Future Use) and must be programmed to
* 0 during MRS. In case where DRAMs which do not have BG1 are attached and
* both the CA parity and the Output Inversion are enabled, this must be s
* et to 0, so that the calculation of CA parity will not include BG1 bit.
* Note: This has no effect on the address of any other memory accesses, or
* of software-driven mode register accesses. If address mirroring is enab
* led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En
* abled - 0 - Disabled
* PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1
* Enable for A17 bit of MRS command. A17 bit of the mode register address
* is specified as RFU (Reserved for Future Use) and must be programmed to
* 0 during MRS. In case where DRAMs which do not have A17 are attached and
* the Output Inversion are enabled, this must be set to 0, so that the ca
* lculation of CA parity will not include A17 bit. Note: This has no effec
* t on the address of any other memory accesses, or of software-driven mod
* e register accesses. - 1 - Enabled - 0 - Disabled
* PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0
* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM
* M implements the Output Inversion feature by default, which means that t
* he following address, bank address and bank group bits of B-side DRAMs a
* re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en
* sures that, for mode register accesses generated by the uMCTL2 during th
* e automatic initialization routine and enabling of a particular DDR4 fea
* ture, separate A-side and B-side mode register accesses are generated. F
* or B-side mode register accesses, these bits are inverted within the uMC
* TL2 to compensate for this RDIMM inversion. Note: This has no effect on
* the address of any other memory accesses, or of software-driven mode reg
* ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 -
* Do not implement output inversion for B-side DRAMs.
* PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0
* Address Mirroring Enable (for multi-rank UDIMM implementations and multi
* -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement
* address mirroring for odd ranks, which means that the following address
* , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7,
* A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t
* his bit ensures that, for mode register accesses during the automatic in
* itialization routine, these bits are swapped within the uMCTL2 to compen
* sate for this UDIMM/RDIMM swapping. In addition to the automatic initial
* ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th
* e automatic MRS access to enable/disable of a particular DDR4 feature. N
* ote: This has no effect on the address of any other memory accesses, or
* of software-driven mode register accesses. This is not supported for mDD
* R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1
* output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
* hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran
* ks, implement address mirroring for MRS commands to during initializatio
* n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp
* lements address mirroring) - 0 - Do not implement address mirroring
* PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0
* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM
* M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3
* or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of
* software driven MR commands (via MRCTRL0/MRCTRL1), where software is re
* sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se
* nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma
* nds to even and odd ranks seperately - 0 - Do not stagger accesses
* PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0
* DIMM Control Register
* (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U)
*/
PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U);
/*##################################################################### */
/*
* Register : RANKCTL @ 0XFD0700F4
* Only present for multi-rank configurations. Indicates the number of cloc
* ks of gap in data responses when performing consecutive writes to differ
* ent ranks. This is used to switch the delays in the PHY to match the ran
* k requirements. This value should consider both PHY requirement and ODT
* requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v
* alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by
* 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas
* ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc
* reased by 1. - ODT requirement: The value programmed in this register ta
* kes care of the ODT switch off timing requirement when switching ranks d
* uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1
* For configurations with MEMC_FREQ_RATIO=1, program this to the larger o
* f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_
* RATIO=2, program this to the larger value divided by two and round it up
* to the next integer.
* PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6
* Only present for multi-rank configurations. Indicates the number of cloc
* ks of gap in data responses when performing consecutive reads to differe
* nt ranks. This is used to switch the delays in the PHY to match the rank
* requirements. This value should consider both PHY requirement and ODT r
* equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va
* lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only),
* should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only
* ), should be increased by 1. - ODT requirement: The value programmed in
* this register takes care of the ODT switch off timing requirement when s
* witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1,
* program this to the larger of PHY requirement or ODT requirement. For co
* nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di
* vided by two and round it up to the next integer.
* PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6
* Only present for multi-rank configurations. Background: Reads to the sam
* e rank can be performed back-to-back. Reads to different ranks require a
* dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is
* to avoid possible data bus contention as well as to give PHY enough tim
* e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus
* access on a cycle-by-cycle basis; therefore after a read is scheduled,
* there are few clock cycles (determined by the value on RANKCTL.diff_rank
* _rd_gap register) in which only reads from the same rank are eligible to
* be scheduled. This prevents reads from other ranks from having fair acc
* ess to the data bus. This parameter represents the maximum number of rea
* ds that can be scheduled consecutively to the same rank. After this numb
* er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by
* the scheduler to allow all ranks a fair opportunity to be scheduled. Hig
* her numbers increase bandwidth utilization, lower numbers increase fairn
* ess. This feature can be DISABLED by setting this register to 0. When se
* t to 0, the Controller will stay on the same rank as long as commands ar
* e available for it. Minimum programmable value is 0 (feature disabled) a
* nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
* PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf
* Rank Control Register
* (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU)
*/
PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU);
/*##################################################################### */
/*
* Register : DRAMTMG0 @ 0XFD070100
* Minimum time between write and precharge to same bank. Unit: Clocks Spec
* ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks
* @400MHz and less for lower frequencies where: - WL = write latency - BL
* = burst length. This must match the value programmed in the BL bit of t
* he mode register to the SDRAM. BST (burst terminate) is not supported at
* present. - tWR = Write recovery time. This comes directly from the SDRA
* M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p
* arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the
* above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT
* IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u
* p to the next integer value.
* PSU_DDRC_DRAMTMG0_WR2PRE 0x11
* tFAW Valid only when 8 or more banks(or banks x bank groups) are present
* . In 8-bank design, at most 4 banks must be activated in a rolling windo
* w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi
* s to (tFAW/2) and round up to next integer value. In a 4-bank design, se
* t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration.
* Unit: Clocks
* PSU_DDRC_DRAMTMG0_T_FAW 0x10
* tRAS(max): Maximum time between activate and precharge to same bank. Thi
* s is the maximum time that a page can be kept open Minimum value of this
* register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO
* =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of
* 1024 clocks.
* PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24
* tRAS(min): Minimum time between activate and precharge to the same bank.
* For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA
* S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T
* mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th
* e next integer value. Unit: Clocks
* PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12
* SDRAM Timing Register 0
* (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U)
*/
PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U);
/*##################################################################### */
/*
* Register : DRAMTMG1 @ 0XFD070104
* tXP: Minimum time after power-down exit to any operation. For DDR3, this
* should be programmed to tXPDLL if slow powerdown exit is selected in MR
* 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf
* igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it
* up to the next integer value. Units: Clocks
* PSU_DDRC_DRAMTMG1_T_XP 0x4
* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL
* /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi
* ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2
* - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t
* RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4)
* - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_
* RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi
* gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo
* ve value by 2 and round it up to the next integer value. Unit: Clocks.
* PSU_DDRC_DRAMTMG1_RD2PRE 0x4
* tRC: Minimum time between activates to same bank. For configurations wit
* h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege
* r value. Unit: Clocks.
* PSU_DDRC_DRAMTMG1_T_RC 0x1a
* SDRAM Timing Register 1
* (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU)
*/
PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU);
/*##################################################################### */
/*
* Register : DRAMTMG2 @ 0XFD070108
* Set to WL Time from write command to write data on SDRAM interface. This
* must be set to WL. For mDDR, it should normally be set to 1. Note that,
* depending on the PHY, if using RDIMM, it may be necessary to use a valu
* e of WL + 1 to compensate for the extra cycle of latency through the RDI
* MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate
* d using the above equation by 2, and round it up to next integer. This r
* egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING
* is set), as the DFI read and write latencies defined in DFITMG0 and DFI
* TMG1 are sufficient for those protocols Unit: clocks
* PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7
* Set to RL Time from read command to read data on SDRAM interface. This m
* ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma
* t be necessary to use a value of RL + 1 to compensate for the extra cycl
* e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2
* , divide the value calculated using the above equation by 2, and round i
* t up to next integer. This register field is not required for DDR2 and D
* DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie
* s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit
* : clocks
* PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8
* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L
* PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di
* sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL
* LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL
* E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write
* command. Include time for bus turnaround and all per-bank, per-rank, an
* d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b
* urst length. This must match the value programmed in the BL bit of the m
* ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL
* E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE =
* read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d
* erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should
* be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal
* culated using the above equation by 2, and round it up to next integer.
* PSU_DDRC_DRAMTMG2_RD2WR 0x6
* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu
* m time from write command to read command for same bank group. In others
* , minimum time from write command to read command. Includes time for bus
* turnaround, recovery times, and all per-bank, per-rank, and global cons
* traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la
* tency - BL = burst length. This must match the value programmed in the B
* L bit of the mode register to the SDRAM - tWTR_L = internal write to rea
* d command delay for same bank group. This comes directly from the SDRAM
* specification. - tWTR = internal write to read command delay. This comes
* directly from the SDRAM specification. Add one extra cycle for LPDDR2/L
* PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid
* e the value calculated using the above equation by 2, and round it up to
* next integer.
* PSU_DDRC_DRAMTMG2_WR2RD 0xd
* SDRAM Timing Register 2
* (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU)
*/
PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU);
/*##################################################################### */
/*
* Register : DRAMTMG3 @ 0XFD07010C
* Time to wait after a mode register write or read (MRW or MRR). Present o
* nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty
* pically requires value of 5. LPDDR3 typically requires value of 10. LPDD
* R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist
* er is used for the time from a MRW/MRR to all other commands. For LDPDR3
* , this register is used for the time from a MRW/MRR to a MRW/MRR.
* PSU_DDRC_DRAMTMG3_T_MRW 0x5
* tMRD: Cycles to wait after a mode register write or read. Depending on t
* he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com
* mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim
* e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2,
* program this to (tMRD/2) and round it up to the next integer value. If
* C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
* PSU_DDRC_DRAMTMG3_T_MRD 0x4
* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com
* mand and following non-load mode command. If C/A parity for DDR4 is used
* , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or
* tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if
* using RDIMM, depending on the PHY, it may be necessary to use a value of
* tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a
* pplied to mode register writes by the RDIMM chip.
* PSU_DDRC_DRAMTMG3_T_MOD 0xc
* SDRAM Timing Register 3
* (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)
*/
PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU);
/*##################################################################### */
/*
* Register : DRAMTMG4 @ 0XFD070110
* tRCD - tAL: Minimum time from activate to read or write command to same
* bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD
* - tAL)/2) and round it up to the next integer value. Minimum value allow
* ed for this register is 1, which implies minimum (tRCD - tAL) value to b
* e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
* PSU_DDRC_DRAMTMG4_T_RCD 0x8
* DDR4: tCCD_L: This is the minimum time between two reads or two writes f
* or same bank group. Others: tCCD: This is the minimum time between two r
* eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t
* his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U
* nit: clocks.
* PSU_DDRC_DRAMTMG4_T_CCD 0x3
* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f
* or same bank group. Others: tRRD: Minimum time between activates from ba
* nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi
* s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni
* t: Clocks.
* PSU_DDRC_DRAMTMG4_T_RRD 0x3
* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ
* _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM
* C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t
* RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho
* uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
* PSU_DDRC_DRAMTMG4_T_RP 0x9
* SDRAM Timing Register 4
* (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U)
*/
PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030309U);
/*##################################################################### */
/*
* Register : DRAMTMG5 @ 0XFD070114
* This is the time before Self Refresh Exit that CK is maintained as a val
* id clock before issuing SRX. Specifies the clock stable time before SRX.
* Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK
* EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_
* FREQ_RATIO=2, program this to recommended value divided by two and round
* it up to next integer.
* PSU_DDRC_DRAMTMG5_T_CKSRX 0x6
* This is the time after Self Refresh Down Entry that CK is maintained as
* a valid clock. Specifies the clock disable delay after SRE. Recommended
* settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1
* - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations
* with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw
* o and round it up to next integer.
* PSU_DDRC_DRAMTMG5_T_CKSRE 0x6
* Minimum CKE low width for Self refresh or Self refresh power down entry
* to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF
* C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2:
* tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ
* _RATIO=2, program this to recommended value divided by two and round it
* up to next integer.
* PSU_DDRC_DRAMTMG5_T_CKESR 0x4
* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr
* esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP
* DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/
* non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration
* s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and
* round it up to the next integer value. Unit: Clocks.
* PSU_DDRC_DRAMTMG5_T_CKE 0x3
* SDRAM Timing Register 5
* (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U)
*/
PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U);
/*##################################################################### */
/*
* Register : DRAMTMG6 @ 0XFD070118
* This is the time after Deep Power Down Entry that CK is maintained as a
* valid clock. Specifies the clock disable delay after DPDE. Recommended s
* ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_
* FREQ_RATIO=2, program this to recommended value divided by two and round
* it up to next integer. This is only present for designs supporting mDDR
* or LPDDR2/LPDDR3 devices.
* PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1
* This is the time before Deep Power Down Exit that CK is maintained as a
* valid clock before issuing DPDX. Specifies the clock stable time before
* DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config
* urations with MEMC_FREQ_RATIO=2, program this to recommended value divid
* ed by two and round it up to next integer. This is only present for desi
* gns supporting mDDR or LPDDR2 devices.
* PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1
* This is the time before Clock Stop Exit that CK is maintained as a valid
* clock before issuing Clock Stop Exit. Specifies the clock stable time b
* efore next command after Clock Stop Exit. Recommended settings: - mDDR:
* 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio
* ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by
* two and round it up to next integer. This is only present for designs su
* pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
* PSU_DDRC_DRAMTMG6_T_CKCSX 0x4
* SDRAM Timing Register 6
* (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U)
*/
PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U);
/*##################################################################### */
/*
* Register : DRAMTMG7 @ 0XFD07011C
* This is the time after Power Down Entry that CK is maintained as a valid
* clock. Specifies the clock disable delay after PDE. Recommended setting
* s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration
* s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t
* wo and round it up to next integer. This is only present for designs sup
* porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
* PSU_DDRC_DRAMTMG7_T_CKPDE 0x6
* This is the time before Power Down Exit that CK is maintained as a valid
* clock before issuing PDX. Specifies the clock stable time before PDX. R
* ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c
* onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value
* divided by two and round it up to next integer. This is only present for
* designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
* PSU_DDRC_DRAMTMG7_T_CKPDX 0x6
* SDRAM Timing Register 7
* (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U)
*/
PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U);
/*##################################################################### */
/*
* Register : DRAMTMG8 @ 0XFD070120
* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and
* Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this
* to the above value divided by 2 and round up to next integer value. Unit
* : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com
* mands. Note: Ensure this is less than or equal to t_xs_x32.
* PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3
* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S
* elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th
* is to the above value divided by 2 and round up to next integer value. U
* nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to
* t_xs_x32.
* PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3
* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config
* urations with MEMC_FREQ_RATIO=2, program this to the above value divided
* by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
* Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
* PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd
* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi
* gurations with MEMC_FREQ_RATIO=2, program this to the above value divide
* d by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
* Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
* PSU_DDRC_DRAMTMG8_T_XS_X32 0x6
* SDRAM Timing Register 8
* (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U)
*/
PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x03030D06U);
/*##################################################################### */
/*
* Register : DRAMTMG9 @ 0XFD070124
* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o
* nly with MEMC_FREQ_RATIO=2
* PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0
* tCCD_S: This is the minimum time between two reads or two writes for dif
* ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m
* inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2
* , program this to (tCCD_S/2) and round it up to the next integer value.
* Present only in designs configured to support DDR4. Unit: clocks.
* PSU_DDRC_DRAMTMG9_T_CCD_S 0x2
* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif
* ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th
* is to (tRRD_S/2) and round it up to the next integer value. Present only
* in designs configured to support DDR4. Unit: Clocks.
* PSU_DDRC_DRAMTMG9_T_RRD_S 0x2
* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command
* for different bank group. Includes time for bus turnaround, recovery ti
* mes, and all per-bank, per-rank, and global constraints. Present only in
* designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr
* ite latency - PL = Parity latency - BL = burst length. This must match t
* he value programmed in the BL bit of the mode register to the SDRAM - tW
* TR_S = internal write to read command delay for different bank group. Th
* is comes directly from the SDRAM specification. For configurations with
* MEMC_FREQ_RATIO=2, divide the value calculated using the above equation
* by 2, and round it up to next integer.
* PSU_DDRC_DRAMTMG9_WR2RD_S 0xb
* SDRAM Timing Register 9
* (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU)
*/
PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002020BU);
/*##################################################################### */
/*
* Register : DRAMTMG11 @ 0XFD07012C
* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL
* L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2
* ) and round it up to the next integer value. Present only in designs con
* figured to support DDR4. Unit: Multiples of 32 clocks.
* PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70
* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For
* configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2
* )+1. Present only in designs configured to support DDR4. Unit: clocks.
* PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7
* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_
* FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int
* eger value. Present only in designs configured to support DDR4. Unit: Cl
* ocks.
* PSU_DDRC_DRAMTMG11_T_MPX_S 0x1
* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i
* n designs configured to support DDR4. Unit: Clocks. For configurations w
* ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat
* ion by 2, and round it up to next integer.
* PSU_DDRC_DRAMTMG11_T_CKMPE 0xe
* SDRAM Timing Register 11
* (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU)
*/
PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x7007010EU);
/*##################################################################### */
/*
* Register : DRAMTMG12 @ 0XFD070130
* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg
* er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr
* am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu
* e.
* PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2
* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat
* ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u
* p to next integer value.
* PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6
* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.
* For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2)
* and round it up to next integer value.
* PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8
* SDRAM Timing Register 12
* (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U)
*/
PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U);
/*##################################################################### */
/*
* Register : ZQCTL0 @ 0XFD070180
* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg
* ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration
* request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati
* on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre
* sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
* PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1
* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres
* h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2
* or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio
* n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i
* n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present
* for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
* PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0
* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC
* L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
* tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co
* mmands to different ranks do not overlap. - 0 - ZQ resistor is not share
* d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR
* 3/LPDDR4 devices.
* PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0
* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit.
* Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com
* mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4
* mode. This is only present for designs supporting DDR4 devices.
* PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0
* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe
* r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St
* art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO
* =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int
* eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th
* e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t
* o the next integer value. Unit: Clock cycles. This is only present for d
* esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
* PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100
* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of
* NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command
* is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t
* his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy
* cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP
* DDR3/LPDDR4 devices.
* PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40
* ZQ Control Register 0
* (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U)
*/
PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U);
/*##################################################################### */
/*
* Register : ZQCTL1 @ 0XFD070184
* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati
* on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_
* RATIO=2, program this to tZQReset/2 and round it up to the next integer
* value. Unit: Clock cycles. This is only present for designs supporting L
* PDDR2/LPDDR3/LPDDR4 devices.
* PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20
* Average interval to wait between automatically issuing ZQCS (ZQ calibrat
* ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR
* 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles
* . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3
* /LPDDR4 devices.
* PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc
* ZQ Control Register 1
* (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU)
*/
PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196DCU);
/*##################################################################### */
/*
* Register : DFITMG0 @ 0XFD070190
* Specifies the number of DFI clock cycles after an assertion or de-assert
* ion of the DFI control signals that the control signals at the PHY-DRAM
* interface reflect the assertion or de-assertion. If the DFI clock and th
* e memory clock are not phase-aligned, this timing parameter should be ro
* unded up to the next integer value. Note that if using RDIMM, it is nece
* ssary to increment this parameter by RDIMM's extra cycle of latency in t
* erms of DFI clock.
* PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4
* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
* sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
* is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
* - 1 in terms of SDR clock cycles Refer to PHY specification for correct
* value.
* PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1
* Time from the assertion of a read command on the DFI interface to the as
* sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
* ect value. This corresponds to the DFI parameter trddata_en. Note that,
* depending on the PHY, if using RDIMM, it may be necessary to use the val
* ue (CL + 1) in the calculation of trddata_en. This is to compensate for
* the extra cycle of latency through the RDIMM. Unit: Clocks
* PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb
* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
* ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
* in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
* i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
* clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
* n for correct value.
* PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1
* Specifies the number of clock cycles between when dfi_wrdata_en is asser
* ted to when the associated write data is driven on the dfi_wrdata signal
* . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
* specification for correct value. Note, max supported value is 8. Unit:
* Clocks
* PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2
* Write latency Number of clocks from the write command to write data enab
* le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
* lat. Refer to PHY specification for correct value.Note that, depending o
* n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
* in the calculation of tphy_wrlat. This is to compensate for the extra c
* ycle of latency through the RDIMM.
* PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb
* DFI Timing Register 0
* (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)
*/
PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU);
/*##################################################################### */
/*
* Register : DFITMG1 @ 0XFD070194
* Specifies the number of DFI PHY clocks between when the dfi_cs signal is
* asserted and when the associated command is driven. This field is used
* for CAL mode, should be set to '0' or the value which matches the CAL mo
* de register setting in the DRAM. If the PHY can add the latency for CAL
* mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
* PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0
* Specifies the number of DFI PHY clocks between when the dfi_cs signal is
* asserted and when the associated dfi_parity_in signal is driven.
* PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0
* Specifies the number of DFI clocks between when the dfi_wrdata_en signal
* is asserted and when the corresponding write data transfer is completed
* on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d
* elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set
* to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI
* 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va
* lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_
* RATIO=2, divide PHY's value by 2 and round up to next integer. If using
* DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
* PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3
* Specifies the number of DFI clock cycles from the assertion of the dfi_d
* ram_clk_disable signal on the DFI until the clock to the DRAM memory dev
* ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock
* and the memory clock are not phase aligned, this timing parameter should
* be rounded up to the next integer value.
* PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3
* Specifies the number of DFI clock cycles from the de-assertion of the df
* i_dram_clk_disable signal on the DFI until the first valid rising edge o
* f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the
* DFI clock and the memory clock are not phase aligned, this timing param
* eter should be rounded up to the next integer value.
* PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4
* DFI Timing Register 1
* (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U)
*/
PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U);
/*##################################################################### */
/*
* Register : DFILPCFG0 @ 0XFD070198
* Setting for DFI's tlp_resp time. Same value is used for both Power Down,
* Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s
* pecification onwards, recommends using a fixed value of 7 always.
* PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7
* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente
* red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32
* cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5
* 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles -
* 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553
* 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T
* his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices
* .
* PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0
* Enables DFI Low Power interface handshaking during Deep Power Down Entry
* /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup
* porting mDDR or LPDDR2/LPDDR3 devices.
* PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0
* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered
* . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc
* les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512
* cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9
* - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c
* ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
* PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0
* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex
* it. - 0 - Disabled - 1 - Enabled
* PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1
* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered.
* Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle
* s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy
* cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 -
* 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc
* les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
* PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0
* Enables DFI Low Power interface handshaking during Power Down Entry/Exit
* . - 0 - Disabled - 1 - Enabled
* PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1
* DFI Low Power Configuration Register 0
* (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U)
*/
PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U);
/*##################################################################### */
/*
* Register : DFILPCFG1 @ 0XFD07019C
* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is
* entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1
* - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x
* 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl
* es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC -
* 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi
* ted This is only present for designs supporting DDR4 devices.
* PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2
* Enables DFI Low Power interface handshaking during Maximum Power Saving
* Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d
* esigns supporting DDR4 devices.
* PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1
* DFI Low Power Configuration Register 1
* (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U)
*/
PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U);
/*##################################################################### */
/*
* Register : DFIUPD0 @ 0XFD0701A0
* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
* . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc
* _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically.
* PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0
* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
* following a self-refresh exit. The core must issue the dfi_ctrlupd_req
* signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct
* rlupd_req after exiting self-refresh.
* PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0
* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si
* gnal can assert. Lowest value to assign to this variable is 0x40. Unit:
* Clocks
* PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40
* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si
* gnal must be asserted. The uMCTL2 expects the PHY to respond within this
* time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup
* d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this
* variable is 0x3. Unit: Clocks
* PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3
* DFI Update Register 0
* (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U)
*/
PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U);
/*##################################################################### */
/*
* Register : DFIUPD1 @ 0XFD0701A4
* This is the minimum amount of time between uMCTL2 initiated DFI update r
* equests (which is executed whenever the uMCTL2 is idle). Set this number
* higher to reduce the frequency of update requests, which can have a sma
* ll impact on the latency of the first read request when the uMCTL2 is id
* le. Unit: 1024 clocks
* PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41
* This is the maximum amount of time between uMCTL2 initiated DFI update r
* equests. This timer resets with each update request; when the timer expi
* res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd
* _ackx is received. PHY can use this idle time to recalibrate the delay l
* ines to the DLLs. The DFI controller update is also used to reset PHY FI
* FO pointers in case of data capture errors. Updates are required to main
* tain calibration over PVT, but frequent updates may impact performance.
* Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must
* be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl
* ocks
* PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1
* DFI Update Register 1
* (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U)
*/
PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x004100E1U);
/*##################################################################### */
/*
* Register : DFIMISC @ 0XFD0701B0
* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal
* s are active low - 1: Signals are active high
* PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0
* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality.
* - 1 - PHY implements DBI functionality. Present only in designs configu
* red to support DDR4 and LPDDR4.
* PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0
* PHY initialization complete enable signal. When asserted the dfi_init_co
* mplete signal can be used to trigger SDRAM initialisation
* PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0
* DFI Miscellaneous Control Register
* (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U)
*/
PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U);
/*##################################################################### */
/*
* Register : DFITMG2 @ 0XFD0701B4
* >Number of clocks between when a read command is sent on the DFI control
* interface and when the associated dfi_rddata_cs signal is asserted. Thi
* s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe
* cification for correct value.
* PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9
* Number of clocks between when a write command is sent on the DFI control
* interface and when the associated dfi_wrdata_cs signal is asserted. Thi
* s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe
* cification for correct value.
* PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6
* DFI Timing Register 2
* (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U)
*/
PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000906U);
/*##################################################################### */
/*
* Register : DBICTL @ 0XFD0701C0
* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D
* BI is enabled. This signal must be set the same value as DRAM's mode reg
* ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b
* e set to 0. - LPDDR4: MR3[6]
* PSU_DDRC_DBICTL_RD_DBI_EN 0x0
* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ
* e DBI is enabled. This signal must be set the same value as DRAM's mode
* register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus
* t be set to 0. - LPDDR4: MR3[7]
* PSU_DDRC_DBICTL_WR_DBI_EN 0x0
* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi
* s signal must be set the same logical value as DRAM's mode register. - D
* DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th
* is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13
* [5] which is opposite polarity from this signal
* PSU_DDRC_DBICTL_DM_EN 0x1
* DM/DBI Control Register
* (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U)
*/
PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U);
/*##################################################################### */
/*
* Register : ADDRMAP0 @ 0XFD070200
* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t
* o 27, and 31 Internal Base: 6 The selected HIF address bit is determined
* by adding the internal base to the value of this field. If set to 31, r
* ank address bit 0 is set to 0.
* PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f
* Address Map Register 0
* (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU)
*/
PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU);
/*##################################################################### */
/*
* Register : ADDRMAP1 @ 0XFD070204
* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t
* o 29 and 31 Internal Base: 4 The selected HIF address bit is determined
* by adding the internal base to the value of this field. If set to 31, ba
* nk address bit 2 is set to 0.
* PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f
* Selects the HIF address bits used as bank address bit 1. Valid Range: 0
* to 30 Internal Base: 3 The selected HIF address bit for each of the bank
* address bits is determined by adding the internal base to the value of
* this field.
* PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa
* Selects the HIF address bits used as bank address bit 0. Valid Range: 0
* to 30 Internal Base: 2 The selected HIF address bit for each of the bank
* address bits is determined by adding the internal base to the value of
* this field.
* PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa
* Address Map Register 1
* (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)
*/
PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0A0AU);
/*##################################################################### */
/*
* Register : ADDRMAP2 @ 0XFD070208
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 5. - Half bus width mode: Selects the HIF address bit used as colu
* mn address bit 6. - Quarter bus width mode: Selects the HIF address bit
* used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base
* : 5 The selected HIF address bit is determined by adding the internal ba
* se to the value of this field. If set to 15, this column address bit is
* set to 0.
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 4. - Half bus width mode: Selects the HIF address bit used as colu
* mn address bit 5. - Quarter bus width mode: Selects the HIF address bit
* used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base:
* 4 The selected HIF address bit is determined by adding the internal bas
* e to the value of this field. If set to 15, this column address bit is s
* et to 0.
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 3. - Half bus width mode: Selects the HIF address bit used as colu
* mn address bit 4. - Quarter bus width mode: Selects the HIF address bit
* used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s
* elected HIF address bit is determined by adding the internal base to the
* value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1
* 6, it is required to program this to 0, hence register does not exist in
* this case.
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 2. - Half bus width mode: Selects the HIF address bit used as colu
* mn address bit 3. - Quarter bus width mode: Selects the HIF address bit
* used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s
* elected HIF address bit is determined by adding the internal base to the
* value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
* or 16, it is required to program this to 0.
* PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0
* Address Map Register 2
* (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U)
*/
PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U);
/*##################################################################### */
/*
* Register : ADDRMAP3 @ 0XFD07020C
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 9. - Half bus width mode: Selects the HIF address bit used as colu
* mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode:
* Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/
* LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
* HIF address bit is determined by adding the internal base to the value o
* f this field. If set to 15, this column address bit is set to 0. Note: P
* er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo
* r indicating auto-precharge, and hence no source address bit can be mapp
* ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit
* for auto-precharge in the CA bus and hence column bit 10 is used.
* PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 8. - Half bus width mode: Selects the HIF address bit used as colu
* mn address bit 9. - Quarter bus width mode: Selects the HIF address bit
* used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0
* to 7, and 15 Internal Base: 8 The selected HIF address bit is determine
* d by adding the internal base to the value of this field. If set to 15,
* this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi
* cation, column address bit 10 is reserved for indicating auto-precharge,
* and hence no source address bit can be mapped to column address bit 10.
* In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA
* bus and hence column bit 10 is used.
* PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 7. - Half bus width mode: Selects the HIF address bit used as colu
* mn address bit 8. - Quarter bus width mode: Selects the HIF address bit
* used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base:
* 7 The selected HIF address bit is determined by adding the internal bas
* e to the value of this field. If set to 15, this column address bit is s
* et to 0.
* PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 6. - Half bus width mode: Selects the HIF address bit used as colu
* mn address bit 7. - Quarter bus width mode: Selects the HIF address bit
* used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base:
* 6 The selected HIF address bit is determined by adding the internal bas
* e to the value of this field. If set to 15, this column address bit is s
* et to 0.
* PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0
* Address Map Register 3
* (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)
*/
PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x00000000U);
/*##################################################################### */
/*
* Register : ADDRMAP4 @ 0XFD070210
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m
* ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un
* used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7,
* and 15 Internal Base: 11 The selected HIF address bit is determined by
* adding the internal base to the value of this field. If set to 15, this
* column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio
* n, column address bit 10 is reserved for indicating auto-precharge, and
* hence no source address bit can be mapped to column address bit 10. In L
* PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus
* and hence column bit 10 is used.
* PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf
* - Full bus width mode: Selects the HIF address bit used as column addres
* s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the
* HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)
* . - Quarter bus width mode: UNUSED. To make it unused, this must be tied
* to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
* address bit is determined by adding the internal base to the value of t
* his field. If set to 15, this column address bit is set to 0. Note: Per
* JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i
* ndicating auto-precharge, and hence no source address bit can be mapped
* to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
* auto-precharge in the CA bus and hence column bit 10 is used.
* PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf
* Address Map Register 4
* (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU)
*/
PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU);
/*##################################################################### */
/*
* Register : ADDRMAP5 @ 0XFD070214
* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t
* o 11, and 15 Internal Base: 17 The selected HIF address bit is determine
* d by adding the internal base to the value of this field. If set to 15,
* row address bit 11 is set to 0.
* PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8
* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran
* ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row
* address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro
* w address bit 10) The selected HIF address bit for each of the row addre
* ss bits is determined by adding the internal base to the value of this f
* ield. When value 15 is used the values of row address bits 2 to 10 are d
* efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
* PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf
* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t
* o 11 Internal Base: 7 The selected HIF address bit for each of the row a
* ddress bits is determined by adding the internal base to the value of th
* is field.
* PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8
* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t
* o 11 Internal Base: 6 The selected HIF address bit for each of the row a
* ddress bits is determined by adding the internal base to the value of th
* is field.
* PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8
* Address Map Register 5
* (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)
*/
PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x080F0808U);
/*##################################################################### */
/*
* Register : ADDRMAP6 @ 0XFD070218
* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1
* - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]=
* =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use.
* All addresses are valid Present only in designs configured to support L
* PDDR3.
* PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0
* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t
* o 11, and 15 Internal Base: 21 The selected HIF address bit is determine
* d by adding the internal base to the value of this field. If set to 15,
* row address bit 15 is set to 0.
* PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf
* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t
* o 11, and 15 Internal Base: 20 The selected HIF address bit is determine
* d by adding the internal base to the value of this field. If set to 15,
* row address bit 14 is set to 0.
* PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8
* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t
* o 11, and 15 Internal Base: 19 The selected HIF address bit is determine
* d by adding the internal base to the value of this field. If set to 15,
* row address bit 13 is set to 0.
* PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8
* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t
* o 11, and 15 Internal Base: 18 The selected HIF address bit is determine
* d by adding the internal base to the value of this field. If set to 15,
* row address bit 12 is set to 0.
* PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8
* Address Map Register 6
* (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)
*/
PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x0F080808U);
/*##################################################################### */
/*
* Register : ADDRMAP7 @ 0XFD07021C
* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t
* o 10, and 15 Internal Base: 23 The selected HIF address bit is determine
* d by adding the internal base to the value of this field. If set to 15,
* row address bit 17 is set to 0.
* PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf
* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t
* o 11, and 15 Internal Base: 22 The selected HIF address bit is determine
* d by adding the internal base to the value of this field. If set to 15,
* row address bit 16 is set to 0.
* PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf
* Address Map Register 7
* (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU)
*/
PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU);
/*##################################################################### */
/*
* Register : ADDRMAP8 @ 0XFD070220
* Selects the HIF address bits used as bank group address bit 1. Valid Ran
* ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea
* ch of the bank group address bits is determined by adding the internal b
* ase to the value of this field. If set to 31, bank group address bit 1 i
* s set to 0.
* PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8
* Selects the HIF address bits used as bank group address bit 0. Valid Ran
* ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th
* e bank group address bits is determined by adding the internal base to t
* he value of this field.
* PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8
* Address Map Register 8
* (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U)
*/
PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00000808U);
/*##################################################################### */
/*
* Register : ADDRMAP9 @ 0XFD070224
* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t
* o 11 Internal Base: 11 The selected HIF address bit for each of the row
* address bits is determined by adding the internal base to the value of t
* his field. This register field is used only when ADDRMAP5.addrmap_row_b2
* _10 is set to value 15.
* PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8
* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t
* o 11 Internal Base: 10 The selected HIF address bit for each of the row
* address bits is determined by adding the internal base to the value of t
* his field. This register field is used only when ADDRMAP5.addrmap_row_b2
* _10 is set to value 15.
* PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8
* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t
* o 11 Internal Base: 9 The selected HIF address bit for each of the row a
* ddress bits is determined by adding the internal base to the value of th
* is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
* 10 is set to value 15.
* PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8
* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t
* o 11 Internal Base: 8 The selected HIF address bit for each of the row a
* ddress bits is determined by adding the internal base to the value of th
* is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
* 10 is set to value 15.
* PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8
* Address Map Register 9
* (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U)
*/
PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x08080808U);
/*##################################################################### */
/*
* Register : ADDRMAP10 @ 0XFD070228
* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t
* o 11 Internal Base: 15 The selected HIF address bit for each of the row
* address bits is determined by adding the internal base to the value of t
* his field. This register field is used only when ADDRMAP5.addrmap_row_b2
* _10 is set to value 15.
* PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8
* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t
* o 11 Internal Base: 14 The selected HIF address bit for each of the row
* address bits is determined by adding the internal base to the value of t
* his field. This register field is used only when ADDRMAP5.addrmap_row_b2
* _10 is set to value 15.
* PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8
* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t
* o 11 Internal Base: 13 The selected HIF address bit for each of the row
* address bits is determined by adding the internal base to the value of t
* his field. This register field is used only when ADDRMAP5.addrmap_row_b2
* _10 is set to value 15.
* PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8
* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t
* o 11 Internal Base: 12 The selected HIF address bit for each of the row
* address bits is determined by adding the internal base to the value of t
* his field. This register field is used only when ADDRMAP5.addrmap_row_b2
* _10 is set to value 15.
* PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8
* Address Map Register 10
* (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U)
*/
PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x08080808U);
/*##################################################################### */
/*
* Register : ADDRMAP11 @ 0XFD07022C
* Selects the HIF address bits used as row address bit 10. Valid Range: 0
* to 11 Internal Base: 16 The selected HIF address bit for each of the row
* address bits is determined by adding the internal base to the value of
* this field. This register field is used only when ADDRMAP5.addrmap_row_b
* 2_10 is set to value 15.
* PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8
* Address Map Register 11
* (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U)
*/
PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000008U);
/*##################################################################### */
/*
* Register : ODTCFG @ 0XFD070240
* Cycles to hold ODT for a write command. The minimum supported value is 2
* . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800
* ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D
* DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR
* EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (
* not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
* PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6
* The delay, in clock cycles, from issuing a write command to setting ODT
* values associated with that command. ODT setting must remain constant fo
* r the entire time that DQS is driven by the uMCTL2. Recommended values:
* DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL +
* AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo
* r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust
* for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
* PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0
* Cycles to hold ODT for a read command. The minimum supported value is 2.
* Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) -
* BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8
* : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p
* reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) +
* RU(tODTon(max)/tCK)
* PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6
* The delay, in clock cycles, from issuing a read command to setting ODT v
* alues associated with that command. ODT setting must remain constant for
* the entire time that DQS is driven by the uMCTL2. Recommended values: D
* DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL
* - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C
* WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat
* (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
* write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre
* amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su
* pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R
* U(tODTon(max)/tCK)
* PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0
* ODT Configuration Register
* (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U)
*/
PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U);
/*##################################################################### */
/*
* Register : ODTMAP @ 0XFD070244
* Indicates which remote ODTs must be turned on during a read from rank 1.
* Each rank has a remote ODT (in the SDRAM) which can be turned on by set
* ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
* s controlled by bit next to the LSB, etc. For each rank, set its bit to
* 1 to enable its ODT. Present only in configurations that have 2 or more
* ranks
* PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0
* Indicates which remote ODTs must be turned on during a write to rank 1.
* Each rank has a remote ODT (in the SDRAM) which can be turned on by sett