/** | |
****************************************************************************** | |
* @file stm32f10x.h | |
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. | |
* This file contains all the peripheral register's definitions, bits | |
* definitions and memory mapping for STM32F10x Connectivity line, High | |
* density, Medium density and Low density devices. | |
* @author STMicroelectronics - MCD Application Team | |
* @version V3.1.0RC1 | |
* @date 05/07/2009 | |
****************************************************************************** | |
* | |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS | |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE | |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY | |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING | |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE | |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. | |
* | |
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> | |
****************************************************************************** | |
*/ | |
/** @addtogroup CMSIS | |
* @{ | |
*/ | |
/** @addtogroup stm32f10x | |
* @{ | |
*/ | |
#ifndef __STM32F10x_H | |
#define __STM32F10x_H | |
/** @addtogroup Library_configuration_section | |
* @{ | |
*/ | |
/* Uncomment the line below according to the target STM32 device used in your | |
application | |
*/ | |
#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL) | |
/* #define STM32F10X_LD */ /*!< STM32 Low density devices */ | |
/* #define STM32F10X_MD */ /*!< STM32 Medium density devices */ | |
/* #define STM32F10X_HD */ /*!< STM32 High density devices */ | |
#define STM32F10X_CL /*!< STM32 Connectivity line devices */ | |
#endif | |
/* Tip: To avoid modifying this file each time you need to switch between these | |
devices, you can define the device in your toolchain compiler preprocessor. | |
- Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers | |
where the Flash memory density ranges between 16 and 32 Kbytes. | |
- Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers | |
where the Flash memory density ranges between 64 and 128 Kbytes. | |
- High density devices are STM32F101xx and STM32F103xx microcontrollers where | |
the Flash memory density ranges between 256 and 512 Kbytes. | |
- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. | |
*/ | |
#if !defined USE_STDPERIPH_DRIVER | |
/** | |
* @brief Comment the line below if you will not use the peripherals drivers. | |
In this case, these drivers will not be included and the application code will | |
be based on direct access to peripherals registers | |
*/ | |
/*#define USE_STDPERIPH_DRIVER*/ | |
#endif | |
/** | |
* @brief In the following line adjust the value of External High Speed oscillator (HSE) | |
used in your application | |
*/ | |
#ifdef STM32F10X_CL | |
#define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ | |
#else | |
#define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ | |
#endif /* STM32F10X_CL */ | |
/** | |
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup | |
Timeout value | |
*/ | |
#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */ | |
#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ | |
/*!< [31:16] STM32F10x Standard Peripheral Library main version */ | |
#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) | |
/*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ | |
#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) | |
/*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ | |
#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) | |
/*!< STM32F10x Standard Peripheral Library version number */ | |
#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ | |
| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ | |
| __STM32F10X_STDPERIPH_VERSION_SUB2) | |
/** | |
* @} | |
*/ | |
/** @addtogroup Configuration_section_for_CMSIS | |
* @{ | |
*/ | |
/** | |
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals | |
*/ | |
#define __MPU_PRESENT 0 /*!< STM32 does not provide a MPU present or not */ | |
#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ | |
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ | |
/*!< Interrupt Number Definition */ | |
typedef enum IRQn | |
{ | |
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ | |
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ | |
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ | |
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ | |
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ | |
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ | |
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ | |
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ | |
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ | |
/****** STM32 specific Interrupt Numbers *********************************************************/ | |
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ | |
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ | |
TAMPER_IRQn = 2, /*!< Tamper Interrupt */ | |
RTC_IRQn = 3, /*!< RTC global Interrupt */ | |
FLASH_IRQn = 4, /*!< FLASH global Interrupt */ | |
RCC_IRQn = 5, /*!< RCC global Interrupt */ | |
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ | |
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ | |
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ | |
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ | |
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ | |
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ | |
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ | |
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ | |
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ | |
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ | |
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ | |
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ | |
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ | |
#ifdef STM32F10X_LD | |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ | |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ | |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ | |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ | |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ | |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ | |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ | |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ | |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ | |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ | |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ | |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ | |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ | |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ | |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ | |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ | |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ | |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ | |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ | |
#endif /* STM32F10X_LD */ | |
#ifdef STM32F10X_MD | |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ | |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ | |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ | |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ | |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ | |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ | |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ | |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ | |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ | |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ | |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ | |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ | |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ | |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ | |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ | |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ | |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ | |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ | |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ | |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ | |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ | |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ | |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ | |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ | |
#endif /* STM32F10X_MD */ | |
#ifdef STM32F10X_HD | |
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ | |
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ | |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ | |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ | |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ | |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ | |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ | |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ | |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ | |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ | |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ | |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ | |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ | |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ | |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ | |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ | |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ | |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ | |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ | |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ | |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ | |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ | |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ | |
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ | |
TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ | |
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ | |
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ | |
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ | |
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ | |
FSMC_IRQn = 48, /*!< FSMC global Interrupt */ | |
SDIO_IRQn = 49, /*!< SDIO global Interrupt */ | |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ | |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ | |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ | |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ | |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ | |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ | |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ | |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ | |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ | |
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ | |
#endif /* STM32F10X_HD */ | |
#ifdef STM32F10X_CL | |
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ | |
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ | |
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ | |
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ | |
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ | |
TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ | |
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ | |
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ | |
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ | |
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ | |
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ | |
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ | |
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ | |
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ | |
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ | |
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ | |
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ | |
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ | |
USART1_IRQn = 37, /*!< USART1 global Interrupt */ | |
USART2_IRQn = 38, /*!< USART2 global Interrupt */ | |
USART3_IRQn = 39, /*!< USART3 global Interrupt */ | |
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ | |
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ | |
OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ | |
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ | |
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ | |
UART4_IRQn = 52, /*!< UART4 global Interrupt */ | |
UART5_IRQn = 53, /*!< UART5 global Interrupt */ | |
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ | |
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ | |
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ | |
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ | |
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ | |
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ | |
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ | |
ETH_IRQn = 61, /*!< Ethernet global Interrupt */ | |
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ | |
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ | |
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ | |
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ | |
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ | |
OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ | |
#endif /* STM32F10X_CL */ | |
} IRQn_Type; | |
/** | |
* @} | |
*/ | |
#include "core_cm3.h" | |
#include "system_stm32f10x.h" | |
#include <stdint.h> | |
/** @addtogroup Exported_types | |
* @{ | |
*/ | |
/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy prupose) */ | |
typedef int32_t s32; | |
typedef int16_t s16; | |
typedef int8_t s8; | |
typedef const int32_t sc32; /*!< Read Only */ | |
typedef const int16_t sc16; /*!< Read Only */ | |
typedef const int8_t sc8; /*!< Read Only */ | |
typedef __IO int32_t vs32; | |
typedef __IO int16_t vs16; | |
typedef __IO int8_t vs8; | |
typedef __I int32_t vsc32; /*!< Read Only */ | |
typedef __I int16_t vsc16; /*!< Read Only */ | |
typedef __I int8_t vsc8; /*!< Read Only */ | |
typedef uint32_t u32; | |
typedef uint16_t u16; | |
typedef uint8_t u8; | |
typedef const uint32_t uc32; /*!< Read Only */ | |
typedef const uint16_t uc16; /*!< Read Only */ | |
typedef const uint8_t uc8; /*!< Read Only */ | |
typedef __IO uint32_t vu32; | |
typedef __IO uint16_t vu16; | |
typedef __IO uint8_t vu8; | |
typedef __I uint32_t vuc32; /*!< Read Only */ | |
typedef __I uint16_t vuc16; /*!< Read Only */ | |
typedef __I uint8_t vuc8; /*!< Read Only */ | |
typedef enum {FALSE = 0, TRUE = !FALSE} bool; | |
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; | |
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; | |
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) | |
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; | |
/** | |
* @} | |
*/ | |
/** @addtogroup Peripheral_registers_structures | |
* @{ | |
*/ | |
/** | |
* @brief Analog to Digital Converter | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t SR; | |
__IO uint32_t CR1; | |
__IO uint32_t CR2; | |
__IO uint32_t SMPR1; | |
__IO uint32_t SMPR2; | |
__IO uint32_t JOFR1; | |
__IO uint32_t JOFR2; | |
__IO uint32_t JOFR3; | |
__IO uint32_t JOFR4; | |
__IO uint32_t HTR; | |
__IO uint32_t LTR; | |
__IO uint32_t SQR1; | |
__IO uint32_t SQR2; | |
__IO uint32_t SQR3; | |
__IO uint32_t JSQR; | |
__IO uint32_t JDR1; | |
__IO uint32_t JDR2; | |
__IO uint32_t JDR3; | |
__IO uint32_t JDR4; | |
__IO uint32_t DR; | |
} ADC_TypeDef; | |
/** | |
* @brief Backup Registers | |
*/ | |
typedef struct | |
{ | |
uint32_t RESERVED0; | |
__IO uint16_t DR1; | |
uint16_t RESERVED1; | |
__IO uint16_t DR2; | |
uint16_t RESERVED2; | |
__IO uint16_t DR3; | |
uint16_t RESERVED3; | |
__IO uint16_t DR4; | |
uint16_t RESERVED4; | |
__IO uint16_t DR5; | |
uint16_t RESERVED5; | |
__IO uint16_t DR6; | |
uint16_t RESERVED6; | |
__IO uint16_t DR7; | |
uint16_t RESERVED7; | |
__IO uint16_t DR8; | |
uint16_t RESERVED8; | |
__IO uint16_t DR9; | |
uint16_t RESERVED9; | |
__IO uint16_t DR10; | |
uint16_t RESERVED10; | |
__IO uint16_t RTCCR; | |
uint16_t RESERVED11; | |
__IO uint16_t CR; | |
uint16_t RESERVED12; | |
__IO uint16_t CSR; | |
uint16_t RESERVED13[5]; | |
__IO uint16_t DR11; | |
uint16_t RESERVED14; | |
__IO uint16_t DR12; | |
uint16_t RESERVED15; | |
__IO uint16_t DR13; | |
uint16_t RESERVED16; | |
__IO uint16_t DR14; | |
uint16_t RESERVED17; | |
__IO uint16_t DR15; | |
uint16_t RESERVED18; | |
__IO uint16_t DR16; | |
uint16_t RESERVED19; | |
__IO uint16_t DR17; | |
uint16_t RESERVED20; | |
__IO uint16_t DR18; | |
uint16_t RESERVED21; | |
__IO uint16_t DR19; | |
uint16_t RESERVED22; | |
__IO uint16_t DR20; | |
uint16_t RESERVED23; | |
__IO uint16_t DR21; | |
uint16_t RESERVED24; | |
__IO uint16_t DR22; | |
uint16_t RESERVED25; | |
__IO uint16_t DR23; | |
uint16_t RESERVED26; | |
__IO uint16_t DR24; | |
uint16_t RESERVED27; | |
__IO uint16_t DR25; | |
uint16_t RESERVED28; | |
__IO uint16_t DR26; | |
uint16_t RESERVED29; | |
__IO uint16_t DR27; | |
uint16_t RESERVED30; | |
__IO uint16_t DR28; | |
uint16_t RESERVED31; | |
__IO uint16_t DR29; | |
uint16_t RESERVED32; | |
__IO uint16_t DR30; | |
uint16_t RESERVED33; | |
__IO uint16_t DR31; | |
uint16_t RESERVED34; | |
__IO uint16_t DR32; | |
uint16_t RESERVED35; | |
__IO uint16_t DR33; | |
uint16_t RESERVED36; | |
__IO uint16_t DR34; | |
uint16_t RESERVED37; | |
__IO uint16_t DR35; | |
uint16_t RESERVED38; | |
__IO uint16_t DR36; | |
uint16_t RESERVED39; | |
__IO uint16_t DR37; | |
uint16_t RESERVED40; | |
__IO uint16_t DR38; | |
uint16_t RESERVED41; | |
__IO uint16_t DR39; | |
uint16_t RESERVED42; | |
__IO uint16_t DR40; | |
uint16_t RESERVED43; | |
__IO uint16_t DR41; | |
uint16_t RESERVED44; | |
__IO uint16_t DR42; | |
uint16_t RESERVED45; | |
} BKP_TypeDef; | |
/** | |
* @brief Controller Area Network TxMailBox | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t TIR; | |
__IO uint32_t TDTR; | |
__IO uint32_t TDLR; | |
__IO uint32_t TDHR; | |
} CAN_TxMailBox_TypeDef; | |
/** | |
* @brief Controller Area Network FIFOMailBox | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t RIR; | |
__IO uint32_t RDTR; | |
__IO uint32_t RDLR; | |
__IO uint32_t RDHR; | |
} CAN_FIFOMailBox_TypeDef; | |
/** | |
* @brief Controller Area Network FilterRegister | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t FR1; | |
__IO uint32_t FR2; | |
} CAN_FilterRegister_TypeDef; | |
/** | |
* @brief Controller Area Network | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t MCR; | |
__IO uint32_t MSR; | |
__IO uint32_t TSR; | |
__IO uint32_t RF0R; | |
__IO uint32_t RF1R; | |
__IO uint32_t IER; | |
__IO uint32_t ESR; | |
__IO uint32_t BTR; | |
uint32_t RESERVED0[88]; | |
CAN_TxMailBox_TypeDef sTxMailBox[3]; | |
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; | |
uint32_t RESERVED1[12]; | |
__IO uint32_t FMR; | |
__IO uint32_t FM1R; | |
uint32_t RESERVED2; | |
__IO uint32_t FS1R; | |
uint32_t RESERVED3; | |
__IO uint32_t FFA1R; | |
uint32_t RESERVED4; | |
__IO uint32_t FA1R; | |
uint32_t RESERVED5[8]; | |
#ifndef STM32F10X_CL | |
CAN_FilterRegister_TypeDef sFilterRegister[14]; | |
#else | |
CAN_FilterRegister_TypeDef sFilterRegister[28]; | |
#endif /* STM32F10X_CL */ | |
} CAN_TypeDef; | |
/** | |
* @brief CRC calculation unit | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t DR; | |
__IO uint8_t IDR; | |
uint8_t RESERVED0; | |
uint16_t RESERVED1; | |
__IO uint32_t CR; | |
} CRC_TypeDef; | |
/** | |
* @brief Digital to Analog Converter | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t CR; | |
__IO uint32_t SWTRIGR; | |
__IO uint32_t DHR12R1; | |
__IO uint32_t DHR12L1; | |
__IO uint32_t DHR8R1; | |
__IO uint32_t DHR12R2; | |
__IO uint32_t DHR12L2; | |
__IO uint32_t DHR8R2; | |
__IO uint32_t DHR12RD; | |
__IO uint32_t DHR12LD; | |
__IO uint32_t DHR8RD; | |
__IO uint32_t DOR1; | |
__IO uint32_t DOR2; | |
} DAC_TypeDef; | |
/** | |
* @brief Debug MCU | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t IDCODE; | |
__IO uint32_t CR; | |
}DBGMCU_TypeDef; | |
/** | |
* @brief DMA Controller | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t CCR; | |
__IO uint32_t CNDTR; | |
__IO uint32_t CPAR; | |
__IO uint32_t CMAR; | |
} DMA_Channel_TypeDef; | |
typedef struct | |
{ | |
__IO uint32_t ISR; | |
__IO uint32_t IFCR; | |
} DMA_TypeDef; | |
/** | |
* @brief Ethernet MAC | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t MACCR; | |
__IO uint32_t MACFFR; | |
__IO uint32_t MACHTHR; | |
__IO uint32_t MACHTLR; | |
__IO uint32_t MACMIIAR; | |
__IO uint32_t MACMIIDR; | |
__IO uint32_t MACFCR; | |
__IO uint32_t MACVLANTR; /* 8 */ | |
uint32_t RESERVED0[2]; | |
__IO uint32_t MACRWUFFR; /* 11 */ | |
__IO uint32_t MACPMTCSR; | |
uint32_t RESERVED1[2]; | |
__IO uint32_t MACSR; /* 15 */ | |
__IO uint32_t MACIMR; | |
__IO uint32_t MACA0HR; | |
__IO uint32_t MACA0LR; | |
__IO uint32_t MACA1HR; | |
__IO uint32_t MACA1LR; | |
__IO uint32_t MACA2HR; | |
__IO uint32_t MACA2LR; | |
__IO uint32_t MACA3HR; | |
__IO uint32_t MACA3LR; /* 24 */ | |
uint32_t RESERVED2[40]; | |
__IO uint32_t MMCCR; /* 65 */ | |
__IO uint32_t MMCRIR; | |
__IO uint32_t MMCTIR; | |
__IO uint32_t MMCRIMR; | |
__IO uint32_t MMCTIMR; /* 69 */ | |
uint32_t RESERVED3[14]; | |
__IO uint32_t MMCTGFSCCR; /* 84 */ | |
__IO uint32_t MMCTGFMSCCR; | |
uint32_t RESERVED4[5]; | |
__IO uint32_t MMCTGFCR; | |
uint32_t RESERVED5[10]; | |
__IO uint32_t MMCRFCECR; | |
__IO uint32_t MMCRFAECR; | |
uint32_t RESERVED6[10]; | |
__IO uint32_t MMCRGUFCR; | |
uint32_t RESERVED7[334]; | |
__IO uint32_t PTPTSCR; | |
__IO uint32_t PTPSSIR; | |
__IO uint32_t PTPTSHR; | |
__IO uint32_t PTPTSLR; | |
__IO uint32_t PTPTSHUR; | |
__IO uint32_t PTPTSLUR; | |
__IO uint32_t PTPTSAR; | |
__IO uint32_t PTPTTHR; | |
__IO uint32_t PTPTTLR; | |
uint32_t RESERVED8[567]; | |
__IO uint32_t DMABMR; | |
__IO uint32_t DMATPDR; | |
__IO uint32_t DMARPDR; | |
__IO uint32_t DMARDLAR; | |
__IO uint32_t DMATDLAR; | |
__IO uint32_t DMASR; | |
__IO uint32_t DMAOMR; | |
__IO uint32_t DMAIER; | |
__IO uint32_t DMAMFBOCR; | |
uint32_t RESERVED9[9]; | |
__IO uint32_t DMACHTDR; | |
__IO uint32_t DMACHRDR; | |
__IO uint32_t DMACHTBAR; | |
__IO uint32_t DMACHRBAR; | |
} ETH_TypeDef; | |
/** | |
* @brief External Interrupt/Event Controller | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t IMR; | |
__IO uint32_t EMR; | |
__IO uint32_t RTSR; | |
__IO uint32_t FTSR; | |
__IO uint32_t SWIER; | |
__IO uint32_t PR; | |
} EXTI_TypeDef; | |
/** | |
* @brief FLASH Registers | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t ACR; | |
__IO uint32_t KEYR; | |
__IO uint32_t OPTKEYR; | |
__IO uint32_t SR; | |
__IO uint32_t CR; | |
__IO uint32_t AR; | |
__IO uint32_t RESERVED; | |
__IO uint32_t OBR; | |
__IO uint32_t WRPR; | |
} FLASH_TypeDef; | |
/** | |
* @brief Option Bytes Registers | |
*/ | |
typedef struct | |
{ | |
__IO uint16_t RDP; | |
__IO uint16_t USER; | |
__IO uint16_t Data0; | |
__IO uint16_t Data1; | |
__IO uint16_t WRP0; | |
__IO uint16_t WRP1; | |
__IO uint16_t WRP2; | |
__IO uint16_t WRP3; | |
} OB_TypeDef; | |
/** | |
* @brief Flexible Static Memory Controller | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t BTCR[8]; | |
} FSMC_Bank1_TypeDef; | |
/** | |
* @brief Flexible Static Memory Controller Bank1E | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t BWTR[7]; | |
} FSMC_Bank1E_TypeDef; | |
/** | |
* @brief Flexible Static Memory Controller Bank2 | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t PCR2; | |
__IO uint32_t SR2; | |
__IO uint32_t PMEM2; | |
__IO uint32_t PATT2; | |
uint32_t RESERVED0; | |
__IO uint32_t ECCR2; | |
} FSMC_Bank2_TypeDef; | |
/** | |
* @brief Flexible Static Memory Controller Bank3 | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t PCR3; | |
__IO uint32_t SR3; | |
__IO uint32_t PMEM3; | |
__IO uint32_t PATT3; | |
uint32_t RESERVED0; | |
__IO uint32_t ECCR3; | |
} FSMC_Bank3_TypeDef; | |
/** | |
* @brief Flexible Static Memory Controller Bank4 | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t PCR4; | |
__IO uint32_t SR4; | |
__IO uint32_t PMEM4; | |
__IO uint32_t PATT4; | |
__IO uint32_t PIO4; | |
} FSMC_Bank4_TypeDef; | |
/** | |
* @brief General Purpose I/O | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t CRL; | |
__IO uint32_t CRH; | |
__IO uint32_t IDR; | |
__IO uint32_t ODR; | |
__IO uint32_t BSRR; | |
__IO uint32_t BRR; | |
__IO uint32_t LCKR; | |
} GPIO_TypeDef; | |
/** | |
* @brief Alternate Function I/O | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t EVCR; | |
__IO uint32_t MAPR; | |
__IO uint32_t EXTICR[4]; | |
} AFIO_TypeDef; | |
/** | |
* @brief Inter-integrated Circuit Interface | |
*/ | |
typedef struct | |
{ | |
__IO uint16_t CR1; | |
uint16_t RESERVED0; | |
__IO uint16_t CR2; | |
uint16_t RESERVED1; | |
__IO uint16_t OAR1; | |
uint16_t RESERVED2; | |
__IO uint16_t OAR2; | |
uint16_t RESERVED3; | |
__IO uint16_t DR; | |
uint16_t RESERVED4; | |
__IO uint16_t SR1; | |
uint16_t RESERVED5; | |
__IO uint16_t SR2; | |
uint16_t RESERVED6; | |
__IO uint16_t CCR; | |
uint16_t RESERVED7; | |
__IO uint16_t TRISE; | |
uint16_t RESERVED8; | |
} I2C_TypeDef; | |
/** | |
* @brief Independent WATCHDOG | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t KR; | |
__IO uint32_t PR; | |
__IO uint32_t RLR; | |
__IO uint32_t SR; | |
} IWDG_TypeDef; | |
/** | |
* @brief Power Control | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t CR; | |
__IO uint32_t CSR; | |
} PWR_TypeDef; | |
/** | |
* @brief Reset and Clock Control | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t CR; | |
__IO uint32_t CFGR; | |
__IO uint32_t CIR; | |
__IO uint32_t APB2RSTR; | |
__IO uint32_t APB1RSTR; | |
__IO uint32_t AHBENR; | |
__IO uint32_t APB2ENR; | |
__IO uint32_t APB1ENR; | |
__IO uint32_t BDCR; | |
__IO uint32_t CSR; | |
#ifdef STM32F10X_CL | |
__IO uint32_t AHBRSTR; | |
__IO uint32_t CFGR2; | |
#endif /* STM32F10X_CL */ | |
} RCC_TypeDef; | |
/** | |
* @brief Real-Time Clock | |
*/ | |
typedef struct | |
{ | |
__IO uint16_t CRH; | |
uint16_t RESERVED0; | |
__IO uint16_t CRL; | |
uint16_t RESERVED1; | |
__IO uint16_t PRLH; | |
uint16_t RESERVED2; | |
__IO uint16_t PRLL; | |
uint16_t RESERVED3; | |
__IO uint16_t DIVH; | |
uint16_t RESERVED4; | |
__IO uint16_t DIVL; | |
uint16_t RESERVED5; | |
__IO uint16_t CNTH; | |
uint16_t RESERVED6; | |
__IO uint16_t CNTL; | |
uint16_t RESERVED7; | |
__IO uint16_t ALRH; | |
uint16_t RESERVED8; | |
__IO uint16_t ALRL; | |
uint16_t RESERVED9; | |
} RTC_TypeDef; | |
/** | |
* @brief SD host Interface | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t POWER; | |
__IO uint32_t CLKCR; | |
__IO uint32_t ARG; | |
__IO uint32_t CMD; | |
__I uint32_t RESPCMD; | |
__I uint32_t RESP1; | |
__I uint32_t RESP2; | |
__I uint32_t RESP3; | |
__I uint32_t RESP4; | |
__IO uint32_t DTIMER; | |
__IO uint32_t DLEN; | |
__IO uint32_t DCTRL; | |
__I uint32_t DCOUNT; | |
__I uint32_t STA; | |
__IO uint32_t ICR; | |
__IO uint32_t MASK; | |
uint32_t RESERVED0[2]; | |
__I uint32_t FIFOCNT; | |
uint32_t RESERVED1[13]; | |
__IO uint32_t FIFO; | |
} SDIO_TypeDef; | |
/** | |
* @brief Serial Peripheral Interface | |
*/ | |
typedef struct | |
{ | |
__IO uint16_t CR1; | |
uint16_t RESERVED0; | |
__IO uint16_t CR2; | |
uint16_t RESERVED1; | |
__IO uint16_t SR; | |
uint16_t RESERVED2; | |
__IO uint16_t DR; | |
uint16_t RESERVED3; | |
__IO uint16_t CRCPR; | |
uint16_t RESERVED4; | |
__IO uint16_t RXCRCR; | |
uint16_t RESERVED5; | |
__IO uint16_t TXCRCR; | |
uint16_t RESERVED6; | |
__IO uint16_t I2SCFGR; | |
uint16_t RESERVED7; | |
__IO uint16_t I2SPR; | |
uint16_t RESERVED8; | |
} SPI_TypeDef; | |
/** | |
* @brief TIM | |
*/ | |
typedef struct | |
{ | |
__IO uint16_t CR1; | |
uint16_t RESERVED0; | |
__IO uint16_t CR2; | |
uint16_t RESERVED1; | |
__IO uint16_t SMCR; | |
uint16_t RESERVED2; | |
__IO uint16_t DIER; | |
uint16_t RESERVED3; | |
__IO uint16_t SR; | |
uint16_t RESERVED4; | |
__IO uint16_t EGR; | |
uint16_t RESERVED5; | |
__IO uint16_t CCMR1; | |
uint16_t RESERVED6; | |
__IO uint16_t CCMR2; | |
uint16_t RESERVED7; | |
__IO uint16_t CCER; | |
uint16_t RESERVED8; | |
__IO uint16_t CNT; | |
uint16_t RESERVED9; | |
__IO uint16_t PSC; | |
uint16_t RESERVED10; | |
__IO uint16_t ARR; | |
uint16_t RESERVED11; | |
__IO uint16_t RCR; | |
uint16_t RESERVED12; | |
__IO uint16_t CCR1; | |
uint16_t RESERVED13; | |
__IO uint16_t CCR2; | |
uint16_t RESERVED14; | |
__IO uint16_t CCR3; | |
uint16_t RESERVED15; | |
__IO uint16_t CCR4; | |
uint16_t RESERVED16; | |
__IO uint16_t BDTR; | |
uint16_t RESERVED17; | |
__IO uint16_t DCR; | |
uint16_t RESERVED18; | |
__IO uint16_t DMAR; | |
uint16_t RESERVED19; | |
} TIM_TypeDef; | |
/** | |
* @brief Universal Synchronous Asynchronous Receiver Transmitter | |
*/ | |
typedef struct | |
{ | |
__IO uint16_t SR; | |
uint16_t RESERVED0; | |
__IO uint16_t DR; | |
uint16_t RESERVED1; | |
__IO uint16_t BRR; | |
uint16_t RESERVED2; | |
__IO uint16_t CR1; | |
uint16_t RESERVED3; | |
__IO uint16_t CR2; | |
uint16_t RESERVED4; | |
__IO uint16_t CR3; | |
uint16_t RESERVED5; | |
__IO uint16_t GTPR; | |
uint16_t RESERVED6; | |
} USART_TypeDef; | |
/** | |
* @brief Window WATCHDOG | |
*/ | |
typedef struct | |
{ | |
__IO uint32_t CR; | |
__IO uint32_t CFR; | |
__IO uint32_t SR; | |
} WWDG_TypeDef; | |
/** | |
* @} | |
*/ | |
/** @addtogroup Peripheral_memory_map | |
* @{ | |
*/ | |
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ | |
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ | |
#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */ | |
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */ | |
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ | |
/*!< Peripheral memory map */ | |
#define APB1PERIPH_BASE PERIPH_BASE | |
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) | |
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) | |
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) | |
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) | |
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) | |
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) | |
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) | |
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) | |
#define RTC_BASE (APB1PERIPH_BASE + 0x2800) | |
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) | |
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) | |
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) | |
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) | |
#define USART2_BASE (APB1PERIPH_BASE + 0x4400) | |
#define USART3_BASE (APB1PERIPH_BASE + 0x4800) | |
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) | |
#define UART5_BASE (APB1PERIPH_BASE + 0x5000) | |
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) | |
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) | |
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) | |
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) | |
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) | |
#define PWR_BASE (APB1PERIPH_BASE + 0x7000) | |
#define DAC_BASE (APB1PERIPH_BASE + 0x7400) | |
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) | |
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) | |
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) | |
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) | |
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) | |
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) | |
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) | |
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) | |
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) | |
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) | |
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) | |
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) | |
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) | |
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) | |
#define USART1_BASE (APB2PERIPH_BASE + 0x3800) | |
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) | |
#define SDIO_BASE (PERIPH_BASE + 0x18000) | |
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) | |
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) | |
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) | |
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) | |
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) | |
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) | |
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) | |
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) | |
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) | |
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) | |
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) | |
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) | |
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) | |
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) | |
#define RCC_BASE (AHBPERIPH_BASE + 0x1000) | |
#define CRC_BASE (AHBPERIPH_BASE + 0x3000) | |
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ | |
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ | |
#define ETH_BASE (AHBPERIPH_BASE + 0x8000) | |
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ | |
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ | |
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ | |
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ | |
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ | |
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ | |
/** | |
* @} | |
*/ | |
/** @addtogroup Peripheral_declaration | |
* @{ | |
*/ | |
#define TIM2 ((TIM_TypeDef *) TIM2_BASE) | |
#define TIM3 ((TIM_TypeDef *) TIM3_BASE) | |
#define TIM4 ((TIM_TypeDef *) TIM4_BASE) | |
#define TIM5 ((TIM_TypeDef *) TIM5_BASE) | |
#define TIM6 ((TIM_TypeDef *) TIM6_BASE) | |
#define TIM7 ((TIM_TypeDef *) TIM7_BASE) | |
#define RTC ((RTC_TypeDef *) RTC_BASE) | |
#define WWDG ((WWDG_TypeDef *) WWDG_BASE) | |
#define IWDG ((IWDG_TypeDef *) IWDG_BASE) | |
#define SPI2 ((SPI_TypeDef *) SPI2_BASE) | |
#define SPI3 ((SPI_TypeDef *) SPI3_BASE) | |
#define USART2 ((USART_TypeDef *) USART2_BASE) | |
#define USART3 ((USART_TypeDef *) USART3_BASE) | |
#define UART4 ((USART_TypeDef *) UART4_BASE) | |
#define UART5 ((USART_TypeDef *) UART5_BASE) | |
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) | |
#define I2C2 ((I2C_TypeDef *) I2C2_BASE) | |
#define CAN1 ((CAN_TypeDef *) CAN1_BASE) | |
#define CAN2 ((CAN_TypeDef *) CAN2_BASE) | |
#define BKP ((BKP_TypeDef *) BKP_BASE) | |
#define PWR ((PWR_TypeDef *) PWR_BASE) | |
#define DAC ((DAC_TypeDef *) DAC_BASE) | |
#define AFIO ((AFIO_TypeDef *) AFIO_BASE) | |
#define EXTI ((EXTI_TypeDef *) EXTI_BASE) | |
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) | |
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) | |
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) | |
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) | |
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) | |
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) | |
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) | |
#define ADC1 ((ADC_TypeDef *) ADC1_BASE) | |
#define ADC2 ((ADC_TypeDef *) ADC2_BASE) | |
#define TIM1 ((TIM_TypeDef *) TIM1_BASE) | |
#define SPI1 ((SPI_TypeDef *) SPI1_BASE) | |
#define TIM8 ((TIM_TypeDef *) TIM8_BASE) | |
#define USART1 ((USART_TypeDef *) USART1_BASE) | |
#define ADC3 ((ADC_TypeDef *) ADC3_BASE) | |
#define SDIO ((SDIO_TypeDef *) SDIO_BASE) | |
#define DMA1 ((DMA_TypeDef *) DMA1_BASE) | |
#define DMA2 ((DMA_TypeDef *) DMA2_BASE) | |
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) | |
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) | |
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) | |
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) | |
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) | |
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) | |
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) | |
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) | |
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) | |
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) | |
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) | |
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) | |
#define RCC ((RCC_TypeDef *) RCC_BASE) | |
#define CRC ((CRC_TypeDef *) CRC_BASE) | |
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) | |
#define OB ((OB_TypeDef *) OB_BASE) | |
#define ETH ((ETH_TypeDef *) ETH_BASE) | |
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) | |
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) | |
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) | |
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) | |
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) | |
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) | |
/** | |
* @} | |
*/ | |
/** @addtogroup Exported_constants | |
* @{ | |
*/ | |
/** @addtogroup Peripheral_Registers_Bits_Definition | |
* @{ | |
*/ | |
/******************************************************************************/ | |
/* Peripheral Registers_Bits_Definition */ | |
/******************************************************************************/ | |
/******************************************************************************/ | |
/* */ | |
/* CRC calculation unit */ | |
/* */ | |
/******************************************************************************/ | |
/******************* Bit definition for CRC_DR register *********************/ | |
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ | |
/******************* Bit definition for CRC_IDR register ********************/ | |
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ | |
/******************** Bit definition for CRC_CR register ********************/ | |
#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ | |
/******************************************************************************/ | |
/* */ | |
/* Power Control */ | |
/* */ | |
/******************************************************************************/ | |
/******************** Bit definition for PWR_CR register ********************/ | |
#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ | |
#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ | |
#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ | |
#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ | |
#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ | |
#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ | |
#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ | |
#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ | |
#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ | |
/*!< PVD level configuration */ | |
#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ | |
#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ | |
#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ | |
#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ | |
#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ | |
#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ | |
#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ | |
#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ | |
#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ | |
/******************* Bit definition for PWR_CSR register ********************/ | |
#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ | |
#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ | |
#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ | |
#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ | |
/******************************************************************************/ | |
/* */ | |
/* Backup registers */ | |
/* */ | |
/******************************************************************************/ | |
/******************* Bit definition for BKP_DR1 register ********************/ | |
#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR2 register ********************/ | |
#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR3 register ********************/ | |
#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR4 register ********************/ | |
#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR5 register ********************/ | |
#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR6 register ********************/ | |
#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR7 register ********************/ | |
#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR8 register ********************/ | |
#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR9 register ********************/ | |
#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR10 register *******************/ | |
#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR11 register *******************/ | |
#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR12 register *******************/ | |
#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR13 register *******************/ | |
#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR14 register *******************/ | |
#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR15 register *******************/ | |
#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR16 register *******************/ | |
#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR17 register *******************/ | |
#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/****************** Bit definition for BKP_DR18 register ********************/ | |
#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR19 register *******************/ | |
#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR20 register *******************/ | |
#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR21 register *******************/ | |
#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR22 register *******************/ | |
#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR23 register *******************/ | |
#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR24 register *******************/ | |
#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR25 register *******************/ | |
#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR26 register *******************/ | |
#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR27 register *******************/ | |
#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR28 register *******************/ | |
#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR29 register *******************/ | |
#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR30 register *******************/ | |
#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR31 register *******************/ | |
#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR32 register *******************/ | |
#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR33 register *******************/ | |
#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR34 register *******************/ | |
#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR35 register *******************/ | |
#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR36 register *******************/ | |
#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR37 register *******************/ | |
#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR38 register *******************/ | |
#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR39 register *******************/ | |
#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR40 register *******************/ | |
#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR41 register *******************/ | |
#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/******************* Bit definition for BKP_DR42 register *******************/ | |
#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ | |
/****************** Bit definition for BKP_RTCCR register *******************/ | |
#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ | |
#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ | |
#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ | |
#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ | |
/******************** Bit definition for BKP_CR register ********************/ | |
#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ | |
#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ | |
/******************* Bit definition for BKP_CSR register ********************/ | |
#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ | |
#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ | |
#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ | |
#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ | |
#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ | |
/******************************************************************************/ | |
/* */ | |
/* Reset and Clock Control */ | |
/* */ | |
/******************************************************************************/ | |
/******************** Bit definition for RCC_CR register ********************/ | |
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ | |
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ | |
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ | |
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ | |
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ | |
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ | |
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ | |
#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ | |
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ | |
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ | |
#ifdef STM32F10X_CL | |
#define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ | |
#define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ | |
#define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ | |
#define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ | |
#endif /* STM32F10X_CL */ | |
/******************* Bit definition for RCC_CFGR register *******************/ | |
/*!< SW configuration */ | |
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ | |
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ | |
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ | |
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ | |
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ | |
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ | |
/*!< SWS configuration */ | |
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ | |
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ | |
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ | |
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ | |
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ | |
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ | |
/*!< HPRE configuration */ | |
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ | |
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ | |
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ | |
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ | |
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ | |
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ | |
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ | |
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ | |
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ | |
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ | |
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ | |
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ | |
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ | |
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ | |
/*!< PPRE1 configuration */ | |
#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ | |
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ | |
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ | |
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ | |
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ | |
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ | |
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ | |
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ | |
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ | |
/*!< PPRE2 configuration */ | |
#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ | |
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ | |
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ | |
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ | |
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ | |
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ | |
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ | |
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ | |
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ | |
/*!< ADCPPRE configuration */ | |
#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ | |
#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ | |
#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ | |
#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ | |
#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ | |
#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ | |
#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ | |
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ | |
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ | |
/*!< PLLMUL configuration */ | |
#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ | |
#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ | |
#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ | |
#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ | |
#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ | |
#ifdef STM32F10X_CL | |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ | |
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ | |
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ | |
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ | |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ | |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ | |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ | |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ | |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ | |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ | |
#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ | |
#define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTF FS prescaler */ | |
/*!< MCO configuration */ | |
#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ | |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ | |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ | |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ | |
#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ | |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ | |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ | |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ | |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ | |
#define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ | |
#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ | |
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ | |
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source (for Ethernet) */ | |
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source (for Ethernet) */ | |
#else | |
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ | |
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ | |
#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ | |
#define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ | |
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ | |
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ | |
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ | |
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ | |
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ | |
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ | |
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ | |
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ | |
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ | |
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ | |
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ | |
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ | |
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ | |
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ | |
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ | |
#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ | |
/*!< MCO configuration */ | |
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ | |
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ | |
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ | |
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ | |
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ | |
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ | |
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ | |
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ | |
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ | |
#endif /* STM32F10X_CL */ | |
/*!<****************** Bit definition for RCC_CIR register ********************/ | |
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ | |
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ | |
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ | |
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ | |
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ | |
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ | |
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ | |
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ | |
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ | |
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ | |
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ | |
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ | |
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ | |
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ | |
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ | |
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ | |
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ | |
#ifdef STM32F10X_CL | |
#define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ | |
#define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ | |
#define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ | |
#define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ | |
#define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ | |
#define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ | |
#endif /* STM32F10X_CL */ | |
/***************** Bit definition for RCC_APB2RSTR register *****************/ | |
#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */ | |
#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */ | |
#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */ | |
#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */ | |
#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */ | |
#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */ | |
#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */ | |
#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */ | |
#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */ | |
#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */ | |
#ifndef STM32F10X_LD | |
#define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */ | |
#endif /* STM32F10X_HD */ | |
#ifdef STM32F10X_HD | |
#define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */ | |
#define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */ | |
#define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */ | |
#define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */ | |
#endif /* STM32F10X_HD */ | |
/***************** Bit definition for RCC_APB1RSTR register *****************/ | |
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ | |
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ | |
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ | |
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ | |
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ | |
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ | |
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ | |
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ | |
#ifndef STM32F10X_LD | |
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ | |
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ | |
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ | |
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ | |
#endif /* STM32F10X_HD */ | |
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) | |
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ | |
#endif | |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) | |
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ | |
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ | |
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ | |
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ | |
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ | |
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ | |
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ | |
#endif | |
#ifdef STM32F10X_CL | |
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */ | |
#endif /* STM32F10X_CL */ | |
/****************** Bit definition for RCC_AHBENR register ******************/ | |
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ | |
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ | |
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ | |
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ | |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) | |
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ | |
#endif | |
#ifdef STM32F10X_HD | |
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ | |
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ | |
#endif /* STM32F10X_HD */ | |
#ifdef STM32F10X_CL | |
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ | |
#define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ | |
#define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ | |
#define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ | |
#endif /* STM32F10X_CL */ | |
/****************** Bit definition for RCC_APB2ENR register *****************/ | |
#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */ | |
#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */ | |
#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */ | |
#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */ | |
#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */ | |
#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */ | |
#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */ | |
#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */ | |
#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */ | |
#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */ | |
#ifndef STM32F10X_LD | |
#define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */ | |
#endif /* STM32F10X_HD */ | |
#ifdef STM32F10X_HD | |
#define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */ | |
#define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */ | |
#define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */ | |
#define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */ | |
#endif /* STM32F10X_HD */ | |
/***************** Bit definition for RCC_APB1ENR register ******************/ | |
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ | |
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ | |
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ | |
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ | |
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ | |
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ | |
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ | |
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ | |
#ifndef STM32F10X_LD | |
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ | |
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ | |
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ | |
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ | |
#endif /* STM32F10X_HD */ | |
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) | |
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ | |
#endif | |
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) | |
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ | |
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ | |
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ | |
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ | |
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ | |
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ | |
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ | |
#endif | |
#ifdef STM32F10X_CL | |
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */ | |
#endif /* STM32F10X_CL */ | |
/******************* Bit definition for RCC_BDCR register *******************/ | |
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ | |
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ | |
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ | |
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ | |
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ | |
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ | |
/*!< RTC congiguration */ | |
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ | |
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ | |
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ | |
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ | |
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ | |
#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ | |
/******************* Bit definition for RCC_CSR register ********************/ | |
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ | |
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ | |
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ | |
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ | |
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ | |
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ | |
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ | |
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ | |
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ | |
#ifdef STM32F10X_CL | |
/******************* Bit definition for RCC_AHBRSTR register ****************/ | |
#define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ | |
#define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ | |
/******************* Bit definition for RCC_CFGR2 register ******************/ | |
/*!< PREDIV1 configuration */ | |
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ | |
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ | |
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ | |
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ | |
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ | |
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ | |
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ | |
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ | |
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ | |
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ | |
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ | |
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ | |
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ | |
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ | |
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ | |
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ | |
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ | |
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ | |
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ | |
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ | |
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ | |
/*!< PREDIV2 configuration */ | |
#define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ | |
#define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ | |
#define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ | |
#define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ | |
#define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ | |
#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ | |
#define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ | |
#define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ | |
#define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ | |
#define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ | |
#define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ | |
#define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ | |
#define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ | |
#define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ | |
#define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ | |
#define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ | |
#define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ | |
#define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ | |
#define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ | |
#define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ | |
#define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ | |
/*!< PLL2MUL configuration */ | |
#define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ | |
#define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ | |
#define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ | |
#define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ | |
#define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ | |
#define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ | |
#define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ | |
#define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ | |
#define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ | |
#define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ | |
#define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ | |
#define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ | |
#define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ | |
#define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ | |
/*!< PLL3MUL configuration */ | |
#define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ | |
#define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ | |
#define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ | |
#define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ | |
#define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ | |
#define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ | |
#define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ | |
#define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ | |
#define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ | |
#define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ | |
#define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ | |
#define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ | |
#define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ | |
#define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ | |
#define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ | |
#define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ | |
#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ | |
#define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ | |
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ | |
#endif /* STM32F10X_CL */ | |
/******************************************************************************/ | |
/* */ | |
/* General Purpose and Alternate Function I/O */ | |
/* */ | |
/******************************************************************************/ | |
/******************* Bit definition for GPIO_CRL register *******************/ | |
#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ | |
#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ | |
#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ | |
#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ | |
#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ | |
#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ | |
#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ | |
#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ | |
#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ | |
#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ | |
#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ | |
#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ | |
#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ | |
#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ | |
#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ | |
#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ | |
#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ | |
#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ | |
#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ | |
#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ | |
#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ | |
#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ | |
#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ | |
#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ | |
#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ | |
#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ | |
#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ | |
#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ | |
#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ | |
#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ | |
#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ | |
#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ | |
#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ | |
#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ | |
#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ | |
#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ | |
#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ | |
#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ | |
#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ | |
#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ | |
#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ | |
#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ | |
#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ | |
#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ | |
#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ | |
#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ | |
#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ | |
#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ | |
#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ | |
#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ | |
/******************* Bit definition for GPIO_CRH register *******************/ | |
#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ | |
#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ | |
#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ | |
#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ | |
#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ | |
#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ | |
#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ | |
#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ | |
#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ | |
#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ | |
#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ | |
#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ | |
#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ | |
#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ | |
#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ | |
#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ | |
#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ | |
#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ | |
#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ | |
#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ | |
#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ | |
#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ | |
#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ | |
#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ | |
#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ | |
#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ | |
#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ | |
#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ | |
#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ | |
#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ | |
#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ | |
#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ | |
#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ | |
#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ | |
#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ | |
#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ | |
#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ | |
#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ | |
#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ | |
#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ | |
#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ | |
#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ | |
#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ | |
#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ | |
#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ | |
#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ | |
#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ | |
#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ | |
#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ | |
#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ | |
/*!<****************** Bit definition for GPIO_IDR register *******************/ | |
#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ | |
#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ | |
#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ | |
#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ | |
#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ | |
#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ | |
#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ | |
#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ | |
#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ | |
#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ | |
#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ | |
#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ | |
#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ | |
#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ | |
#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ | |
#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ | |
/******************* Bit definition for GPIO_ODR register *******************/ | |
#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ | |
#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ | |
#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ | |
#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ | |
#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ | |
#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ | |
#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ | |
#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ | |
#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ | |
#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ | |
#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ | |
#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ | |
#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ | |
#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ | |
#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ | |
#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ | |
/****************** Bit definition for GPIO_BSRR register *******************/ | |
#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ | |
#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ | |
#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ | |
#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ | |
#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ | |
#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ | |
#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ | |
#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ | |
#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ | |
#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ | |
#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ | |
#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ | |
#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ | |
#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ | |
#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ | |
#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ | |
#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ | |
#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ | |
#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ | |
#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ | |
#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ | |
#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ | |
#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ | |
#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ | |
#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ | |
#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ | |
#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ | |
#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ | |
#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ | |
#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ | |
#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ | |
#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ | |
/******************* Bit definition for GPIO_BRR register *******************/ | |
#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ | |
#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ | |
#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ | |
#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ | |
#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ | |
#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ | |
#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ | |
#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ | |
#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ | |
#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ | |
#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ | |
#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ | |
#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ | |
#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ | |
#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ | |
#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ | |
/****************** Bit definition for GPIO_LCKR register *******************/ | |
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ | |
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ | |
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ | |
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ | |
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ | |
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ | |
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ | |
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ | |
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ | |
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ | |
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ | |
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ | |
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ | |
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ | |
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ | |
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ | |
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ | |
/*----------------------------------------------------------------------------*/ | |
/****************** Bit definition for AFIO_EVCR register *******************/ | |
#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ | |
#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ | |
#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ | |
#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ | |
#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ | |
/*!< PIN configuration */ | |
#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ | |
#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ | |
#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ | |
#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ | |
#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ | |
#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ | |
#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ | |
#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ | |
#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ | |
#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ | |
#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ | |
#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ | |
#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ | |
#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ | |
#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ | |
#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ | |
#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ | |
#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ | |
#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ | |
#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ | |
/*!< PORT configuration */ | |
#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ | |
#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ | |
#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ | |
#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ | |
#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ | |
#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ | |
/****************** Bit definition for AFIO_MAPR register *******************/ | |
#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ | |
#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ | |
#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ | |
#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ | |
#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ | |
#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ | |
#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ | |
/* USART3_REMAP configuration */ | |
#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ | |
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ | |
#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ | |
#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ | |
#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ | |
#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ | |
/*!< TIM1_REMAP configuration */ | |
#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ | |
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ | |
#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ | |
#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ | |
#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ | |
#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ | |
/*!< TIM2_REMAP configuration */ | |
#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ | |
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ | |
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ | |
#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ | |
#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ | |
#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ | |
#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ | |
/*!< TIM3_REMAP configuration */ | |
#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ | |
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ | |
#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ | |
#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ | |
#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ | |
#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ | |
#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ | |
/*!< CAN_REMAP configuration */ | |
#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ | |
#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ | |
#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ | |
#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ | |
#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ | |
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ | |
#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ | |
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ | |
#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ | |
#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ | |
#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ | |
#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ | |
#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ | |
/*!< SWJ_CFG configuration */ | |
#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ | |
#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ | |
#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ | |
#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ | |
/***************** Bit definition for AFIO_EXTICR1 register *****************/ | |
#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ | |
#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ | |
#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ | |
#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ | |
/*!< EXTI0 configuration */ | |
#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ | |
#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ | |
#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ | |
#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ | |
#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ | |
#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ | |
#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ | |
/*!< EXTI1 configuration */ | |
#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ | |
#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ | |
#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ | |
#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ | |
#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ | |
#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ | |
#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ | |
/*!< EXTI2 configuration */ | |
#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ | |
#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ | |
#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ | |
#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ | |
#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ | |
#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ | |
#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ | |
/*!< EXTI3 configuration */ | |
#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ | |
#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ | |
#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ | |
#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ | |
#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ | |
#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ | |
#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ | |
/***************** Bit definition for AFIO_EXTICR2 register *****************/ | |
#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ | |
#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ | |
#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ | |
#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ | |
/*!< EXTI4 configuration */ | |
#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ | |
#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ | |
#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ | |
#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ | |
#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ | |
#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ | |
#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ | |
/* EXTI5 configuration */ | |
#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ | |
#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ | |
#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ | |
#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ | |
#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ | |
#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ | |
#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ | |
/*!< EXTI6 configuration */ | |
#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ | |
#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ | |
#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ | |
#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ | |
#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ | |
#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ | |
#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ | |
/*!< EXTI7 configuration */ | |
#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ | |
#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ | |
#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ | |
#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ | |
#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ | |
#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ | |
#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ | |
/***************** Bit definition for AFIO_EXTICR3 register *****************/ | |
#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ | |
#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ | |
#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ | |
#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ | |
/*!< EXTI8 configuration */ | |
#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ | |
#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ | |
#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ | |
#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ | |
#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ | |
#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ | |
#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ | |
/*!< EXTI9 configuration */ | |
#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ | |
#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ | |
#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ | |
#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ | |
#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ | |
#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ | |
#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ | |
/*!< EXTI10 configuration */ | |
#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ | |
#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ | |
#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ | |
#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ | |
#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ | |
#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ | |
#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ | |
/*!< EXTI11 configuration */ | |
#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ | |
#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ | |
#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ | |
#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ | |
#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ | |
#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ | |
#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ | |
/***************** Bit definition for AFIO_EXTICR4 register *****************/ | |
#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ | |
#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ | |
#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ | |
#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ | |
/* EXTI12 configuration */ | |
#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ | |
#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ | |
#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ | |
#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ | |
#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ | |
#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ | |
#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ | |
/* EXTI13 configuration */ | |
#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ | |
#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ | |
#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ | |
#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ | |
#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ | |
#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ | |
#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ | |
/*!< EXTI14 configuration */ | |
#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ | |
#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ | |
#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ | |
#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ | |
#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ | |
#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ | |
#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ | |
/*!< EXTI15 configuration */ | |
#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ | |
#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ | |
#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ | |
#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ | |
#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ | |
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ | |
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ | |
/******************************************************************************/ | |
/* */ | |
/* SystemTick */ | |
/* */ | |
/******************************************************************************/ | |
/***************** Bit definition for SysTick_CTRL register *****************/ | |
#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ | |
#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ | |
#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ | |
#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ | |
/***************** Bit definition for SysTick_LOAD register *****************/ | |
#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ | |
/***************** Bit definition for SysTick_VAL register ******************/ | |
#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ | |
/***************** Bit definition for SysTick_CALIB register ****************/ | |
#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ | |
#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ | |
#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ | |
/******************************************************************************/ | |
/* */ | |
/* Nested Vectored Interrupt Controller */ | |
/* */ | |
/******************************************************************************/ | |
/****************** Bit definition for NVIC_ISER register *******************/ | |
#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ | |
#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ | |
#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ | |
#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ | |
#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ | |
#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ | |
#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ | |
#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ | |
#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ | |
#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ | |
#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ | |
#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ | |
#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ | |
#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ | |
#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ | |
#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ | |
#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ | |
#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ | |
#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ | |
#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ | |
#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ | |
#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ | |
#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ | |
#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ | |
#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ | |
#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ | |
#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ | |
#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ | |
#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ | |
#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ | |
#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ | |
#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ | |
#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ | |
/****************** Bit definition for NVIC_ICER register *******************/ | |
#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ | |
#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ | |
#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ | |
#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ | |
#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ | |
#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ | |
#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ | |
#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ | |
#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ | |
#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ | |
#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ | |
#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ | |
#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ | |
#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ | |
#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ | |
#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ | |
#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ | |
#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ | |
#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ | |
#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ | |
#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ | |
#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ | |
#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ | |
#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ | |
#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ | |
#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ | |
#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ | |
#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ | |
#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ | |
#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ | |
#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ | |
#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ | |
#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ | |
/****************** Bit definition for NVIC_ISPR register *******************/ | |
#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ | |
#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ | |
#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ | |
#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ | |
#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ | |
#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ | |
#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ | |
#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ | |
#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ | |
#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ | |
#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ | |
#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ | |
#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ | |
#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ | |
#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ | |
#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ | |
#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ | |
#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ | |
#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ | |
#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ | |
#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ | |
#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ | |
#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ | |
#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ | |
#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ | |
#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ | |
#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ | |
#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ | |
#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ | |
#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ | |
#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ | |
#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ | |
#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ | |
/****************** Bit definition for NVIC_ICPR register *******************/ | |
#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ | |
#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ | |
#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ | |
#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ | |
#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ | |
#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ | |
#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ | |
#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ | |
#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ | |
#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ | |
#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ | |
#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ | |
#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ | |
#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ | |
#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ | |
#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ | |
#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ | |
#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ | |
#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ | |
#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ | |
#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ | |
#define NVIC_ICPR_CLRPEND_20 ((uint32_t |