Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15  |  IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20  |  IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC = AE24  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC = AD24  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC = AD25  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC = G16  |  IOSTANDARD=LVCMOS25  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC = AD26  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC = G15  |  IOSTANDARD=LVCMOS25  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC = L18  |  IOSTANDARD=LVCMOS25  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC = H18  |  IOSTANDARD=LVCMOS25  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=E8  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=AF23  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=AG12  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=AG23  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=AF13  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> LOC = AJ6  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> LOC = AJ7  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> LOC = V8  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> LOC = AK7  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> LOC = U8  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> LOC=U25  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> LOC=AG27  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> LOC=AF25  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> LOC=AF26  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> LOC=AE27  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> LOC=AE26  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> LOC=AC25  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> LOC=AC24  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
Net fpga_0_IIC_EEPROM_Sda_pin LOC=F8  |  SLEW = SLOW  |  DRIVE = 6  |  IOSTANDARD=LVCMOS33;
Net fpga_0_IIC_EEPROM_Scl_pin LOC=F9  |  SLEW = SLOW  |  DRIVE = 6  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<30> LOC=K12  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<29> LOC=K13  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<28> LOC=H23  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<27> LOC=G23  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<26> LOC=H12  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<25> LOC=J12  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<24> LOC=K22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<23> LOC=K23  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<22> LOC=K14  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<21> LOC=L14  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<20> LOC=H22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<19> LOC=G22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<18> LOC=J15  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<17> LOC=K16  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<16> LOC=K21  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<15> LOC=J22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<14> LOC=L16  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<13> LOC=L15  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<12> LOC=L20  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<11> LOC=L21  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<10> LOC=AE23  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<9> LOC=AE22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<8> LOC=AE12  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<7> LOC=AE13  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_CEN_pin LOC=J10  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_OEN_pin LOC=B12  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_WEN_pin LOC=AF20  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=J11  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=K11  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=D10  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=D11  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=H8  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=AG22  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=AH22  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=AH12  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=AG13  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=AH20  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=AH19  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=AH14  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=AH13  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=AF15  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=AE16  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=AE21  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=AD20  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=AF16  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=AE17  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=AE19  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=AD19  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=J9  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=K8  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=K9  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=B13  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=C13  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=G11  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=G12  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=M8  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=L8  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=F11  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=E11  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=M10  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=L9  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=E12  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=E13  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=N10  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_ZBT_CLK_OUT_pin LOC=G8  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_ZBT_CLK_FB_pin LOC=AG21  |  IOSTANDARD=LVCMOS33;
Net fpga_0_PCIe_Bridge_RXN_pin LOC=AF1  |  IOSTANDARD = LVDS_25;
Net fpga_0_PCIe_Bridge_RXP_pin LOC=AE1  |  IOSTANDARD = LVDS_25;
Net fpga_0_PCIe_Bridge_TXN_pin LOC=AE2  |  IOSTANDARD = LVDS_25;
Net fpga_0_PCIe_Bridge_TXP_pin LOC=AD2  |  IOSTANDARD = LVDS_25;
Net "pcie_bridge/*SPLB_Clk" TNM_NET = "SPLB_Clk";
Net "pcie_bridge/*Bridge_Clk" TNM_NET = "Bridge_Clk";

## Timing constraints between clock-domain boundaries
#
TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly;
TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 8 ns datapathonly;

Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=K17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=H17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=E34  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=E32  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=A33  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=B33  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=C33  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=C32  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=B32  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=E33  |  IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J14  |  IOSTANDARD = LVCMOS25  |  TIG;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=AJ10  |  IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AH10  |  IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AH9  |  IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=AE11  |  IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=AF11  |  IOSTANDARD = LVDCI_33;
Net fpga_0_Ethernet_MAC_MDINT_pin LOC=H20  |  IOSTANDARD = LVCMOS25  |  TIG;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<0> LOC=AF30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<1> LOC=AK31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<2> LOC=AF31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<3> LOC=AD30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<4> LOC=AJ30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<5> LOC=AF29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<6> LOC=AD29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<7> LOC=AE29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<8> LOC=AH27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<9> LOC=AF28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<10> LOC=AH28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<11> LOC=AA28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<12> LOC=AG25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13> LOC=AJ26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<14> LOC=AG28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<15> LOC=AB28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<16> LOC=AC28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<17> LOC=AB25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<18> LOC=AC27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<19> LOC=AA26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<20> LOC=AB26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<21> LOC=AA24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<22> LOC=AB27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<23> LOC=AA25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<24> LOC=AC29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<25> LOC=AB30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<26> LOC=W31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<27> LOC=V30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<28> LOC=AC30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<29> LOC=W29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<30> LOC=V27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<31> LOC=W27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<32> LOC=V29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<33> LOC=Y27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<34> LOC=Y26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<35> LOC=W24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<36> LOC=V28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<37> LOC=W25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<38> LOC=W26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<39> LOC=V24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<40> LOC=R24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<41> LOC=P25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<42> LOC=N24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<43> LOC=P26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<44> LOC=T24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<45> LOC=N25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<46> LOC=P27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<47> LOC=N28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<48> LOC=M28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<49> LOC=L28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<50> LOC=F25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<51> LOC=H25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<52> LOC=K27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<53> LOC=K28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<54> LOC=H24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<55> LOC=G26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<56> LOC=G25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<57> LOC=M26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<58> LOC=J24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<59> LOC=L26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<60> LOC=J27  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<61> LOC=M25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<62> LOC=L25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<63> LOC=L24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<0> LOC=AA29  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<1> LOC=AK28  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<2> LOC=AK26  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<3> LOC=AB31  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<4> LOC=Y28  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<5> LOC=E26  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<6> LOC=H28  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<7> LOC=G27  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<0> LOC=AA30  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<1> LOC=AK27  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<2> LOC=AJ27  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<3> LOC=AA31  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<4> LOC=Y29  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<5> LOC=E27  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<6> LOC=G28  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<7> LOC=H27  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<0> LOC=L30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<1> LOC=M30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<2> LOC=N29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<3> LOC=P29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<4> LOC=K31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<5> LOC=L31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<6> LOC=P31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<7> LOC=P30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<8> LOC=M31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<9> LOC=R28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<10> LOC=J31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<11> LOC=R29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<12> LOC=T31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<0> LOC=G31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<1> LOC=J30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin LOC=H30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin LOC=E31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_WE_N_pin LOC=K29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CS_N_pin LOC=L29  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<0> LOC=F31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<1> LOC=F30  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CKE_pin LOC=T28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AJ31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=AE28  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=Y24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=Y31  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=V25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=P24  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=F26  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=J25  |  IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<0> LOC=AK29  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<1> LOC=E28  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<0> LOC=AJ29  |  IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<1> LOC=F28  |  IOSTANDARD = DIFF_SSTL18_II;
############################################################################
#
#  PPC440MC_DDR2 BRAM Location Constraints
#
############################################################################

##------------------------------------------------------------------------------
## MIG 2.0 Constraints
##------------------------------------------------------------------------------
###########################################################################
## Define multicycle paths - these paths may take longer because additional
## time allowed for logic to settle in calibration/initialization FSM
###########################################################################

NET "DDR2_SDRAM*/mc_mibclk" TNM = FFS "TNM_CLK0";
NET "DDR2_SDRAM*/mi_mcclk90" TNM = FFS "TNM_CLK90";

NET "DDR2_SDRAM*/mc_mibclk" TNM_NET =  "mc_clk";
TIMESPEC "TS_MC_CLK" = PERIOD "mc_clk" 5.000 ns;


## MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO "TNM_CLK0"
"TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i" * 4;

## Calibration/Initialization complete status flag (for PHY logic only)
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO
 "TNM_CLK0"
"TS_MC_CLK" * 4;

TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO
  "TNM_CLK90" "TS_MC_CLK" * 4;

## Select (address) bits for SRL32 shift registers used in stage3/stage4
## calibration
INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO "TNM_CLK0"
"TS_MC_CLK" * 4;

INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO "TNM_CLK0"
"TS_MC_CLK" * 4;

INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
  TNM = "TNM_CAL_RDEN_DLY";
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO "TNM_CLK0"
"TS_MC_CLK" * 4;

## MUX select for read data - optional delay on data to account for byte skews
INST "*/usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO "TNM_CLK0"
"TS_MC_CLK" * 4;

###########################################################################
## LOC placment of DQS-squelch related IDDR and IDELAY elements
## Each circuit can be located at any of the following locations:
## 1. Ununsed "N"-side of DQS diff pair I/O
## 2. DM data mask (output only, input side is free for use)
## 3. Any output-only site
###########################################################################

INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96";
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96";
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58";
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58";
INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";
INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";
INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100";
INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100";
INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102";
INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102";
INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256";
INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256";
INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";

###########################################################################
## DQS Squelch-related timing constraints
###########################################################################

###########################################################################
## Half-cycle path constraint from IDDR to CE pin for all DQ IDDRs
## for DQS Read Postamble Glitch Squelch circuit
###########################################################################
## Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
## where slack account for rise-time of DQS on board. For now assume slack =
## 0.400ns (based on initial SPICE simulations, assumes use of ODT), so
## time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;

###########################################################################
## LOC and timing constraints for flop driving DQS CE enable signal
## from fabric logic. Even though the absolute delay on this path is
## calibrated out (when synchronizing this output to DQS), the delay
## should still be kept as low as possible to reduce post-calibration
## voltage/temp variations - these are roughly proportional to the
## absolute delay of the path
###########################################################################

INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48;
INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29;
INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31;
INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50;
INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51;
INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128;
INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130;
INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131;

###########################################################################
## Control for DQS gate - from fabric flop. Prevent runaway delay -
## two parts to this path: (1) from fabric flop to IDELAY, (2) from
## IDELAY to asynchronous reset of IDDR that drives the DQ CEs
## A single number is used for all speed grades - value based on 333MHz.
## This can be relaxed for lower frequencies.
###########################################################################

NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;

###########################################################################

INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42;
INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43;
INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45;
INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46;
INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y41;
INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42;
INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44;
INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44;
INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28;
INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32;
INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33;
INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34;
INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26;
INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28;
INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33;
INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34;
INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35;
INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36;
INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38;
INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39;
INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36;
INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37;
INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38;
INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39;
INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46;
INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49;
INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y53;
INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y55;
INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49;
INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52;
INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54;
INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56;
INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52;
INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56;
INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58;
INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59;
INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54;
INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y57;
INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58;
INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59;
INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122;
INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132;
INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125;
INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137;
INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135;
INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139;


INST "DDR2_SDRAM/*/*u_rdf" LOC = RAMB36_X0Y19;
INST "DDR2_SDRAM/*/*u_rdf1" LOC = RAMB36_X0Y18;
INST "DDR2_SDRAM/*/*gen_wdf[0]*u_wdf" LOC = RAMB36_X0Y17;
INST "DDR2_SDRAM/*/*gen_wdf[1]*u_wdf" LOC = RAMB36_X0Y16;


###############################################################################

# Prevent unrelated logic from being packed into any slices used

# by read data capture RPM's - if unrelated logic gets packed into

# these slices, it could cause the DIRT strings that define the

# IDDR -> fabric flop routing to become unroutable during PAR stage

# (unrelated logic may require routing resources required by the

# DIRT strings - MAP does not currently take into account DIRT

# strings when placing logic

###############################################################################

AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;

 
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=G5  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=N7  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=N5  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=P5  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=R6  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=M6  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=L6  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH17  |  IOSTANDARD = LVCMOS33  |  PERIOD = 30000 ps;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=M7  |  IOSTANDARD = LVCMOS33  |  TIG;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=M5  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=N8  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=R9  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=P9  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=T8  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=J7  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=H7  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=R7  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=U7  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=P7  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=P6  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=R8  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=L5  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=L4  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=K6  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=J5  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=T6  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=K7  |  IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=J6  |  IOSTANDARD = LVCMOS33;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC = AH15  |  IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = E9  |  IOSTANDARD=LVCMOS33  |  PULLUP;
Net fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin LOC=AF4  |  IOSTANDARD = LVDS_25;
Net fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin LOC=AF3  |  IOSTANDARD = LVDS_25;