| /* | |
| FreeRTOS V6.0.1 - Copyright (C) 2009 Real Time Engineers Ltd. | |
| *************************************************************************** | |
| * * | |
| * If you are: * | |
| * * | |
| * + New to FreeRTOS, * | |
| * + Wanting to learn FreeRTOS or multitasking in general quickly * | |
| * + Looking for basic training, * | |
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| * * | |
| * then take a look at the FreeRTOS eBook * | |
| * * | |
| * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * | |
| * http://www.FreeRTOS.org/Documentation * | |
| * * | |
| * A pdf reference manual is also available. Both are usually delivered * | |
| * to your inbox within 20 minutes to two hours when purchased between 8am * | |
| * and 8pm GMT (although please allow up to 24 hours in case of * | |
| * exceptional circumstances). Thank you for your support! * | |
| * * | |
| *************************************************************************** | |
| This file is part of the FreeRTOS distribution. | |
| FreeRTOS is free software; you can redistribute it and/or modify it under | |
| the terms of the GNU General Public License (version 2) as published by the | |
| Free Software Foundation AND MODIFIED BY the FreeRTOS exception. | |
| ***NOTE*** The exception to the GPL is included to allow you to distribute | |
| a combined work that includes FreeRTOS without being obliged to provide the | |
| source code for proprietary components outside of the FreeRTOS kernel. | |
| FreeRTOS is distributed in the hope that it will be useful, but WITHOUT | |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| more details. You should have received a copy of the GNU General Public | |
| License and the FreeRTOS license exception along with FreeRTOS; if not it | |
| can be viewed here: http://www.freertos.org/a00114.html and also obtained | |
| by writing to Richard Barry, contact details for whom are available on the | |
| FreeRTOS WEB site. | |
| 1 tab == 4 spaces! | |
| http://www.FreeRTOS.org - Documentation, latest information, license and | |
| contact details. | |
| http://www.SafeRTOS.com - A version that is certified for use in safety | |
| critical systems. | |
| http://www.OpenRTOS.com - Commercial support, development, porting, | |
| licensing and training services. | |
| */ | |
| /*----------------------------------------------------------- | |
| * Components that can be compiled to either ARM or THUMB mode are | |
| * contained in port.c The ISR routines, which can only be compiled | |
| * to ARM mode, are contained in this file. | |
| *----------------------------------------------------------*/ | |
| /* | |
| */ | |
| /* Scheduler includes. */ | |
| #include "FreeRTOS.h" | |
| #include "task.h" | |
| /* Constants required to handle critical sections. */ | |
| #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 ) | |
| volatile unsigned long ulCriticalNesting = 9999UL; | |
| /*-----------------------------------------------------------*/ | |
| /* | |
| * The scheduler can only be started from ARM mode, hence the inclusion of this | |
| * function here. | |
| */ | |
| void vPortISRStartFirstTask( void ); | |
| /*-----------------------------------------------------------*/ | |
| void vPortISRStartFirstTask( void ) | |
| { | |
| /* Simply start the scheduler. This is included here as it can only be | |
| called from ARM mode. */ | |
| asm volatile ( \ | |
| "LDR R0, =pxCurrentTCB \n\t" \ | |
| "LDR R0, [R0] \n\t" \ | |
| "LDR LR, [R0] \n\t" \ | |
| \ | |
| /* The critical nesting depth is the first item on the stack. */ \ | |
| /* Load it into the ulCriticalNesting variable. */ \ | |
| "LDR R0, =ulCriticalNesting \n\t" \ | |
| "LDMFD LR!, {R1} \n\t" \ | |
| "STR R1, [R0] \n\t" \ | |
| \ | |
| /* Get the SPSR from the stack. */ \ | |
| "LDMFD LR!, {R0} \n\t" \ | |
| "MSR SPSR, R0 \n\t" \ | |
| \ | |
| /* Restore all system mode registers for the task. */ \ | |
| "LDMFD LR, {R0-R14}^ \n\t" \ | |
| "NOP \n\t" \ | |
| \ | |
| /* Restore the return address. */ \ | |
| "LDR LR, [LR, #+60] \n\t" \ | |
| \ | |
| /* And return - correcting the offset in the LR to obtain the */ \ | |
| /* correct address. */ \ | |
| "SUBS PC, LR, #4 \n\t" \ | |
| ); | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void vPortTickISR( void ) | |
| { | |
| /* Increment the RTOS tick count, then look for the highest priority | |
| task that is ready to run. */ | |
| vTaskIncrementTick(); | |
| #if configUSE_PREEMPTION == 1 | |
| vTaskSwitchContext(); | |
| #endif | |
| /* Ready for the next interrupt. */ | |
| TB_ClearITPendingBit( TB_IT_Update ); | |
| } | |
| /*-----------------------------------------------------------*/ | |
| /* | |
| * The interrupt management utilities can only be called from ARM mode. When | |
| * THUMB_INTERWORK is defined the utilities are defined as functions here to | |
| * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then | |
| * the utilities are defined as macros in portmacro.h - as per other ports. | |
| */ | |
| #ifdef THUMB_INTERWORK | |
| void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); | |
| void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); | |
| void vPortDisableInterruptsFromThumb( void ) | |
| { | |
| asm volatile ( | |
| "STMDB SP!, {R0} \n\t" /* Push R0. */ | |
| "MRS R0, CPSR \n\t" /* Get CPSR. */ | |
| "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ | |
| "MSR CPSR, R0 \n\t" /* Write back modified value. */ | |
| "LDMIA SP!, {R0} \n\t" /* Pop R0. */ | |
| "BX R14" ); /* Return back to thumb. */ | |
| } | |
| void vPortEnableInterruptsFromThumb( void ) | |
| { | |
| asm volatile ( | |
| "STMDB SP!, {R0} \n\t" /* Push R0. */ | |
| "MRS R0, CPSR \n\t" /* Get CPSR. */ | |
| "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ | |
| "MSR CPSR, R0 \n\t" /* Write back modified value. */ | |
| "LDMIA SP!, {R0} \n\t" /* Pop R0. */ | |
| "BX R14" ); /* Return back to thumb. */ | |
| } | |
| #endif /* THUMB_INTERWORK */ | |
| /*-----------------------------------------------------------*/ | |
| void vPortEnterCritical( void ) | |
| { | |
| /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ | |
| asm volatile ( | |
| "STMDB SP!, {R0} \n\t" /* Push R0. */ | |
| "MRS R0, CPSR \n\t" /* Get CPSR. */ | |
| "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ | |
| "MSR CPSR, R0 \n\t" /* Write back modified value. */ | |
| "LDMIA SP!, {R0}" ); /* Pop R0. */ | |
| /* Now interrupts are disabled ulCriticalNesting can be accessed | |
| directly. Increment ulCriticalNesting to keep a count of how many times | |
| portENTER_CRITICAL() has been called. */ | |
| ulCriticalNesting++; | |
| } | |
| /*-----------------------------------------------------------*/ | |
| void vPortExitCritical( void ) | |
| { | |
| if( ulCriticalNesting > portNO_CRITICAL_NESTING ) | |
| { | |
| /* Decrement the nesting count as we are leaving a critical section. */ | |
| ulCriticalNesting--; | |
| /* If the nesting level has reached zero then interrupts should be | |
| re-enabled. */ | |
| if( ulCriticalNesting == portNO_CRITICAL_NESTING ) | |
| { | |
| /* Enable interrupts as per portEXIT_CRITICAL(). */ | |
| asm volatile ( | |
| "STMDB SP!, {R0} \n\t" /* Push R0. */ | |
| "MRS R0, CPSR \n\t" /* Get CPSR. */ | |
| "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ | |
| "MSR CPSR, R0 \n\t" /* Write back modified value. */ | |
| "LDMIA SP!, {R0}" ); /* Pop R0. */ | |
| } | |
| } | |
| } | |