| <EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Mon Aug 29 16:09:40 2011"> |
| |
| <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.xmp" SPEEDGRADE="-3"/> |
| |
| <EXTERNALPORTS> |
| <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/> |
| <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/> |
| <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/> |
| <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/> |
| <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/> |
| <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="DIP_Switches_4Bits_TRI_I" RIGHT="3" SIGNAME="DIP_Switches_4Bits_TRI_I"/> |
| <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="6" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/> |
| <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="7" MSB="0" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="3" SIGNAME="Push_Buttons_4Bits_TRI_I"/> |
| <PORT DIR="O" MHS_INDEX="8" NAME="mcbx_dram_clk" SIGNAME="mcbx_dram_clk"/> |
| <PORT DIR="O" MHS_INDEX="9" NAME="mcbx_dram_clk_n" SIGNAME="mcbx_dram_clk_n"/> |
| <PORT DIR="O" MHS_INDEX="10" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/> |
| <PORT DIR="O" MHS_INDEX="11" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/> |
| <PORT DIR="O" MHS_INDEX="12" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/> |
| <PORT DIR="O" MHS_INDEX="13" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/> |
| <PORT DIR="O" MHS_INDEX="14" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/> |
| <PORT DIR="O" MHS_INDEX="15" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/> |
| <PORT DIR="O" MHS_INDEX="16" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/> |
| <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="17" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba"/> |
| <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="18" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr"/> |
| <PORT DIR="O" MHS_INDEX="19" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/> |
| <PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="20" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/> |
| <PORT DIR="IO" MHS_INDEX="21" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/> |
| <PORT DIR="IO" MHS_INDEX="22" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/> |
| <PORT DIR="IO" MHS_INDEX="23" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/> |
| <PORT DIR="IO" MHS_INDEX="24" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/> |
| <PORT DIR="IO" MHS_INDEX="25" NAME="rzq" SIGNAME="rzq"/> |
| <PORT DIR="IO" MHS_INDEX="26" NAME="zio" SIGNAME="zio"/> |
| <PORT DIR="IO" MHS_INDEX="27" NAME="ETHERNET_MDIO" SIGNAME="ETHERNET_MDIO"/> |
| <PORT DIR="O" MHS_INDEX="28" NAME="ETHERNET_MDC" SIGNAME="ETHERNET_MDC"/> |
| <PORT DIR="O" MHS_INDEX="29" NAME="ETHERNET_TX_ER" SIGNAME="ETHERNET_TX_ER"/> |
| <PORT DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="30" MSB="7" NAME="ETHERNET_TXD" RIGHT="0" SIGNAME="ETHERNET_TXD"/> |
| <PORT DIR="O" MHS_INDEX="31" NAME="ETHERNET_TX_EN" SIGNAME="ETHERNET_TX_EN"/> |
| <PORT DIR="I" MHS_INDEX="32" NAME="ETHERNET_MII_TX_CLK" SIGNAME="ETHERNET_MII_TX_CLK"/> |
| <PORT DIR="O" MHS_INDEX="33" NAME="ETHERNET_TX_CLK" SIGNAME="ETHERNET_TX_CLK"/> |
| <PORT DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="34" MSB="7" NAME="ETHERNET_RXD" RIGHT="0" SIGNAME="ETHERNET_RXD"/> |
| <PORT DIR="I" MHS_INDEX="35" NAME="ETHERNET_RX_ER" SIGNAME="ETHERNET_RX_ER"/> |
| <PORT DIR="I" MHS_INDEX="36" NAME="ETHERNET_RX_CLK" SIGNAME="ETHERNET_RX_CLK"/> |
| <PORT DIR="I" MHS_INDEX="37" NAME="ETHERNET_RX_DV" SIGNAME="ETHERNET_RX_DV"/> |
| <PORT DIR="O" MHS_INDEX="38" NAME="ETHERNET_PHY_RST_N" SIGNAME="ETHERNET_PHY_RST_N"/> |
| </EXTERNALPORTS> |
| |
| <MODULES> |
| <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect"> |
| <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="5"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="3"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff00000000c0000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c7ffffff"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400000003000000020000000100000000"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e100"/> |
| <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100"/> |
| <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111110101"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111101111"/> |
| <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5"/> |
| <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f"/> |
| <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111100000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000400000001000000010000000100000020"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004000000010000000200000002"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004"/> |
| <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/> |
| <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="2" MSB="4" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="5" MSB="4" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi4_0_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="6" MSB="14" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="159" LSB="0" MPD_INDEX="7" MSB="159" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="39" LSB="0" MPD_INDEX="8" MSB="39" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="9" MSB="14" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="10" MSB="9" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="11" MSB="9" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="12" MSB="19" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="13" MSB="14" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="14" MSB="19" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="24" LSB="0" MPD_INDEX="15" MSB="24" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="16" MSB="4" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi4_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="17" MSB="4" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi4_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="159" LSB="0" MPD_INDEX="18" MSB="159" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="19" MSB="19" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="20" MSB="4" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi4_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="21" MSB="4" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="22" MSB="4" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi4_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="23" MSB="4" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi4_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="24" MSB="14" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi4_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="25" MSB="9" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="26" MSB="4" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="27" MSB="4" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi4_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="28" MSB="4" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi4_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="29" MSB="14" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="159" LSB="0" MPD_INDEX="30" MSB="159" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="39" LSB="0" MPD_INDEX="31" MSB="39" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="32" MSB="14" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="33" MSB="9" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="34" MSB="9" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="35" MSB="19" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="36" MSB="14" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="19" LSB="0" MPD_INDEX="37" MSB="19" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="24" LSB="0" MPD_INDEX="38" MSB="24" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="39" MSB="4" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi4_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="40" MSB="4" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi4_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="41" MSB="14" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi4_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="159" LSB="0" MPD_INDEX="42" MSB="159" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="43" MSB="9" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="44" MSB="4" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi4_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="45" MSB="4" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="46" MSB="4" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi4_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="47" MSB="4" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi4_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ACLK" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="axi4_0_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="49" MSB="2" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="59" MSB="4" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="62" MSB="2" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi4_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi4_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi4_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi4_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="69" MSB="2" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi4_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi4_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi4_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="74" MSB="2" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="84" MSB="4" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="87" MSB="2" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi4_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi4_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi4_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi4_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI_CTRL"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| </MODULE> |
| <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect"> |
| <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="9"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000020000000200000002000000020000000200000002000000020000000200000002"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041240000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040040000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000074800000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041e0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041c0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004127ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004004ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007480ffff"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100"/> |
| <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000100000001000000010000000102faf08005f5e10002faf08002faf08002faf08002faf08002faf08002faf08002faf080"/> |
| <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000"/> |
| <PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"/> |
| <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/> |
| <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/> |
| <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/> |
| <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000010000000100000001000000010000000100000001000000010000000100000001"/> |
| <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/> |
| <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/> |
| <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="3" MSB="8" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi4lite_0_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="48" MSB="8" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi4lite_0_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="49" MSB="8" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="287" LSB="0" MPD_INDEX="50" MSB="287" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="71" LSB="0" MPD_INDEX="51" MSB="71" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="26" LSB="0" MPD_INDEX="52" MSB="26" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="53" MSB="17" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="54" MSB="17" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="55" MSB="35" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="26" LSB="0" MPD_INDEX="56" MSB="26" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="57" MSB="35" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="58" MSB="35" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="59" MSB="8" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="60" MSB="8" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="61" MSB="8" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="62" MSB="8" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="287" LSB="0" MPD_INDEX="63" MSB="287" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="64" MSB="35" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="65" MSB="8" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="66" MSB="8" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="67" MSB="8" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="68" MSB="8" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="69" MSB="8" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="70" MSB="17" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="71" MSB="8" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="72" MSB="8" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="73" MSB="8" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="74" MSB="8" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="287" LSB="0" MPD_INDEX="75" MSB="287" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="71" LSB="0" MPD_INDEX="76" MSB="71" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="26" LSB="0" MPD_INDEX="77" MSB="26" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="78" MSB="17" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="79" MSB="17" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="80" MSB="35" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="26" LSB="0" MPD_INDEX="81" MSB="26" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="82" MSB="35" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="83" MSB="35" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="84" MSB="8" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="85" MSB="8" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="86" MSB="8" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="87" MSB="8" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="287" LSB="0" MPD_INDEX="88" MSB="287" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="89" MSB="17" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="90" MSB="8" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="91" MSB="8" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="92" MSB="8" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="93" MSB="8" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI_CTRL"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| </MODULE> |
| <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE"> |
| <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/> |
| <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2"/> |
| <PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/> |
| <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/> |
| <PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0"/> |
| <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00"/> |
| <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/> |
| <PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000"/> |
| <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="17"/> |
| <PARAMETER MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/> |
| <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/> |
| <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/> |
| <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/> |
| <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000"/> |
| <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc7ffffff"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="17"/> |
| <PARAMETER MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/> |
| <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/> |
| <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/> |
| <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/> |
| <PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4"/> |
| <PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2"/> |
| <PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3"/> |
| <PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16"/> |
| <PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_M_AXI_DP_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_DP_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_DP_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_DP_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_DP_B_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_IC_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_IC_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_IC_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_IC_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_IC_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/> |
| <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"/> |
| <PORT BUS="DLMB:ILMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/> |
| <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/> |
| <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/> |
| <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/> |
| <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/> |
| <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="microblaze_0_ilmb_LMB_Ready"/> |
| <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="microblaze_0_ilmb_LMB_Wait"/> |
| <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="microblaze_0_ilmb_LMB_CE"/> |
| <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="microblaze_0_ilmb_LMB_UE"/> |
| <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:31]"/> |
| <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/> |
| <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/> |
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| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="microblaze_0_dlmb_LMB_Ready"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="microblaze_0_dlmb_LMB_Wait"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="microblaze_0_dlmb_LMB_CE"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="microblaze_0_dlmb_LMB_UE"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:31]"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:31]"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/> |
| <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:3]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="86" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="89" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="92" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="95" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="96" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="99" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="100" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="109" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="110" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="111" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="114" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="116" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="118" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="119" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="120" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="121" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="124" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="125" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="126" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="128" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="130" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="131" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="132" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="134" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="135" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="136" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="137" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="139" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="140" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="141" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="142" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="144" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="145" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="147" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="148" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="149" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="150" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="152" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="153" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="154" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="155" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="156" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="158" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RLAST" SIGNAME="axi4lite_0_S_RLAST"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="I" MPD_INDEX="160" NAME="M_AXI_DP_RVALID" SIGNAME="axi4lite_0_S_RVALID"/> |
| <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="O" MPD_INDEX="161" NAME="M_AXI_DP_RREADY" SIGNAME="axi4lite_0_S_RREADY"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="162" NAME="M_AXI_IC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="164" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="165" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="166" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="167" NAME="M_AXI_IC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="168" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="169" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="170" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="171" NAME="M_AXI_IC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="172" NAME="M_AXI_IC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="173" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="175" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="176" NAME="M_AXI_IC_WLAST" SIGNAME="axi4_0_S_WLAST"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="177" NAME="M_AXI_IC_WVALID" SIGNAME="axi4_0_S_WVALID"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="178" NAME="M_AXI_IC_WREADY" SIGNAME="axi4_0_S_WREADY"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="180" NAME="M_AXI_IC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="182" NAME="M_AXI_IC_BVALID" SIGNAME="axi4_0_S_BVALID"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="183" NAME="M_AXI_IC_BREADY" SIGNAME="axi4_0_S_BREADY"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="184" NAME="M_AXI_IC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="185" NAME="M_AXI_IC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="187" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="188" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="189" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="190" NAME="M_AXI_IC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="192" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="194" NAME="M_AXI_IC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="195" NAME="M_AXI_IC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="196" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="197" NAME="M_AXI_IC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="198" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="199" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RLAST" SIGNAME="axi4_0_S_RLAST"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_IC_RVALID" SIGNAME="axi4_0_S_RVALID"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="202" NAME="M_AXI_IC_RREADY" SIGNAME="axi4_0_S_RREADY"/> |
| <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="204" NAME="M_AXI_DC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="205" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="206" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="207" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="208" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="209" NAME="M_AXI_DC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="211" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="212" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="213" NAME="M_AXI_DC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="214" NAME="M_AXI_DC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="215" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="216" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="217" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="218" NAME="M_AXI_DC_WLAST" SIGNAME="axi4_0_S_WLAST"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="219" NAME="M_AXI_DC_WVALID" SIGNAME="axi4_0_S_WVALID"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="220" NAME="M_AXI_DC_WREADY" SIGNAME="axi4_0_S_WREADY"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="222" NAME="M_AXI_DC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="224" NAME="M_AXI_DC_BVALID" SIGNAME="axi4_0_S_BVALID"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="225" NAME="M_AXI_DC_BREADY" SIGNAME="axi4_0_S_BREADY"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="226" NAME="M_AXI_DC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="227" NAME="M_AXI_DC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="229" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="230" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="231" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="232" NAME="M_AXI_DC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="234" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="236" NAME="M_AXI_DC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="237" NAME="M_AXI_DC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="238" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="239" NAME="M_AXI_DC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="241" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RLAST" SIGNAME="axi4_0_S_RLAST"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="243" NAME="M_AXI_DC_RVALID" SIGNAME="axi4_0_S_RVALID"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="244" NAME="M_AXI_DC_RREADY" SIGNAME="axi4_0_S_RREADY"/> |
| <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/> |
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| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="254" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="255" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/> |
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| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="257" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="258" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="259" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="260" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="261" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="262" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="263" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/> |
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| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="Trace_Data_Access" SIGNAME="__NOC__"/> |
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| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="270" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="271" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="272" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="273" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="274" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="275" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/> |
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| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="277" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="278" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="279" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="280" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="281" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/> |
| <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="FSL0_S_READ" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="286" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="287" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="288" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="289" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="290" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="291" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="292" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="293" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="294" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="295" NAME="FSL1_S_READ" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="296" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="297" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="298" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="299" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="300" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="301" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="302" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="303" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="304" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="FSL2_S_READ" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="306" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="307" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="308" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="309" NAME="FSL2_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="310" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="311" MSB="0" NAME="FSL2_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="FSL2_M_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="313" NAME="FSL2_M_FULL" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="FSL3_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="FSL3_S_READ" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="316" MSB="0" NAME="FSL3_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="317" NAME="FSL3_S_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="318" NAME="FSL3_S_EXISTS" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="319" NAME="FSL3_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="320" NAME="FSL3_M_WRITE" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="321" MSB="0" NAME="FSL3_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="FSL3_M_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="323" NAME="FSL3_M_FULL" SIGNAME="__NOC__"/> |
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| <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="325" NAME="FSL4_S_READ" SIGNAME="__NOC__"/> |
| <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="326" MSB="0" NAME="FSL4_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/> |
| <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="327" NAME="FSL4_S_CONTROL" SIGNAME="__NOC__"/> |
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| <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="332" NAME="FSL4_M_CONTROL" SIGNAME="__NOC__"/> |
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| <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="337" NAME="FSL5_S_CONTROL" SIGNAME="__NOC__"/> |
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| <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="585" NAME="DCACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="586" NAME="DCACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/> |
| <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="587" NAME="DCACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="588" NAME="DCACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/> |
| <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="589" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="590" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/> |
| <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="591" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/> |
| <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/> |
| <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/> |
| <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/> |
| <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="CLK"/> |
| <PORTMAP DIR="I" PHYSICAL="RESET"/> |
| <PORTMAP DIR="I" PHYSICAL="DATA_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="DREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="DWAIT"/> |
| <PORTMAP DIR="I" PHYSICAL="DCE"/> |
| <PORTMAP DIR="I" PHYSICAL="DUE"/> |
| <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="D_AS"/> |
| <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/> |
| <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/> |
| <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="CLK"/> |
| <PORTMAP DIR="I" PHYSICAL="RESET"/> |
| <PORTMAP DIR="I" PHYSICAL="INSTR"/> |
| <PORTMAP DIR="I" PHYSICAL="IREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="IWAIT"/> |
| <PORTMAP DIR="I" PHYSICAL="ICE"/> |
| <PORTMAP DIR="I" PHYSICAL="IUE"/> |
| <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="IFETCH"/> |
| <PORTMAP DIR="O" PHYSICAL="I_AS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="4" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/> |
| <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/> |
| <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/> |
| <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/> |
| <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/> |
| <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/> |
| <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/> |
| <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_PC"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/> |
| <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/> |
| <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/> |
| <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/> |
| <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/> |
| <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/> |
| <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/> |
| <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/> |
| <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1074003968" BASENAME="C_BASEADDR" BASEVALUE="0x40040000" HIGHDECIMAL="1074069503" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4004ffff" INSTANCE="DIP_Switches_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1092878336" BASENAME="C_BASEADDR" BASEVALUE="0x41240000" HIGHDECIMAL="1093140479" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4127ffff" INSTANCE="ETHERNET" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="262144" SIZEABRV="256K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1105199104" BASENAME="C_BASEADDR" BASEVALUE="0x41e00000" HIGHDECIMAL="1105264639" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41e0ffff" INSTANCE="ETHERNET_dma" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="microblaze_0_intc" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" INSTANCE="MCB_DDR3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="134217728" SIZEABRV="128M"> |
| <ACCESSROUTE> |
| <ROUTEPNT INDEX="0" INSTANCE="axi4_0"/> |
| </ACCESSROUTE> |
| </MEMRANGE> |
| </MEMORYMAP> |
| <PERIPHERALS> |
| <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/> |
| <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/> |
| <PERIPHERAL INSTANCE="debug_module"/> |
| <PERIPHERAL INSTANCE="RS232_Uart_1"/> |
| <PERIPHERAL INSTANCE="DIP_Switches_4Bits"/> |
| <PERIPHERAL INSTANCE="LEDs_4Bits"/> |
| <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/> |
| <PERIPHERAL INSTANCE="ETHERNET"/> |
| <PERIPHERAL INSTANCE="axi_timer_0"/> |
| <PERIPHERAL INSTANCE="ETHERNET_dma"/> |
| <PERIPHERAL INSTANCE="microblaze_0_intc"/> |
| <PERIPHERAL INSTANCE="MCB_DDR3"/> |
| </PERIPHERALS> |
| <INTERRUPTINFO TYPE="TARGET"> |
| <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/> |
| </INTERRUPTINFO> |
| </MODULE> |
| <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10"> |
| <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/> |
| <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_ilmb_LMB_Rst"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE"/> |
| <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/> |
| </PORTS> |
| <BUSINTERFACES/> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/> |
| </IOINTERFACES> |
| </MODULE> |
| <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10"> |
| <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/> |
| <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_dlmb_LMB_Rst"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE"/> |
| <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/> |
| </PORTS> |
| <BUSINTERFACES/> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/> |
| </IOINTERFACES> |
| </MODULE> |
| <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr"> |
| <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/> |
| <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x00800000"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/> |
| <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_BE"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_UE"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_CE"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="SLMB"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="SPLB_CTRL"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI_CTRL"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| </MODULE> |
| <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr"> |
| <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/> |
| <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x00800000"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE"/> |
| <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/> |
| <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/> |
| <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/> |
| <PORTMAP DIR="I" PHYSICAL="LMB_BE"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_UE"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_CE"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/> |
| <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="SLMB"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="SPLB_CTRL"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI_CTRL"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| </MODULE> |
| <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block"> |
| <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000"/> |
| <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/> |
| <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/> |
| <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/> |
| <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/> |
| <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/> |
| <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/> |
| <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/> |
| <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/> |
| <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/> |
| <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/> |
| <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/> |
| <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/> |
| <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/> |
| <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/> |
| <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/> |
| <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| </MODULE> |
| <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset"> |
| <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t"/> |
| <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"/> |
| <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/> |
| <PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked"/> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]"/> |
| <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/> |
| <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/> |
| <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/> |
| <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/> |
| <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/> |
| <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/> |
| <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/> |
| <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/> |
| <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/> |
| <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/> |
| <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/> |
| <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/> |
| </IOINTERFACES> |
| </MODULE> |
| <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator"> |
| <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="600000000"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="600000000"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0"/> |
| <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="125000000"/> |
| <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="200000000"/> |
| <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="PLL0"/> |
| <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="50000000"/> |
| <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="PLL0"/> |
| <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE"/> |
| <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/> |
| <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET"/> |
| <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK"/> |
| <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT CLKFREQUENCY="125000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_125_0000MHz"/> |
| <PORT CLKFREQUENCY="200000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="clk_200_0000MHzPLL0"/> |
| <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/> |
| <PORT CLKFREQUENCY="600000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/> |
| <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/> |
| </PORTS> |
| <BUSINTERFACES/> |
| </MODULE> |
| <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm"> |
| <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x74800000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x7480ffff"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/> |
| <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/> |
| <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> |
| <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/> |
| <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_debug_Dbg_Clk"/> |
| <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_debug_Dbg_TDI"/> |
| <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_debug_Dbg_TDO"/> |
| <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/> |
| <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_debug_Dbg_Capture"/> |
| <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_debug_Dbg_Shift"/> |
| <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_debug_Dbg_Update"/> |
| <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_debug_Debug_Rst"/> |
| <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> |
| <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> |
| <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> |
| <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> |
| <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> |
| <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> |
| <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/> |
| <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/> |
| <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/> |
| <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/> |
| <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/> |
| <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/> |
| <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/> |
| <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/> |
| <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/> |
| <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/> |
| <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/> |
| <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/> |
| <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/> |
| <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/> |
| <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/> |
| <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/> |
| <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/> |
| <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/> |
| <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/> |
| <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_abort"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_BE"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_size"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_type"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/> |
| <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_wait"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/> |
| <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/> |
| <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/> |
| <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/> |
| <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/> |
| <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/> |
| <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/> |
| <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/> |
| <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/> |
| <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/> |
| <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/> |
| <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/> |
| <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/> |
| <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/> |
| <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/> |
| <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/> |
| <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/> |
| <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="SPLB"/> |
| <SLAVE BUSINTERFACE="S_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| </MODULE> |
| <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite"> |
| <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout"> |
| <DESCRIPTION>Serial Data Out</DESCRIPTION> |
| </PORT> |
| <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin"> |
| <DESCRIPTION>Serial Data In</DESCRIPTION> |
| </PORT> |
| <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="TX"/> |
| <PORTMAP DIR="I" PHYSICAL="RX"/> |
| </PORTMAPS> |
| </IOINTERFACE> |
| </IOINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| <INTERRUPTINFO TYPE="SOURCE"> |
| <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/> |
| </INTERRUPTINFO> |
| </MODULE> |
| <MODULE HWVERSION="1.01.a" INSTANCE="DIP_Switches_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio"> |
| <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40040000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4004ffff"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="DIP_Switches_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="DIP_Switches_4Bits_IP2INTC_Irpt"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]"> |
| <DESCRIPTION>GPIO1 Data IO</DESCRIPTION> |
| </PORT> |
| <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"> |
| <DESCRIPTION>GPIO2 Data IO</DESCRIPTION> |
| </PORT> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/> |
| <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/> |
| <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/> |
| <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/> |
| </PORTMAPS> |
| </IOINTERFACE> |
| </IOINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1074003968" BASENAME="C_BASEADDR" BASEVALUE="0x40040000" HIGHDECIMAL="1074069503" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4004ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| <INTERRUPTINFO TYPE="SOURCE"> |
| <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/> |
| </INTERRUPTINFO> |
| </MODULE> |
| <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio"> |
| <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]"> |
| <DESCRIPTION>GPIO1 Data IO</DESCRIPTION> |
| </PORT> |
| <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"> |
| <DESCRIPTION>GPIO2 Data IO</DESCRIPTION> |
| </PORT> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/> |
| <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/> |
| <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/> |
| <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/> |
| <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/> |
| </PORTMAPS> |
| </IOINTERFACE> |
| </IOINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| </MODULE> |
| <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio"> |
| <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/> |
| <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]"> |
| <DESCRIPTION>GPIO1 Data IO</DESCRIPTION> |
| </PORT> |
| <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"> |
| <DESCRIPTION>GPIO2 Data IO</DESCRIPTION> |
| </PORT> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/> |
| <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/> |
| <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/> |
| <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/> |
| <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/> |
| </PORTMAPS> |
| </IOINTERFACE> |
| </IOINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| <INTERRUPTINFO TYPE="SOURCE"> |
| <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/> |
| </INTERRUPTINFO> |
| </MODULE> |
| <MODULE HWVERSION="1.02.a" INSTANCE="MCB_DDR3" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx"> |
| <DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">Spartan-6 memory controller</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_02_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="R7"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_MCB_PERFORMANCE" TYPE="STRING" VALUE="STANDARD"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_BYPASS_CORE_UCF" VALUE="0"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="5" NAME="C_S0_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc0000000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="6" NAME="C_S0_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xc7ffffff"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="7" NAME="C_S1_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="8" NAME="C_S1_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="9" NAME="C_S2_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="10" NAME="C_S2_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="11" NAME="C_S3_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="12" NAME="C_S3_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="13" NAME="C_S4_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="14" NAME="C_S4_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="15" NAME="C_S5_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_S5_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="18" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT41J64M16XX-187E"/> |
| <PARAMETER MPD_INDEX="19" NAME="C_MEM_BASEPARTNO" TYPE="STRING" VALUE="NOT_SET"/> |
| <PARAMETER MPD_INDEX="20" NAME="C_NUM_DQ_PINS" TYPE="INTEGER" VALUE="16"/> |
| <PARAMETER MPD_INDEX="21" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="22" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="23" NAME="C_MEM_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/> |
| <PARAMETER MPD_INDEX="24" NAME="C_MEM_TRAS" TYPE="INTEGER" VALUE="-1"/> |
| <PARAMETER MPD_INDEX="25" NAME="C_MEM_TRCD" TYPE="INTEGER" VALUE="-1"/> |
| <PARAMETER MPD_INDEX="26" NAME="C_MEM_TREFI" TYPE="INTEGER" VALUE="-1"/> |
| <PARAMETER MPD_INDEX="27" NAME="C_MEM_TRFC" TYPE="INTEGER" VALUE="-1"/> |
| <PARAMETER MPD_INDEX="28" NAME="C_MEM_TRP" TYPE="INTEGER" VALUE="-1"/> |
| <PARAMETER MPD_INDEX="29" NAME="C_MEM_TWR" TYPE="INTEGER" VALUE="-1"/> |
| <PARAMETER MPD_INDEX="30" NAME="C_MEM_TRTP" TYPE="INTEGER" VALUE="-1"/> |
| <PARAMETER MPD_INDEX="31" NAME="C_MEM_TWTR" TYPE="INTEGER" VALUE="-1"/> |
| <PARAMETER MPD_INDEX="32" NAME="C_PORT_CONFIG" TYPE="STRING" VALUE="B32_B32_B32_B32"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="33" NAME="C_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="34" NAME="C_SKIP_IN_TERM_CAL_VALUE" TYPE="STRING" VALUE="NONE"/> |
| <PARAMETER MPD_INDEX="35" NAME="C_MEMCLK_PERIOD" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="36" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="ROW_BANK_COLUMN"/> |
| <PARAMETER MPD_INDEX="37" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/> |
| <PARAMETER MPD_INDEX="38" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/> |
| <PARAMETER MPD_INDEX="39" NAME="C_SIMULATION" TYPE="STRING" VALUE="FALSE"/> |
| <PARAMETER MPD_INDEX="40" NAME="C_MEM_DDR1_2_ODS" TYPE="STRING" VALUE="FULL"/> |
| <PARAMETER MPD_INDEX="41" NAME="C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/> |
| <PARAMETER MPD_INDEX="42" NAME="C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/> |
| <PARAMETER MPD_INDEX="43" NAME="C_MEM_DDR2_RTT" TYPE="STRING" VALUE="150OHMS"/> |
| <PARAMETER MPD_INDEX="44" NAME="C_MEM_DDR2_DIFF_DQS_EN" TYPE="STRING" VALUE="YES"/> |
| <PARAMETER MPD_INDEX="45" NAME="C_MEM_DDR2_3_PA_SR" TYPE="STRING" VALUE="FULL"/> |
| <PARAMETER MPD_INDEX="46" NAME="C_MEM_DDR2_3_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/> |
| <PARAMETER MPD_INDEX="47" NAME="C_MEM_DDR3_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/> |
| <PARAMETER MPD_INDEX="48" NAME="C_MEM_DDR3_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/> |
| <PARAMETER MPD_INDEX="49" NAME="C_MEM_DDR3_ODS" TYPE="STRING" VALUE="DIV6"/> |
| <PARAMETER MPD_INDEX="50" NAME="C_MEM_DDR3_RTT" TYPE="STRING" VALUE="DIV4"/> |
| <PARAMETER MPD_INDEX="51" NAME="C_MEM_DDR3_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/> |
| <PARAMETER MPD_INDEX="52" NAME="C_MEM_MOBILE_PA_SR" TYPE="STRING" VALUE="FULL"/> |
| <PARAMETER MPD_INDEX="53" NAME="C_MEM_MDDR_ODS" TYPE="STRING" VALUE="FULL"/> |
| <PARAMETER MPD_INDEX="54" NAME="C_ARB_ALGORITHM" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="55" NAME="C_ARB_NUM_TIME_SLOTS" TYPE="INTEGER" VALUE="12"/> |
| <PARAMETER MPD_INDEX="56" NAME="C_ARB_TIME_SLOT_0" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/> |
| <PARAMETER MPD_INDEX="57" NAME="C_ARB_TIME_SLOT_1" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/> |
| <PARAMETER MPD_INDEX="58" NAME="C_ARB_TIME_SLOT_2" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/> |
| <PARAMETER MPD_INDEX="59" NAME="C_ARB_TIME_SLOT_3" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/> |
| <PARAMETER MPD_INDEX="60" NAME="C_ARB_TIME_SLOT_4" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/> |
| <PARAMETER MPD_INDEX="61" NAME="C_ARB_TIME_SLOT_5" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/> |
| <PARAMETER MPD_INDEX="62" NAME="C_ARB_TIME_SLOT_6" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/> |
| <PARAMETER MPD_INDEX="63" NAME="C_ARB_TIME_SLOT_7" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/> |
| <PARAMETER MPD_INDEX="64" NAME="C_ARB_TIME_SLOT_8" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/> |
| <PARAMETER MPD_INDEX="65" NAME="C_ARB_TIME_SLOT_9" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/> |
| <PARAMETER MPD_INDEX="66" NAME="C_ARB_TIME_SLOT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/> |
| <PARAMETER MPD_INDEX="67" NAME="C_ARB_TIME_SLOT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="68" NAME="C_S0_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="69" NAME="C_S0_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="70" NAME="C_S0_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="3"/> |
| <PARAMETER MPD_INDEX="71" NAME="C_S0_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="72" NAME="C_S0_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="73" NAME="C_S0_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="74" NAME="C_S0_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="75" NAME="C_S0_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="76" NAME="C_S0_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/> |
| <PARAMETER MPD_INDEX="77" NAME="C_S0_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/> |
| <PARAMETER MPD_INDEX="78" NAME="C_S0_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="79" NAME="C_S0_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="80" NAME="C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="81" NAME="C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="82" NAME="C_S1_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="83" NAME="C_S1_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="84" NAME="C_S1_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="85" NAME="C_S1_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="86" NAME="C_S1_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="87" NAME="C_S1_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="88" NAME="C_S1_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="89" NAME="C_S1_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="90" NAME="C_S1_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/> |
| <PARAMETER MPD_INDEX="91" NAME="C_S1_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/> |
| <PARAMETER MPD_INDEX="92" NAME="C_S1_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="93" NAME="C_S1_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="94" NAME="C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="95" NAME="C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="96" NAME="C_S2_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="97" NAME="C_S2_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="98" NAME="C_S2_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="99" NAME="C_S2_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="100" NAME="C_S2_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="101" NAME="C_S2_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="102" NAME="C_S2_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="103" NAME="C_S2_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="104" NAME="C_S2_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/> |
| <PARAMETER MPD_INDEX="105" NAME="C_S2_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/> |
| <PARAMETER MPD_INDEX="106" NAME="C_S2_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="107" NAME="C_S2_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="108" NAME="C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="109" NAME="C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="110" NAME="C_S3_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="111" NAME="C_S3_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="112" NAME="C_S3_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="113" NAME="C_S3_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="114" NAME="C_S3_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="115" NAME="C_S3_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="116" NAME="C_S3_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="117" NAME="C_S3_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="118" NAME="C_S3_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/> |
| <PARAMETER MPD_INDEX="119" NAME="C_S3_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/> |
| <PARAMETER MPD_INDEX="120" NAME="C_S3_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="121" NAME="C_S3_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="122" NAME="C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="123" NAME="C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="124" NAME="C_S4_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="125" NAME="C_S4_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="126" NAME="C_S4_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="127" NAME="C_S4_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="128" NAME="C_S4_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="129" NAME="C_S4_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="130" NAME="C_S4_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="131" NAME="C_S4_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="132" NAME="C_S4_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/> |
| <PARAMETER MPD_INDEX="133" NAME="C_S4_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/> |
| <PARAMETER MPD_INDEX="134" NAME="C_S4_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="135" NAME="C_S4_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="136" NAME="C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="137" NAME="C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="138" NAME="C_S5_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="139" NAME="C_S5_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="140" NAME="C_S5_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="141" NAME="C_S5_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="142" NAME="C_S5_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="143" NAME="C_S5_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="144" NAME="C_S5_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="145" NAME="C_S5_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="146" NAME="C_S5_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/> |
| <PARAMETER MPD_INDEX="147" NAME="C_S5_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/> |
| <PARAMETER MPD_INDEX="148" NAME="C_S5_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="149" NAME="C_S5_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="150" NAME="C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="151" NAME="C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="152" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="153" NAME="C_SYS_RST_PRESENT" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S0_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" NAME="C_INTERCONNECT_S0_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" NAME="C_INTERCONNECT_S0_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" NAME="C_INTERCONNECT_S0_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S0_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S0_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="17" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="18" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="16" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="26" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="9" MPD_INDEX="12" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="10" MPD_INDEX="11" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/> |
| <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="27" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/> |
| <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="15" LSB="0" MHS_INDEX="12" MPD_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq" VECFORMULA="[C_NUM_DQ_PINS-1:0]"/> |
| <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="13" MPD_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/> |
| <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="14" MPD_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/> |
| <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="15" MPD_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/> |
| <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="16" MPD_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/> |
| <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="17" MPD_INDEX="28" NAME="rzq" SIGNAME="rzq"/> |
| <PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="18" MPD_INDEX="29" NAME="zio" SIGNAME="zio"/> |
| <PORT BUS="S0_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="32" NAME="s0_axi_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="30" NAME="ui_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="0" NAME="sysclk_2x" SIGIS="CLK" SIGNAME="clk_600_0000MHzPLL0_nobuf"/> |
| <PORT CLKFREQUENCY="600000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="1" NAME="sysclk_2x_180" SIGIS="CLK" SIGNAME="clk_600_0000MHz180PLL0_nobuf"/> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="10" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/> |
| <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="4" NAME="PLL_LOCK" SIGNAME="proc_sys_reset_0_Dcm_locked"/> |
| <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="2" NAME="pll_ce_0" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="pll_ce_90" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="5" NAME="pll_lock_bufpll_o" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="6" NAME="sysclk_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="7" NAME="sysclk_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="8" NAME="pll_ce_0_bufpll_o" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="9" NAME="pll_ce_90_bufpll_o" SIGNAME="__NOC__"/> |
| <PORT DIR="O" MPD_INDEX="31" NAME="uo_done_cal" SIGNAME="__NOC__"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_aresetn" DIR="I" MPD_INDEX="33" NAME="s0_axi_aresetn" SIGIS="RST" SIGNAME="axi4_0_M_aresetn"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awid" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="34" MSB="2" NAME="s0_axi_awid" RIGHT="0" SIGNAME="axi4_0_M_awid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="35" MSB="31" NAME="s0_axi_awaddr" RIGHT="0" SIGNAME="axi4_0_M_awaddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="36" MSB="7" NAME="s0_axi_awlen" RIGHT="0" SIGNAME="axi4_0_M_awlen" VECFORMULA="[7:0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="s0_axi_awsize" RIGHT="0" SIGNAME="axi4_0_M_awsize" VECFORMULA="[2:0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="s0_axi_awburst" RIGHT="0" SIGNAME="axi4_0_M_awburst" VECFORMULA="[1:0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awlock" DIR="I" MPD_INDEX="39" NAME="s0_axi_awlock" SIGNAME="axi4_0_M_awlock" VECFORMULA="[0:0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="40" MSB="3" NAME="s0_axi_awcache" RIGHT="0" SIGNAME="axi4_0_M_awcache" VECFORMULA="[3:0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="s0_axi_awprot" RIGHT="0" SIGNAME="axi4_0_M_awprot" VECFORMULA="[2:0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s0_axi_awqos" RIGHT="0" SIGNAME="axi4_0_M_awqos" VECFORMULA="[3:0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awvalid" DIR="I" MPD_INDEX="43" NAME="s0_axi_awvalid" SIGNAME="axi4_0_M_awvalid"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_awready" DIR="O" MPD_INDEX="44" NAME="s0_axi_awready" SIGNAME="axi4_0_M_awready"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="s0_axi_wdata" RIGHT="0" SIGNAME="axi4_0_M_wdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S0_AXI" DEF_SIGNAME="axi4_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s0_axi_wstrb" RIGHT="0" SIGNAME="axi4_0_M_wstrb" VECFORMULA="[((C_S0_AXI_DATA_WIDTH/8)-1):0]"/> |
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| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="242" NAME="s5_axi_wlast" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="243" NAME="s5_axi_wvalid" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="244" NAME="s5_axi_wready" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="245" MSB="3" NAME="s5_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="246" MSB="1" NAME="s5_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="247" NAME="s5_axi_bvalid" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="248" NAME="s5_axi_bready" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="249" MSB="3" NAME="s5_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="250" MSB="31" NAME="s5_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="251" MSB="7" NAME="s5_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="252" MSB="2" NAME="s5_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="253" MSB="1" NAME="s5_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="s5_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="255" MSB="3" NAME="s5_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="256" MSB="2" NAME="s5_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="257" MSB="3" NAME="s5_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="s5_axi_arvalid" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="259" NAME="s5_axi_arready" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="260" MSB="3" NAME="s5_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="261" MSB="31" NAME="s5_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="262" MSB="1" NAME="s5_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="s5_axi_rlast" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="s5_axi_rvalid" SIGNAME="__NOC__"/> |
| <PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="265" NAME="s5_axi_rready" SIGNAME="__NOC__"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S0_AXI" PROTOCOL="AXI4" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_aresetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awid"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awaddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_awvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_awready"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_wdata"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_wstrb"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_wlast"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_wvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_wready"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_bid"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_bresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_bvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_bready"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arid"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_araddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_arvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_arready"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_rid"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_rdata"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_rresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_rlast"/> |
| <PORTMAP DIR="O" PHYSICAL="s0_axi_rvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s0_axi_rready"/> |
| </PORTMAPS> |
| <MASTERS> |
| <MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/> |
| <MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/> |
| <MASTER BUSINTERFACE="M_AXI_SG" INSTANCE="ETHERNET_dma"/> |
| <MASTER BUSINTERFACE="M_AXI_MM2S" INSTANCE="ETHERNET_dma"/> |
| <MASTER BUSINTERFACE="M_AXI_S2MM" INSTANCE="ETHERNET_dma"/> |
| </MASTERS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S1_AXI" PROTOCOL="AXI4" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_aresetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awid"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awaddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_awvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_awready"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_wdata"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_wstrb"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_wlast"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_wvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_wready"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_bid"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_bresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_bvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_bready"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arid"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_araddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_arvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_arready"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_rid"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_rdata"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_rresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_rlast"/> |
| <PORTMAP DIR="O" PHYSICAL="s1_axi_rvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s1_axi_rready"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="2" NAME="S2_AXI" PROTOCOL="AXI4" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_aresetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awid"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awaddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_awvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_awready"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_wdata"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_wstrb"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_wlast"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_wvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_wready"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_bid"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_bresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_bvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_bready"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arid"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_araddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_arvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_arready"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_rid"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_rdata"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_rresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_rlast"/> |
| <PORTMAP DIR="O" PHYSICAL="s2_axi_rvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s2_axi_rready"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S3_AXI" PROTOCOL="AXI4" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_aresetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awid"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awaddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_awvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_awready"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_wdata"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_wstrb"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_wlast"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_wvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_wready"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_bid"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_bresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_bvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_bready"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arid"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_araddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_arvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_arready"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_rid"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_rdata"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_rresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_rlast"/> |
| <PORTMAP DIR="O" PHYSICAL="s3_axi_rvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s3_axi_rready"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="4" NAME="S4_AXI" PROTOCOL="AXI4" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_aresetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awid"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awaddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_awvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_awready"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_wdata"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_wstrb"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_wlast"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_wvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_wready"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_bid"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_bresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_bvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_bready"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arid"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_araddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_arvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_arready"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_rid"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_rdata"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_rresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_rlast"/> |
| <PORTMAP DIR="O" PHYSICAL="s4_axi_rvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s4_axi_rready"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="5" NAME="S5_AXI" PROTOCOL="AXI4" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_aresetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awid"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awaddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_awvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_awready"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_wdata"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_wstrb"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_wlast"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_wvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_wready"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_bid"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_bresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_bvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_bready"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arid"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_araddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arlen"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arsize"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arburst"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arlock"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arcache"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arprot"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arqos"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_arvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_arready"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_rid"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_rdata"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_rresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_rlast"/> |
| <PORTMAP DIR="O" PHYSICAL="s5_axi_rvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s5_axi_rready"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/> |
| <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/> |
| <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/> |
| <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/> |
| <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/> |
| <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/> |
| <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/> |
| <PORTMAP DIR="IO" PHYSICAL="rzq"/> |
| <PORTMAP DIR="IO" PHYSICAL="zio"/> |
| </PORTMAPS> |
| </IOINTERFACE> |
| </IOINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0xc0000000" HIGHDECIMAL="3355443199" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0xc7ffffff" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S0_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S1_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S1_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S1_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S2_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S2_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S2_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S3_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S3_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S3_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S4_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S4_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S4_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S5_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S5_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S5_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| </MODULE> |
| <MODULE HWVERSION="2.01.a" INSTANCE="ETHERNET" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernet"> |
| <DESCRIPTION TYPE="SHORT">AXI Ethernet</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">AXI Ethernet MAC</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernet_v2_01_a/doc/ds759_axi_ethernet.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO EXPIRESON="Jan-30-2016" ICON_NAME="ps_core_preferred" STATE="Hardware Evaluation" TYPE="Hardware_Evaluation"/> |
| <PARAMETERS> |
| <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER MPD_INDEX="1" NAME="C_AXI_STR_TXC_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="2" NAME="C_AXI_STR_TXD_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_AXI_STR_RXS_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_AXI_STR_RXD_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_AXI_STR_TXC_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_AXI_STR_TXD_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_AXI_STR_RXS_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_AXI_STR_RXD_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_AXI_STR_AVBTX_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_AVB_TX"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_AXI_STR_AVBRX_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_AVB_RX"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="13" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41240000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="27" MPD_INDEX="14" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4127ffff"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="18" NAME="C_TRANS" TYPE="STRING" VALUE="A"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="C_PHYADDR" TYPE="std_logic_vector" VALUE="0B00001"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="C_INCLUDE_IO" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="21" NAME="C_TYPE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="22" NAME="C_PHY_TYPE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="23" NAME="C_HALFDUP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="24" NAME="C_TXMEM" TYPE="INTEGER" VALUE="4096"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="25" NAME="C_RXMEM" TYPE="INTEGER" VALUE="4096"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="26" NAME="C_TXCSUM" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="27" NAME="C_RXCSUM" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="28" NAME="C_TXVLAN_TRAN" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="29" NAME="C_RXVLAN_TRAN" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="30" NAME="C_TXVLAN_TAG" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="31" NAME="C_RXVLAN_TAG" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="32" NAME="C_TXVLAN_STRP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="33" NAME="C_RXVLAN_STRP" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="34" NAME="C_MCAST_EXTEND" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="35" NAME="C_STATS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="36" NAME="C_AVB" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="37" NAME="C_SIMULATION" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC" VALUE="0"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="IO" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="108" NAME="MDIO" SIGNAME="ETHERNET_MDIO" TRI_I="MDIO_I" TRI_O="MDIO_O" TRI_T="MDIO_T"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="83" NAME="MDC" SIGNAME="ETHERNET_MDC"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="65" NAME="GMII_TX_ER" SIGNAME="ETHERNET_TX_ER"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="3" MPD_INDEX="63" MSB="7" NAME="GMII_TXD" RIGHT="0" SIGNAME="ETHERNET_TXD" VECFORMULA="[7:0]"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="64" NAME="GMII_TX_EN" SIGNAME="ETHERNET_TX_EN"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="60" NAME="MII_TX_CLK" SIGNAME="ETHERNET_MII_TX_CLK"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="66" NAME="GMII_TX_CLK" SIGNAME="ETHERNET_TX_CLK"/> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="7" MPD_INDEX="67" MSB="7" NAME="GMII_RXD" RIGHT="0" SIGNAME="ETHERNET_RXD" VECFORMULA="[7:0]"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="69" NAME="GMII_RX_ER" SIGNAME="ETHERNET_RX_ER"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="70" NAME="GMII_RX_CLK" SIGNAME="ETHERNET_RX_CLK"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="68" NAME="GMII_RX_DV" SIGNAME="ETHERNET_RX_DV"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="48" NAME="PHY_RST_N" SIGNAME="ETHERNET_PHY_RST_N"/> |
| <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT CLKFREQUENCY="125000000" DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="49" NAME="GTX_CLK" SIGIS="CLK" SIGNAME="clk_125_0000MHz"/> |
| <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="52" NAME="REF_CLK" SIGIS="CLK" SIGNAME="clk_200_0000MHzPLL0"/> |
| <PORT BUS="AXI_STR_TXD" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="20" NAME="AXI_STR_TXD_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="AXI_STR_TXC" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="27" NAME="AXI_STR_TXC_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="AXI_STR_RXD" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="34" NAME="AXI_STR_RXD_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="AXI_STR_RXS" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="41" NAME="AXI_STR_RXS_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="21" NAME="AXI_STR_TXD_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_TXD_ARESETN"/> |
| <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="28" NAME="AXI_STR_TXC_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_TXC_ARESETN"/> |
| <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="35" NAME="AXI_STR_RXD_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_RXD_ARESETN"/> |
| <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="42" NAME="AXI_STR_RXS_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_RXS_ARESETN"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="2" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="ETHERNET_INTERRUPT"/> |
| <PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/> |
| <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TVALID" DIR="I" MPD_INDEX="22" NAME="AXI_STR_TXD_TVALID" SIGNAME="ETHERNET_dma_txd_TVALID"/> |
| <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TREADY" DIR="O" MPD_INDEX="23" NAME="AXI_STR_TXD_TREADY" SIGNAME="ETHERNET_dma_txd_TREADY"/> |
| <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TLAST" DIR="I" MPD_INDEX="24" NAME="AXI_STR_TXD_TLAST" SIGNAME="ETHERNET_dma_txd_TLAST"/> |
| <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="AXI_STR_TXD_TKEEP" RIGHT="0" SIGNAME="ETHERNET_dma_txd_TKEEP" VECFORMULA="[3:0]"/> |
| <PORT BUS="AXI_STR_TXD" DEF_SIGNAME="ETHERNET_dma_txd_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="26" MSB="31" NAME="AXI_STR_TXD_TDATA" RIGHT="0" SIGNAME="ETHERNET_dma_txd_TDATA" VECFORMULA="[31:0]"/> |
| <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TVALID" DIR="I" MPD_INDEX="29" NAME="AXI_STR_TXC_TVALID" SIGNAME="ETHERNET_dma_txc_TVALID"/> |
| <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TREADY" DIR="O" MPD_INDEX="30" NAME="AXI_STR_TXC_TREADY" SIGNAME="ETHERNET_dma_txc_TREADY"/> |
| <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TLAST" DIR="I" MPD_INDEX="31" NAME="AXI_STR_TXC_TLAST" SIGNAME="ETHERNET_dma_txc_TLAST"/> |
| <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="32" MSB="3" NAME="AXI_STR_TXC_TKEEP" RIGHT="0" SIGNAME="ETHERNET_dma_txc_TKEEP" VECFORMULA="[3:0]"/> |
| <PORT BUS="AXI_STR_TXC" DEF_SIGNAME="ETHERNET_dma_txc_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="33" MSB="31" NAME="AXI_STR_TXC_TDATA" RIGHT="0" SIGNAME="ETHERNET_dma_txc_TDATA" VECFORMULA="[31:0]"/> |
| <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TVALID" DIR="O" MPD_INDEX="36" NAME="AXI_STR_RXD_TVALID" SIGNAME="ETHERNET_dma_rxd_TVALID"/> |
| <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TREADY" DIR="I" MPD_INDEX="37" NAME="AXI_STR_RXD_TREADY" SIGNAME="ETHERNET_dma_rxd_TREADY"/> |
| <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TLAST" DIR="O" MPD_INDEX="38" NAME="AXI_STR_RXD_TLAST" SIGNAME="ETHERNET_dma_rxd_TLAST"/> |
| <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="39" MSB="3" NAME="AXI_STR_RXD_TKEEP" RIGHT="0" SIGNAME="ETHERNET_dma_rxd_TKEEP" VECFORMULA="[3:0]"/> |
| <PORT BUS="AXI_STR_RXD" DEF_SIGNAME="ETHERNET_dma_rxd_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="AXI_STR_RXD_TDATA" RIGHT="0" SIGNAME="ETHERNET_dma_rxd_TDATA" VECFORMULA="[31:0]"/> |
| <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TVALID" DIR="O" MPD_INDEX="43" NAME="AXI_STR_RXS_TVALID" SIGNAME="ETHERNET_dma_rxs_TVALID"/> |
| <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TREADY" DIR="I" MPD_INDEX="44" NAME="AXI_STR_RXS_TREADY" SIGNAME="ETHERNET_dma_rxs_TREADY"/> |
| <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TLAST" DIR="O" MPD_INDEX="45" NAME="AXI_STR_RXS_TLAST" SIGNAME="ETHERNET_dma_rxs_TLAST"/> |
| <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="AXI_STR_RXS_TKEEP" RIGHT="0" SIGNAME="ETHERNET_dma_rxs_TKEEP" VECFORMULA="[3:0]"/> |
| <PORT BUS="AXI_STR_RXS" DEF_SIGNAME="ETHERNET_dma_rxs_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="47" MSB="31" NAME="AXI_STR_RXS_TDATA" RIGHT="0" SIGNAME="ETHERNET_dma_rxs_TDATA" VECFORMULA="[31:0]"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="50" NAME="MGT_CLK_P" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="51" NAME="MGT_CLK_N" SIGNAME="__NOC__"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="53" MSB="3" NAME="MII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="54" NAME="MII_TX_EN" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="55" NAME="MII_TX_ER" SIGNAME="__NOC__"/> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="56" MSB="3" NAME="MII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="57" NAME="MII_RX_DV" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="58" NAME="MII_RX_ER" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="59" NAME="MII_RX_CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="61" NAME="MII_COL" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="62" NAME="MII_CRS" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" MPD_INDEX="71" NAME="GMII_COL" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" MPD_INDEX="72" NAME="GMII_CRS" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="73" NAME="TXP" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="74" NAME="TXN" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="75" NAME="RXP" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="76" NAME="RXN" SIGNAME="__NOC__"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="77" MSB="3" NAME="RGMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="78" NAME="RGMII_TX_CTL" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="79" NAME="RGMII_TXC" SIGNAME="__NOC__"/> |
| <PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="RGMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="81" NAME="RGMII_RX_CTL" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="82" NAME="RGMII_RXC" SIGNAME="__NOC__"/> |
| <PORT DIR="I" IOS="AXIETHERNETIF" MPD_INDEX="84" NAME="MDIO_I" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" MPD_INDEX="85" NAME="MDIO_O" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IOS="AXIETHERNETIF" MPD_INDEX="86" NAME="MDIO_T" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="AXI_STR_AVBTX_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="88" NAME="AXI_STR_AVBTX_ARESETN" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="89" NAME="AXI_STR_AVBTX_TVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="AXI_STR_AVBTX_TREADY" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="AXI_STR_AVBTX_TLAST" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="92" MSB="7" NAME="AXI_STR_AVBTX_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/> |
| <PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="93" NAME="AXI_STR_AVBTX_TUSER" SIGNAME="__NOC__" VECFORMULA="[0:0]"/> |
| <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="AXI_STR_AVBRX_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="AXI_STR_AVBRX_ARESETN" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="AXI_STR_AVBRX_TVALID" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="AXI_STR_AVBRX_TLAST" SIGNAME="__NOC__"/> |
| <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="98" MSB="7" NAME="AXI_STR_AVBRX_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/> |
| <PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="AXI_STR_AVBRX_TUSER" SIGNAME="__NOC__" VECFORMULA="[0:0]"/> |
| <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="100" NAME="RTC_CLK" SIGIS="CLK" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="101" NAME="AV_INTERRUPT_10MS" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="102" NAME="AV_INTERRUPT_PTP_TX" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="103" NAME="AV_INTERRUPT_PTP_RX" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="AV_RTC_NANOSECFIELD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="47" LSB="0" MPD_INDEX="105" MSB="47" NAME="AV_RTC_SECFIELD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[47:0]"/> |
| <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="106" NAME="AV_CLK_8K" SIGNAME="__NOC__"/> |
| <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="AV_RTC_NANOSECFIELD_1722" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="ETHERNET_dma_txd" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="AXI_STR_TXD" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_TXD_TREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TKEEP"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TDATA"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="ETHERNET_dma_txc" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="AXI_STR_TXC" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_TXC_TREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TKEEP"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TDATA"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="ETHERNET_dma_rxd" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="AXI_STR_RXD" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_TREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TKEEP"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TDATA"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="ETHERNET_dma_rxs" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="AXI_STR_RXS" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_TREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TKEEP"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TDATA"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="5" NAME="AXI_STR_AVBTX" PROTOCOL="XIL_AXI_STREAM_ETH_AVB_TX" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBTX_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBTX_TREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TLAST"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TUSER"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="6" NAME="AXI_STR_AVBRX" PROTOCOL="XIL_AXI_STREAM_ETH_AVB_RX" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBRX_ARESETN"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TLAST"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TUSER"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <IOINTERFACES> |
| <IOINTERFACE MPD_INDEX="0" NAME="AXIETHERNETIF" TYPE="XIL_AXIETHERNET_V1"> |
| <PORTMAPS> |
| <PORTMAP DIR="IO" PHYSICAL="MDIO"/> |
| <PORTMAP DIR="O" PHYSICAL="MDC"/> |
| <PORTMAP DIR="O" PHYSICAL="GMII_TX_ER"/> |
| <PORTMAP DIR="O" PHYSICAL="GMII_TXD"/> |
| <PORTMAP DIR="O" PHYSICAL="GMII_TX_EN"/> |
| <PORTMAP DIR="I" PHYSICAL="MII_TX_CLK"/> |
| <PORTMAP DIR="O" PHYSICAL="GMII_TX_CLK"/> |
| <PORTMAP DIR="I" PHYSICAL="GMII_RXD"/> |
| <PORTMAP DIR="I" PHYSICAL="GMII_RX_ER"/> |
| <PORTMAP DIR="I" PHYSICAL="GMII_RX_CLK"/> |
| <PORTMAP DIR="I" PHYSICAL="GMII_RX_DV"/> |
| <PORTMAP DIR="O" PHYSICAL="PHY_RST_N"/> |
| <PORTMAP DIR="I" PHYSICAL="GTX_CLK"/> |
| <PORTMAP DIR="I" PHYSICAL="MGT_CLK_P"/> |
| <PORTMAP DIR="I" PHYSICAL="MGT_CLK_N"/> |
| <PORTMAP DIR="O" PHYSICAL="MII_TXD"/> |
| <PORTMAP DIR="O" PHYSICAL="MII_TX_EN"/> |
| <PORTMAP DIR="O" PHYSICAL="MII_TX_ER"/> |
| <PORTMAP DIR="I" PHYSICAL="MII_RXD"/> |
| <PORTMAP DIR="I" PHYSICAL="MII_RX_DV"/> |
| <PORTMAP DIR="I" PHYSICAL="MII_RX_ER"/> |
| <PORTMAP DIR="I" PHYSICAL="MII_RX_CLK"/> |
| <PORTMAP DIR="I" PHYSICAL="MII_COL"/> |
| <PORTMAP DIR="I" PHYSICAL="MII_CRS"/> |
| <PORTMAP DIR="I" PHYSICAL="GMII_COL"/> |
| <PORTMAP DIR="I" PHYSICAL="GMII_CRS"/> |
| <PORTMAP DIR="O" PHYSICAL="TXP"/> |
| <PORTMAP DIR="O" PHYSICAL="TXN"/> |
| <PORTMAP DIR="I" PHYSICAL="RXP"/> |
| <PORTMAP DIR="I" PHYSICAL="RXN"/> |
| <PORTMAP DIR="O" PHYSICAL="RGMII_TXD"/> |
| <PORTMAP DIR="O" PHYSICAL="RGMII_TX_CTL"/> |
| <PORTMAP DIR="O" PHYSICAL="RGMII_TXC"/> |
| <PORTMAP DIR="I" PHYSICAL="RGMII_RXD"/> |
| <PORTMAP DIR="I" PHYSICAL="RGMII_RX_CTL"/> |
| <PORTMAP DIR="I" PHYSICAL="RGMII_RXC"/> |
| <PORTMAP DIR="I" PHYSICAL="MDIO_I"/> |
| <PORTMAP DIR="O" PHYSICAL="MDIO_O"/> |
| <PORTMAP DIR="O" PHYSICAL="MDIO_T"/> |
| </PORTMAPS> |
| </IOINTERFACE> |
| </IOINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1092878336" BASENAME="C_BASEADDR" BASEVALUE="0x41240000" HIGHDECIMAL="1093140479" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4127ffff" MEMTYPE="REGISTER" MINSIZE="0x40000" SIZE="262144" SIZEABRV="256K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| <INTERRUPTINFO TYPE="SOURCE"> |
| <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/> |
| </INTERRUPTINFO> |
| </MODULE> |
| <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="PERIPHERAL" MODTYPE="axi_timer"> |
| <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41c00000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x41c0ffff"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_Interrupt"/> |
| <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__"> |
| <DESCRIPTION>Capture Trig 0</DESCRIPTION> |
| </PORT> |
| <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__"> |
| <DESCRIPTION>Capture Trig 1</DESCRIPTION> |
| </PORT> |
| <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__"> |
| <DESCRIPTION>Generate Out 0</DESCRIPTION> |
| </PORT> |
| <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__"> |
| <DESCRIPTION>Generate Out 1</DESCRIPTION> |
| </PORT> |
| <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__"> |
| <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION> |
| </PORT> |
| <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| <INTERRUPTINFO TYPE="SOURCE"> |
| <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="4"/> |
| </INTERRUPTINFO> |
| </MODULE> |
| <MODULE HWVERSION="3.00.a" INSTANCE="ETHERNET_dma" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="PERIPHERAL" MODTYPE="axi_dma"> |
| <DESCRIPTION TYPE="SHORT">AXI DMA Engine</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_dma_v3_00_a/doc/axi_dma_ds781.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_LITE_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="1" NAME="C_S_AXI_LITE_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_DLYTMR_RESOLUTION" TYPE="INTEGER" VALUE="1250"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="3" NAME="C_PRMRY_IS_ACLK_ASYNC" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_SG_INCLUDE_DESC_QUEUE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="5" NAME="C_SG_INCLUDE_STSCNTRL_STRM" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_SG_USE_STSAPP_LENGTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="7" NAME="C_SG_LENGTH_WIDTH" TYPE="INTEGER" VALUE="16"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_SG_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_M_AXI_SG_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="12" NAME="C_INCLUDE_MM2S" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="C_INCLUDE_MM2S_DRE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_MM2S_BURST_SIZE" TYPE="INTEGER" VALUE="16"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_M_AXI_MM2S_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="16" NAME="C_M_AXI_MM2S_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="17" NAME="C_M_AXIS_MM2S_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="18" NAME="C_INCLUDE_S2MM" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="19" NAME="C_INCLUDE_S2MM_DRE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="20" NAME="C_S2MM_BURST_SIZE" TYPE="INTEGER" VALUE="16"/> |
| <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_S2MM_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_S2MM_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="23" NAME="C_S_AXIS_S2MM_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="24" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="25" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x41e00000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="26" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x41e0ffff"/> |
| <PARAMETER MPD_INDEX="27" NAME="C_S_AXI_LITE_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_SG_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_MM2S_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER MPD_INDEX="30" NAME="C_M_AXI_S2MM_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/> |
| <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_LITE_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER MPD_INDEX="32" NAME="C_S_AXI_LITE_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_LITE_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SG_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_SG_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_SG_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_SG_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_SG_SUPPORTS_READ" TYPE="STRING" VALUE="1"/> |
| <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_SG_SUPPORTS_WRITE" TYPE="STRING" VALUE="1"/> |
| <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_MM2S_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="41" NAME="C_M_AXI_MM2S_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_MM2S_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="43" NAME="C_M_AXI_MM2S_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="44" NAME="C_M_AXI_MM2S_SUPPORTS_READ" TYPE="STRING" VALUE="1"/> |
| <PARAMETER MPD_INDEX="45" NAME="C_M_AXI_MM2S_SUPPORTS_WRITE" TYPE="STRING" VALUE="0"/> |
| <PARAMETER MPD_INDEX="46" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="47" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH" TYPE="INTEGER" VALUE="512"/> |
| <PARAMETER MPD_INDEX="48" NAME="C_M_AXI_S2MM_PROTOCOL" TYPE="STRING" VALUE="AXI4"/> |
| <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_S2MM_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_S2MM_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_S2MM_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/> |
| <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_S2MM_SUPPORTS_WRITE" TYPE="STRING" VALUE="1"/> |
| <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_S2MM_SUPPORTS_READ" TYPE="STRING" VALUE="0"/> |
| <PARAMETER MPD_INDEX="54" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING" TYPE="INTEGER" VALUE="4"/> |
| <PARAMETER MPD_INDEX="55" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH" TYPE="INTEGER" VALUE="512"/> |
| <PARAMETER MPD_INDEX="56" NAME="C_M_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA"/> |
| <PARAMETER MPD_INDEX="57" NAME="C_S_AXIS_S2MM_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA"/> |
| <PARAMETER MPD_INDEX="58" NAME="C_M_AXIS_CNTRL_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL"/> |
| <PARAMETER MPD_INDEX="59" NAME="C_S_AXIS_STS_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" NAME="C_INTERCONNECT_S_AXI_LITE_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" NAME="C_INTERCONNECT_S_AXI_LITE_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S_AXI_LITE_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S_AXI_LITE_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_S_AXI_LITE_B_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_SG_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_SG_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_SG_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_SG_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_SG_B_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_MM2S_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_MM2S_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_MM2S_B_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="29" NAME="C_INTERCONNECT_M_AXI_S2MM_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="30" NAME="C_INTERCONNECT_M_AXI_S2MM_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="31" NAME="C_INTERCONNECT_M_AXI_S2MM_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT BUS="S_AXI_LITE" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="M_AXI_SG" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="m_axi_sg_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="M_AXI_MM2S:M_AXIS_CNTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="m_axi_mm2s_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="M_AXI_S2MM:S_AXIS_STS" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="m_axi_s2mm_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/> |
| <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="63" NAME="mm2s_prmry_reset_out_n" SIGNAME="AXI_STR_TXD_ARESETN"/> |
| <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="69" NAME="mm2s_cntrl_reset_out_n" SIGNAME="AXI_STR_TXC_ARESETN"/> |
| <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="91" NAME="s2mm_prmry_reset_out_n" SIGNAME="AXI_STR_RXD_ARESETN"/> |
| <PORT BUS="S_AXIS_STS" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="97" NAME="s2mm_sts_reset_out_n" SIGNAME="AXI_STR_RXS_ARESETN"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="103" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="ETHERNET_dma_mm2s_introut"/> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="104" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="ETHERNET_dma_s2mm_introut"/> |
| <PORT BUS="S_AXI_LITE:M_AXI_SG:M_AXI_MM2S:M_AXI_S2MM:S_AXIS_STS:M_AXIS_CNTRL:M_AXIS_MM2S:S_AXIS_S2MM" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="4" NAME="axi_resetn" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="5" NAME="s_axi_lite_awvalid" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="6" NAME="s_axi_lite_awready" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="s_axi_lite_wvalid" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="s_axi_lite_wready" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="10" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="12" NAME="s_axi_lite_bvalid" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="13" NAME="s_axi_lite_bready" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="s_axi_lite_arvalid" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="s_axi_lite_arready" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="s_axi_lite_rvalid" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="s_axi_lite_rready" SIGNAME="axi4lite_0_M_RREADY"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]"/> |
| <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="m_axi_sg_awaddr" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[C_M_AXI_SG_ADDR_WIDTH-1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="m_axi_sg_awlen" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="m_axi_sg_awsize" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="m_axi_sg_awburst" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="25" MSB="2" NAME="m_axi_sg_awprot" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="m_axi_sg_awcache" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="27" NAME="m_axi_sg_awvalid" SIGNAME="axi4_0_S_AWVALID"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="28" NAME="m_axi_sg_awready" SIGNAME="axi4_0_S_AWREADY"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="m_axi_sg_wdata" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[C_M_AXI_SG_DATA_WIDTH-1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="30" MSB="3" NAME="m_axi_sg_wstrb" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(C_M_AXI_SG_DATA_WIDTH/8)-1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="31" NAME="m_axi_sg_wlast" SIGNAME="axi4_0_S_WLAST"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="32" NAME="m_axi_sg_wvalid" SIGNAME="axi4_0_S_WVALID"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="33" NAME="m_axi_sg_wready" SIGNAME="axi4_0_S_WREADY"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="m_axi_sg_bresp" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="35" NAME="m_axi_sg_bvalid" SIGNAME="axi4_0_S_BVALID"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="36" NAME="m_axi_sg_bready" SIGNAME="axi4_0_S_BREADY"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="37" MSB="31" NAME="m_axi_sg_araddr" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[C_M_AXI_SG_ADDR_WIDTH-1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="38" MSB="7" NAME="m_axi_sg_arlen" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="39" MSB="2" NAME="m_axi_sg_arsize" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="m_axi_sg_arburst" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="m_axi_sg_arprot" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="m_axi_sg_arcache" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="43" NAME="m_axi_sg_arvalid" SIGNAME="axi4_0_S_ARVALID"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="44" NAME="m_axi_sg_arready" SIGNAME="axi4_0_S_ARREADY"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="m_axi_sg_rdata" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[C_M_AXI_SG_DATA_WIDTH-1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="m_axi_sg_rresp" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="47" NAME="m_axi_sg_rlast" SIGNAME="axi4_0_S_RLAST"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="48" NAME="m_axi_sg_rvalid" SIGNAME="axi4_0_S_RVALID"/> |
| <PORT BUS="M_AXI_SG" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="49" NAME="m_axi_sg_rready" SIGNAME="axi4_0_S_RREADY"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[C_M_AXI_MM2S_ADDR_WIDTH-1:0]"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="54" MSB="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="56" NAME="m_axi_mm2s_arvalid" SIGNAME="axi4_0_S_ARVALID"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="57" NAME="m_axi_mm2s_arready" SIGNAME="axi4_0_S_ARREADY"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="58" MSB="31" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[C_M_AXI_MM2S_DATA_WIDTH-1:0]"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="59" MSB="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="60" NAME="m_axi_mm2s_rlast" SIGNAME="axi4_0_S_RLAST"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="61" NAME="m_axi_mm2s_rvalid" SIGNAME="axi4_0_S_RVALID"/> |
| <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="62" NAME="m_axi_mm2s_rready" SIGNAME="axi4_0_S_RREADY"/> |
| <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="64" MSB="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGNAME="ETHERNET_dma_txd_TDATA" VECFORMULA="[C_M_AXIS_MM2S_TDATA_WIDTH-1:0]"/> |
| <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="65" MSB="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGNAME="ETHERNET_dma_txd_TKEEP" VECFORMULA="[(C_M_AXIS_MM2S_TDATA_WIDTH/8)-1:0]"/> |
| <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TVALID" DIR="O" MPD_INDEX="66" NAME="m_axis_mm2s_tvalid" SIGNAME="ETHERNET_dma_txd_TVALID"/> |
| <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TREADY" DIR="I" MPD_INDEX="67" NAME="m_axis_mm2s_tready" SIGNAME="ETHERNET_dma_txd_TREADY"/> |
| <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="ETHERNET_dma_txd_TLAST" DIR="O" MPD_INDEX="68" NAME="m_axis_mm2s_tlast" SIGNAME="ETHERNET_dma_txd_TLAST"/> |
| <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="70" MSB="31" NAME="m_axis_mm2s_cntrl_tdata" RIGHT="0" SIGNAME="ETHERNET_dma_txc_TDATA" VECFORMULA="[C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1:0]"/> |
| <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="71" MSB="3" NAME="m_axis_mm2s_cntrl_tkeep" RIGHT="0" SIGNAME="ETHERNET_dma_txc_TKEEP" VECFORMULA="[(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1:0]"/> |
| <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TVALID" DIR="O" MPD_INDEX="72" NAME="m_axis_mm2s_cntrl_tvalid" SIGNAME="ETHERNET_dma_txc_TVALID"/> |
| <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TREADY" DIR="I" MPD_INDEX="73" NAME="m_axis_mm2s_cntrl_tready" SIGNAME="ETHERNET_dma_txc_TREADY"/> |
| <PORT BUS="M_AXIS_CNTRL" DEF_SIGNAME="ETHERNET_dma_txc_TLAST" DIR="O" MPD_INDEX="74" NAME="m_axis_mm2s_cntrl_tlast" SIGNAME="ETHERNET_dma_txc_TLAST"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[C_M_AXI_S2MM_ADDR_WIDTH-1:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="79" MSB="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="81" NAME="m_axi_s2mm_awvalid" SIGNAME="axi4_0_S_AWVALID"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="82" NAME="m_axi_s2mm_awready" SIGNAME="axi4_0_S_AWREADY"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="83" MSB="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[C_M_AXI_S2MM_DATA_WIDTH-1:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="84" MSB="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(C_M_AXI_S2MM_DATA_WIDTH/8)-1:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="85" NAME="m_axi_s2mm_wlast" SIGNAME="axi4_0_S_WLAST"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="86" NAME="m_axi_s2mm_wvalid" SIGNAME="axi4_0_S_WVALID"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="87" NAME="m_axi_s2mm_wready" SIGNAME="axi4_0_S_WREADY"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="88" MSB="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="89" NAME="m_axi_s2mm_bvalid" SIGNAME="axi4_0_S_BVALID"/> |
| <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="90" NAME="m_axi_s2mm_bready" SIGNAME="axi4_0_S_BREADY"/> |
| <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="92" MSB="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGNAME="ETHERNET_dma_rxd_TDATA" VECFORMULA="[C_S_AXIS_S2MM_TDATA_WIDTH-1:0]"/> |
| <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGNAME="ETHERNET_dma_rxd_TKEEP" VECFORMULA="[(C_S_AXIS_S2MM_TDATA_WIDTH/8)-1:0]"/> |
| <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TVALID" DIR="I" MPD_INDEX="94" NAME="s_axis_s2mm_tvalid" SIGNAME="ETHERNET_dma_rxd_TVALID"/> |
| <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TREADY" DIR="O" MPD_INDEX="95" NAME="s_axis_s2mm_tready" SIGNAME="ETHERNET_dma_rxd_TREADY"/> |
| <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="ETHERNET_dma_rxd_TLAST" DIR="I" MPD_INDEX="96" NAME="s_axis_s2mm_tlast" SIGNAME="ETHERNET_dma_rxd_TLAST"/> |
| <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="s_axis_s2mm_sts_tdata" RIGHT="0" SIGNAME="ETHERNET_dma_rxs_TDATA" VECFORMULA="[C_S_AXIS_S2MM_STS_TDATA_WIDTH-1:0]"/> |
| <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="s_axis_s2mm_sts_tkeep" RIGHT="0" SIGNAME="ETHERNET_dma_rxs_TKEEP" VECFORMULA="[(C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1:0]"/> |
| <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TVALID" DIR="I" MPD_INDEX="100" NAME="s_axis_s2mm_sts_tvalid" SIGNAME="ETHERNET_dma_rxs_TVALID"/> |
| <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TREADY" DIR="O" MPD_INDEX="101" NAME="s_axis_s2mm_sts_tready" SIGNAME="ETHERNET_dma_rxs_TREADY"/> |
| <PORT BUS="S_AXIS_STS" DEF_SIGNAME="ETHERNET_dma_rxs_TLAST" DIR="I" MPD_INDEX="102" NAME="s_axis_s2mm_sts_tlast" SIGNAME="ETHERNET_dma_rxs_TLAST"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="axi_resetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="M_AXI_SG" PROTOCOL="AXI4" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="axi_resetn"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awaddr"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awlen"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awsize"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awburst"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awprot"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awcache"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_awvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_awready"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_wdata"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_wstrb"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_wlast"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_wvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_wready"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_bresp"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_bvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_bready"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_araddr"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arlen"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arsize"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arburst"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arprot"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arcache"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_arready"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rdata"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rresp"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rlast"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_sg_rready"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="M_AXI_MM2S" PROTOCOL="AXI4" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="axi_resetn"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_araddr"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arlen"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arsize"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arburst"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arprot"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arcache"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_arready"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rdata"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rresp"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rlast"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_rready"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="ETHERNET_dma_txc" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="6" NAME="M_AXIS_CNTRL" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_aclk"/> |
| <PORTMAP DIR="O" PHYSICAL="mm2s_cntrl_reset_out_n"/> |
| <PORTMAP DIR="I" PHYSICAL="axi_resetn"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tdata"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tkeep"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_cntrl_tready"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tlast"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="M_AXI_S2MM" PROTOCOL="AXI4" TYPE="MASTER"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_aclk"/> |
| <PORTMAP DIR="I" PHYSICAL="axi_resetn"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awaddr"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awlen"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awsize"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awburst"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awprot"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awcache"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_awready"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wdata"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wstrb"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wlast"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_wready"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bresp"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_bready"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="ETHERNET_dma_rxs" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="7" NAME="S_AXIS_STS" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_aclk"/> |
| <PORTMAP DIR="O" PHYSICAL="s2mm_sts_reset_out_n"/> |
| <PORTMAP DIR="I" PHYSICAL="axi_resetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tdata"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tkeep"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axis_s2mm_sts_tready"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tlast"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="ETHERNET_dma_txd" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="M_AXIS_MM2S" TYPE="INITIATOR"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="mm2s_prmry_reset_out_n"/> |
| <PORTMAP DIR="I" PHYSICAL="axi_resetn"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tdata"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tkeep"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tvalid"/> |
| <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tready"/> |
| <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tlast"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| <BUSINTERFACE BUSNAME="ETHERNET_dma_rxd" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="5" NAME="S_AXIS_S2MM" TYPE="TARGET"> |
| <PORTMAPS> |
| <PORTMAP DIR="O" PHYSICAL="s2mm_prmry_reset_out_n"/> |
| <PORTMAP DIR="I" PHYSICAL="axi_resetn"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tdata"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tkeep"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tvalid"/> |
| <PORTMAP DIR="O" PHYSICAL="s_axis_s2mm_tready"/> |
| <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tlast"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1105199104" BASENAME="C_BASEADDR" BASEVALUE="0x41e00000" HIGHDECIMAL="1105264639" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41e0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI_LITE"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| <INTERRUPTINFO TYPE="SOURCE"> |
| <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="5"/> |
| <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="6"/> |
| </INTERRUPTINFO> |
| </MODULE> |
| <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="19" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc"> |
| <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION> |
| <DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION> |
| <DOCUMENTATION> |
| <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/> |
| </DOCUMENTATION> |
| <LICENSEINFO ICON_NAME="ps_core_preferred"/> |
| <PARAMETERS> |
| <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/> |
| <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000"/> |
| <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff"/> |
| <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/> |
| <PARAMETER MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="2"/> |
| <PARAMETER MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0xffffffff"/> |
| <PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1"/> |
| <PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"/> |
| <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/> |
| <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/> |
| </PARAMETERS> |
| <PORTS> |
| <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="20" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"> |
| <DESCRIPTION>Interrupt Request Output</DESCRIPTION> |
| </PORT> |
| <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/> |
| <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="1" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt & DIP_Switches_4Bits_IP2INTC_Irpt & Push_Buttons_4Bits_IP2INTC_Irpt & ETHERNET_INTERRUPT & axi_timer_0_Interrupt & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]"> |
| <SIGNALS> |
| <SIGNAL NAME="RS232_Uart_1_Interrupt"/> |
| <SIGNAL NAME="DIP_Switches_4Bits_IP2INTC_Irpt"/> |
| <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/> |
| <SIGNAL NAME="ETHERNET_INTERRUPT"/> |
| <SIGNAL NAME="axi_timer_0_Interrupt"/> |
| <SIGNAL NAME="ETHERNET_dma_mm2s_introut"/> |
| <SIGNAL NAME="ETHERNET_dma_s2mm_introut"/> |
| </SIGNALS> |
| <DESCRIPTION>Interrupt Inputs</DESCRIPTION> |
| </PORT> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/> |
| <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/> |
| </PORTS> |
| <BUSINTERFACES> |
| <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE"> |
| <PORTMAPS> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/> |
| <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/> |
| <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/> |
| </PORTMAPS> |
| </BUSINTERFACE> |
| </BUSINTERFACES> |
| <MEMORYMAP> |
| <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K"> |
| <SLAVES> |
| <SLAVE BUSINTERFACE="S_AXI"/> |
| </SLAVES> |
| </MEMRANGE> |
| </MEMORYMAP> |
| <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER"> |
| <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="0" SIGNAME="RS232_Uart_1_Interrupt"/> |
| <SOURCE INSTANCE="DIP_Switches_4Bits" PRIORITY="1" SIGNAME="DIP_Switches_4Bits_IP2INTC_Irpt"/> |
| <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="2" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/> |
| <SOURCE INSTANCE="ETHERNET" PRIORITY="3" SIGNAME="ETHERNET_INTERRUPT"/> |
| <SOURCE INSTANCE="axi_timer_0" PRIORITY="4" SIGNAME="axi_timer_0_Interrupt"/> |
| <SOURCE INSTANCE="ETHERNET_dma" PRIORITY="5" SIGNAME="ETHERNET_dma_mm2s_introut"/> |
| <SOURCE INSTANCE="ETHERNET_dma" PRIORITY="6" SIGNAME="ETHERNET_dma_s2mm_introut"/> |
| <TARGET INSTANCE="microblaze_0"/> |
| </INTERRUPTINFO> |
| </MODULE> |
| </MODULES> |
| |
| </EDKSYSTEM> |
