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| ;* Copyright (C) 2012 Renesas Electronics Corporation. All rights reserved. | |
| ;*******************************************************************************/ | |
| ;/******************************************************************************* | |
| ;* File Name : vbar_init.s | |
| ;* Version : 0.01 | |
| ;* Device(s) : Aragon | |
| ;* Tool-Chain : DS-5 Ver 5.8 | |
| ;* ARM Complier | |
| ;* : | |
| ;* H/W Platform : Aragon CPU Board | |
| ;* Description : Aragon Sample Program | |
| ;*******************************************************************************/ | |
| ;/******************************************************************************* | |
| ;* History : DD.MM.YYYY Version Description | |
| ;* : 23.05.2012 0.01 | |
| ;*******************************************************************************/ | |
| ;================================================================== | |
| ; This code provides basic global enable for Cortex-A9 cache. | |
| ; It also enables branch prediction | |
| ; This code must be run from a privileged mode | |
| ;================================================================== | |
| AREA INIT_VBAR, CODE, READONLY | |
| IMPORT ||Image$$VECTOR_MIRROR_TABLE$$Base|| | |
| ; IMPORT ||Image$$VECTOR_TABLE$$Base|| | |
| EXPORT VbarInit | |
| VbarInit FUNCTION | |
| ;=================================================================== | |
| ; Set Vector Base Address Register (VBAR) to point to this application's vector table | |
| ;=================================================================== | |
| LDR r0, =||Image$$VECTOR_MIRROR_TABLE$$Base|| | |
| ; LDR r0, =||Image$$VECTOR_TABLE$$Base|| | |
| MCR p15, 0, r0, c12, c0, 0 | |
| ;=================================================================== | |
| ; Set low vectors | |
| ;=================================================================== | |
| MRC p15, 0, r0, c1, c0, 0 ;/* Read CP15 System Control register (SCTLR) */ | |
| BIC r0, r0, #(0x1 << 13) ;/* Clear V bit 13 to set Low Vectors */ | |
| MCR p15, 0, r0, c1, c0, 0 ;/* Write CP15 System Control register */ | |
| ISB | |
| BX lr | |
| ENDFUNC | |
| END |