)]}'
{
  "commit": "da3d370ff7cdcf883e9f3ca3ba1c7c731889c9ed",
  "tree": "3d6437598b7484868a3a510af7f0e0292ba7a5b1",
  "parents": [
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  ],
  "author": {
    "name": "Richard Barry",
    "email": "ribarry@amazon.com",
    "time": "Wed Sep 04 15:46:45 2019 +0000"
  },
  "committer": {
    "name": "Richard Barry",
    "email": "ribarry@amazon.com",
    "time": "Wed Sep 04 15:46:45 2019 +0000"
  },
  "message": "RISC-V port updates:  The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.\n",
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