Update RISC-V IAR port to support vector mode. (#458)
* Update RISC-V IAR port to support vector mode.
* uncrustify
Co-authored-by: David Chalco <david@chalco.io>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>
diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c
index f8a49ac..1e8819d 100644
--- a/portable/IAR/RISC-V/port.c
+++ b/portable/IAR/RISC-V/port.c
@@ -27,8 +27,8 @@
*/
/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RISC-V RV32 port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the RISC-V port.
+*----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
@@ -39,175 +39,203 @@
#include "string.h"
#ifdef configCLINT_BASE_ADDRESS
- #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+ #warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
#endif
#ifndef configMTIME_BASE_ADDRESS
- #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+ #warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
#endif
#ifndef configMTIMECMP_BASE_ADDRESS
- #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+ #warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
#endif
/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
#ifdef configTASK_RETURN_ADDRESS
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
#else
- #define portTASK_RETURN_ADDRESS prvTaskExitError
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
#endif
/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
-to use a statically allocated array as the interrupt stack. Alternative leave
-configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
-linker variable names __freertos_irq_stack_top has the same value as the top
-of the stack used by main. Using the linker script method will repurpose the
-stack that was used by main before the scheduler was started for use as the
-interrupt stack after the scheduler has started. */
+ * to use a statically allocated array as the interrupt stack. Alternative leave
+ * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
+ * linker variable names __freertos_irq_stack_top has the same value as the top
+ * of the stack used by main. Using the linker script method will repurpose the
+ * stack that was used by main before the scheduler was started for use as the
+ * interrupt stack after the scheduler has started. */
#ifdef configISR_STACK_SIZE_WORDS
- static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
- const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
+static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
+const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
- /* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
- the task stacks, and so will legitimately appear in many positions within
- the ISR stack. */
- #define portISR_STACK_FILL_BYTE 0xee
+/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+ * the task stacks, and so will legitimately appear in many positions within
+ * the ISR stack. */
+ #define portISR_STACK_FILL_BYTE 0xee
#else
- extern const uint32_t __freertos_irq_stack_top[];
- const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
+ extern const uint32_t __freertos_irq_stack_top[];
+ const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
#endif
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
* generate the tick interrupt.
*/
-void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
+void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) );
/*-----------------------------------------------------------*/
/* Used to program the machine timer compare register. */
uint64_t ullNextTime = 0ULL;
-const uint64_t *pullNextTime = &ullNextTime;
+const uint64_t * pullNextTime = &ullNextTime;
const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
volatile uint64_t * pullMachineTimerCompareRegister = NULL;
+/* Holds the critical nesting value - deliberately non-zero at start up to
+ * ensure interrupts are not accidentally enabled before the scheduler starts. */
+size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa;
+size_t * pxCriticalNesting = &xCriticalNesting;
+
+/* Used to catch tasks that attempt to return from their implementing function. */
+size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
+
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
-stack checking. A problem in the ISR stack will trigger an assert, not call the
-stack overflow hook function (because the stack overflow hook is specific to a
-task stack, not the ISR stack). */
+ * stack checking. A problem in the ISR stack will trigger an assert, not call
+ * the stack overflow hook function (because the stack overflow hook is specific
+ * to a task stack, not the ISR stack). */
#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
- #warning This path not tested, or even compiled yet.
+ #warning This path not tested, or even compiled yet.
- static const uint8_t ucExpectedStackBytes[] = {
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
- portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
+ static const uint8_t ucExpectedStackBytes[] =
+ {
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
+ portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
+ }; \
- #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
- /* Define the function away. */
- #define portCHECK_ISR_STACK()
+ #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
+ /* Define the function away. */
+ #define portCHECK_ISR_STACK()
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
/*-----------------------------------------------------------*/
-#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
+static void prvTaskExitError( void )
+{
+ volatile uint32_t ulDummy = 0UL;
- void vPortSetupTimerInterrupt( void )
- {
- uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
- volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
- volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS );
- volatile uint32_t ulHartId;
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( xCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
- __asm volatile( "csrr %0, 0xf14" : "=r"( ulHartId ) ); /* 0xf14 is hartid. */
- pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
- do
- {
- ulCurrentTimeHigh = *pulTimeHigh;
- ulCurrentTimeLow = *pulTimeLow;
- } while( ulCurrentTimeHigh != *pulTimeHigh );
+#if ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
- ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
- ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
- ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
- ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
- *pullMachineTimerCompareRegister = ullNextTime;
+ void vPortSetupTimerInterrupt( void )
+ {
+ uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+ volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */
+ volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS );
+ volatile uint32_t ulHartId;
- /* Prepare the time to use after the next tick interrupt. */
- ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
- }
+ __asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is hartid. */
+
+ pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
+
+ do
+ {
+ ulCurrentTimeHigh = *pulTimeHigh;
+ ulCurrentTimeLow = *pulTimeLow;
+ } while( ulCurrentTimeHigh != *pulTimeHigh );
+
+ ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
+ ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
+ ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ *pullMachineTimerCompareRegister = ullNextTime;
+
+ /* Prepare the time to use after the next tick interrupt. */
+ ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+ }
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
/*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void )
{
-extern void xPortStartFirstTask( void );
+ extern void xPortStartFirstTask( void );
- #if( configASSERT_DEFINED == 1 )
- {
- volatile uint32_t mtvec = 0;
+ #if ( configASSERT_DEFINED == 1 )
+ {
+ /* Check alignment of the interrupt stack - which is the same as the
+ * stack that was being used by main() prior to the scheduler being
+ * started. */
+ configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
- /* Check the least significant two bits of mtvec are 00 - indicating
- single vector mode. */
- __asm volatile( "csrr %0, 0x305" : "=r"( mtvec ) ); /* 0x305 is mtvec. */
- configASSERT( ( mtvec & 0x03UL ) == 0 );
+ #ifdef configISR_STACK_SIZE_WORDS
+ {
+ memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+ }
+ #endif /* configISR_STACK_SIZE_WORDS */
+ }
+ #endif /* configASSERT_DEFINED */
- /* Check alignment of the interrupt stack - which is the same as the
- stack that was being used by main() prior to the scheduler being
- started. */
- configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
+ /* If there is a CLINT then it is ok to use the default implementation
+ * in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+ * configure whichever clock is to be used to generate the tick interrupt. */
+ vPortSetupTimerInterrupt();
- #ifdef configISR_STACK_SIZE_WORDS
- {
- memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
- }
- #endif /* configISR_STACK_SIZE_WORDS */
- }
- #endif /* configASSERT_DEFINED */
+ #if ( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
+ {
+ /* Enable mtime and external interrupts. 1<<7 for timer interrupt,
+ * 1<<11 for external interrupt. _RB_ What happens here when mtime is
+ * not present as with pulpino? */
+ __asm volatile ( "csrs 0x304, %0" ::"r" ( 0x880 ) ); /* 0x304 is mie. */
+ }
+ #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
- /* If there is a CLINT then it is ok to use the default implementation
- in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
- configure whichever clock is to be used to generate the tick interrupt. */
- vPortSetupTimerInterrupt();
+ xPortStartFirstTask();
- #if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
- {
- /* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
- for external interrupt. _RB_ What happens here when mtime is not present as
- with pulpino? */
- __asm volatile( "csrs 0x304, %0" :: "r"(0x880) ); /* 0x304 is mie. */
- }
- #else
- {
- /* Enable external interrupts. */
- __asm volatile( "csrs 0x304, %0" :: "r"(0x800) ); /* 304 is mie. */
- }
- #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
-
- xPortStartFirstTask();
-
- /* Should not get here as after calling xPortStartFirstTask() only tasks
- should be executing. */
- return pdFAIL;
+ /* Should not get here as after calling xPortStartFirstTask() only tasks
+ * should be executing. */
+ return pdFAIL;
}
/*-----------------------------------------------------------*/
void vPortEndScheduler( void )
{
- /* Not implemented. */
- for( ;; );
+ /* Not implemented. */
+ for( ; ; )
+ {
+ }
}
-
-
-
-
-
+/*-----------------------------------------------------------*/
diff --git a/portable/IAR/RISC-V/portASM.s b/portable/IAR/RISC-V/portASM.s
index b529e98..1364644 100644
--- a/portable/IAR/RISC-V/portASM.s
+++ b/portable/IAR/RISC-V/portASM.s
@@ -56,43 +56,27 @@
* registers.
*
*/
-#if __riscv_xlen == 64
- #define portWORD_SIZE 8
- #define store_x sd
- #define load_x ld
-#elif __riscv_xlen == 32
- #define store_x sw
- #define load_x lw
- #define portWORD_SIZE 4
-#else
- #error Assembler did not define __riscv_xlen
-#endif
-#include "freertos_risc_v_chip_specific_extensions.h"
+#include "portContext.h"
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
definitions. */
#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
- #error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+ #error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifdef portasmHAS_CLINT
- #warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
- #define portasmHAS_MTIME portasmHAS_CLINT
- #define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
+ #warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+ #define portasmHAS_MTIME portasmHAS_CLINT
+ #define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
#endif
#ifndef portasmHAS_MTIME
- #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+ #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif
-#ifndef portasmHANDLE_INTERRUPT
- #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file. https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
-#endif
-
-
#ifndef portasmHAS_SIFIVE_CLINT
- #define portasmHAS_SIFIVE_CLINT 0
+ #define portasmHAS_SIFIVE_CLINT 0
#endif
/* CSR definitions. */
@@ -101,260 +85,60 @@
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
-
-/* Only the standard core registers are stored by default. Any additional
-registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
-portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
-specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
-at the top of this file. */
-#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
-
PUBLIC xPortStartFirstTask
- PUBLIC freertos_risc_v_trap_handler
PUBLIC pxPortInitialiseStack
- EXTERN pxCurrentTCB
- EXTERN ulPortTrapHandler
+ PUBLIC freertos_risc_v_trap_handler
+ PUBLIC freertos_risc_v_exception_handler
+ PUBLIC freertos_risc_v_interrupt_handler
+ PUBLIC freertos_risc_v_mtimer_interrupt_handler
+
EXTERN vTaskSwitchContext
EXTERN xTaskIncrementTick
- EXTERN Timer_IRQHandler
EXTERN pullMachineTimerCompareRegister
EXTERN pullNextTime
EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
- EXTERN xISRStackTop
- EXTERN portasmHANDLE_INTERRUPT
+ EXTERN xTaskReturnAddress
+ PUBWEAK freertos_risc_v_application_exception_handler
+ PUBWEAK freertos_risc_v_application_interrupt_handler
/*-----------------------------------------------------------*/
SECTION `.text`:CODE:NOROOT(2)
CODE
-freertos_risc_v_trap_handler:
- addi sp, sp, -portCONTEXT_SIZE
- store_x x1, 1 * portWORD_SIZE( sp )
- store_x x5, 2 * portWORD_SIZE( sp )
- store_x x6, 3 * portWORD_SIZE( sp )
- store_x x7, 4 * portWORD_SIZE( sp )
- store_x x8, 5 * portWORD_SIZE( sp )
- store_x x9, 6 * portWORD_SIZE( sp )
- store_x x10, 7 * portWORD_SIZE( sp )
- store_x x11, 8 * portWORD_SIZE( sp )
- store_x x12, 9 * portWORD_SIZE( sp )
- store_x x13, 10 * portWORD_SIZE( sp )
- store_x x14, 11 * portWORD_SIZE( sp )
- store_x x15, 12 * portWORD_SIZE( sp )
- store_x x16, 13 * portWORD_SIZE( sp )
- store_x x17, 14 * portWORD_SIZE( sp )
- store_x x18, 15 * portWORD_SIZE( sp )
- store_x x19, 16 * portWORD_SIZE( sp )
- store_x x20, 17 * portWORD_SIZE( sp )
- store_x x21, 18 * portWORD_SIZE( sp )
- store_x x22, 19 * portWORD_SIZE( sp )
- store_x x23, 20 * portWORD_SIZE( sp )
- store_x x24, 21 * portWORD_SIZE( sp )
- store_x x25, 22 * portWORD_SIZE( sp )
- store_x x26, 23 * portWORD_SIZE( sp )
- store_x x27, 24 * portWORD_SIZE( sp )
- store_x x28, 25 * portWORD_SIZE( sp )
- store_x x29, 26 * portWORD_SIZE( sp )
- store_x x30, 27 * portWORD_SIZE( sp )
- store_x x31, 28 * portWORD_SIZE( sp )
+portUPDATE_MTIMER_COMPARE_REGISTER MACRO
+ load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
+ load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
- csrr t0, CSR_MSTATUS /* Required for MPIE bit. */
- store_x t0, 29 * portWORD_SIZE( sp )
+ #if( __riscv_xlen == 32 )
- portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+ /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
+ li t4, -1
+ lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
+ lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
+ sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */
+ sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
+ sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
+ lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+ add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
+ sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
+ add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
+ sw t4, 0(t1) /* Store new low word of ullNextTime. */
+ sw t6, 4(t1) /* Store new high word of ullNextTime. */
- load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
- store_x sp, 0( t0 ) /* Write sp to first TCB member. */
+ #endif /* __riscv_xlen == 32 */
- csrr a0, CSR_MCAUSE
- csrr a1, CSR_MEPC
+ #if( __riscv_xlen == 64 )
-test_if_asynchronous:
- srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
- beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
- store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */
+ /* Update the 64-bit mtimer compare match value. */
+ ld t2, 0(t1) /* Load ullNextTime into t2. */
+ sd t2, 0(t0) /* Store ullNextTime into compare register. */
+ ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+ add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
+ sd t4, 0(t1) /* Store ullNextTime. */
-handle_asynchronous:
-
-#if( portasmHAS_MTIME != 0 )
-
- test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
-
- addi t0, x0, 1
-
- slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
- addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
- bne a0, t1, test_if_external_interrupt
-
- load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
- load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
-
- #if( __riscv_xlen == 32 )
-
- /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
- li t4, -1
- lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
- lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
- sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */
- sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
- sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
- lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
- add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
- sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
- add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
- sw t4, 0(t1) /* Store new low word of ullNextTime. */
- sw t6, 4(t1) /* Store new high word of ullNextTime. */
-
- #endif /* __riscv_xlen == 32 */
-
- #if( __riscv_xlen == 64 )
-
- /* Update the 64-bit mtimer compare match value. */
- ld t2, 0(t1) /* Load ullNextTime into t2. */
- sd t2, 0(t0) /* Store ullNextTime into compare register. */
- ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
- add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
- sd t4, 0(t1) /* Store ullNextTime. */
-
- #endif /* __riscv_xlen == 64 */
-
- load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
- jal xTaskIncrementTick
- beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
- jal vTaskSwitchContext
- j processed_source
-
- test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
- addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
- bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
-
-#endif /* portasmHAS_MTIME */
-
- load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
- jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
- j processed_source
-
-handle_synchronous:
- addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
- store_x a1, 0( sp ) /* Save updated exception return address. */
-
-test_if_environment_call:
- li t0, 11 /* 11 == environment call. */
- bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
- load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
- jal vTaskSwitchContext
- j processed_source
-
-is_exception:
- csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
- csrr t1, CSR_MEPC /* For viewing in the debugger only */
- csrr t2, CSR_MSTATUS
- j is_exception /* No other exceptions handled yet. */
-
-as_yet_unhandled:
- csrr t0, mcause /* For viewing in the debugger only. */
- j as_yet_unhandled
-
-processed_source:
- load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
- load_x sp, 0( t1 ) /* Read sp from first TCB member. */
-
- /* Load mret with the address of the next instruction in the task to run next. */
- load_x t0, 0( sp )
- csrw CSR_MEPC, t0
-
- portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
-
- /* Load mstatus with the interrupt enable bits used by the task. */
- load_x t0, 29 * portWORD_SIZE( sp )
- csrw CSR_MSTATUS, t0 /* Required for MPIE bit. */
-
- load_x x1, 1 * portWORD_SIZE( sp )
- load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
- load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
- load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
- load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
- load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
- load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
- load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
- load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
- load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
- load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
- load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
- load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
- load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
- load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
- load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
- load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
- load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
- load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
- load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
- load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
- load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
- load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
- load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
- load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
- load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
- load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
- load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
- addi sp, sp, portCONTEXT_SIZE
-
- mret
-
-/*-----------------------------------------------------------*/
-
-xPortStartFirstTask:
-
-#if( portasmHAS_SIFIVE_CLINT != 0 )
- /* If there is a clint then interrupts can branch directly to the FreeRTOS
- trap handler. Otherwise the interrupt controller will need to be configured
- outside of this file. */
- la t0, freertos_risc_v_trap_handler
- csrw CSR_MTVEC, t0
-#endif /* portasmHAS_CLILNT */
-
- load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
- load_x sp, 0( sp ) /* Read sp from first TCB member. */
-
- load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
-
- portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
-
- load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
- load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
- load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
- load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
- load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
- load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
- load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
- load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
- load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
- load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
- load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
- load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
- load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
- load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
- load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
- load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
- load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
- load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
- load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
- load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
- load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
- load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
- load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
- load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
- load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
- load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
-
- load_x x5, 29 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0) */
- addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
- csrrw x0, CSR_MSTATUS, x5 /* Interrupts enabled from here! */
- load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
- addi sp, sp, portCONTEXT_SIZE
- ret
-
+ #endif /* __riscv_xlen == 64 */
+ ENDM
/*-----------------------------------------------------------*/
/*
@@ -369,25 +153,26 @@
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
*
- * Register ABI Name Description Saver
- * x0 zero Hard-wired zero -
- * x1 ra Return address Caller
- * x2 sp Stack pointer Callee
- * x3 gp Global pointer -
- * x4 tp Thread pointer -
- * x5-7 t0-2 Temporaries Caller
- * x8 s0/fp Saved register/Frame pointer Callee
- * x9 s1 Saved register Callee
- * x10-11 a0-1 Function Arguments/return values Caller
- * x12-17 a2-7 Function arguments Caller
- * x18-27 s2-11 Saved registers Callee
- * x28-31 t3-6 Temporaries Caller
+ * Register ABI Name Description Saver
+ * x0 zero Hard-wired zero -
+ * x1 ra Return address Caller
+ * x2 sp Stack pointer Callee
+ * x3 gp Global pointer -
+ * x4 tp Thread pointer -
+ * x5-7 t0-2 Temporaries Caller
+ * x8 s0/fp Saved register/Frame pointer Callee
+ * x9 s1 Saved register Callee
+ * x10-11 a0-1 Function Arguments/return values Caller
+ * x12-17 a2-7 Function arguments Caller
+ * x18-27 s2-11 Saved registers Callee
+ * x28-31 t3-6 Temporaries Caller
*
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
* where the global and thread pointers are currently assumed to be constant so
* are not saved:
*
* mstatus
+ * xCriticalNesting
* x31
* x30
* x29
@@ -420,29 +205,189 @@
* pxCode
*/
pxPortInitialiseStack:
+ csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */
+ andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
+ addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
+ slli t1, t1, 4
+ or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
- csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */
- andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
- addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
- slli t1, t1, 4
- or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
-
- addi a0, a0, -portWORD_SIZE
- store_x t0, 0(a0) /* mstatus onto the stack. */
- addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
- store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
- addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
- store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
- addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
-chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
- beq t0, x0, no_more_regs /* No more chip specific registers to save. */
- addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
- store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
- addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
- j chip_specific_stack_frame /* Until no more chip specific registers. */
+ addi a0, a0, -portWORD_SIZE
+ store_x t0, 0(a0) /* mstatus onto the stack. */
+ addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
+ store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
+ addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
+ store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
+ addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
+ load_x t0, xTaskReturnAddress
+ store_x t0, 0(a0) /* Return address onto the stack. */
+ addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
+chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
+ beq t0, x0, no_more_regs /* No more chip specific registers to save. */
+ addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
+ store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
+ addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
+ j chip_specific_stack_frame /* Until no more chip specific registers. */
no_more_regs:
- addi a0, a0, -portWORD_SIZE
- store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
- ret
+ addi a0, a0, -portWORD_SIZE
+ store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
+ ret
+/*-----------------------------------------------------------*/
+xPortStartFirstTask:
+ load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
+ load_x sp, 0( sp ) /* Read sp from first TCB member. */
+
+ load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
+
+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+ load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
+ load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
+ load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
+ load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
+ load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
+ load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
+ load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
+ load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
+ load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
+ load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
+ load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
+ load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
+ load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
+ load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
+ load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
+ load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
+ load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
+ load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
+ load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
+ load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
+ load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
+ load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
+ load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
+ load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
+ load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
+
+ load_x x5, 29 * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
+ load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */
+ store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
+
+ load_x x5, 30 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
+ addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
+ csrrw x0, CSR_MSTATUS, x5 /* Interrupts enabled from here! */
+
+ load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
+ load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */
+
+ addi sp, sp, portCONTEXT_SIZE
+ ret
+/*-----------------------------------------------------------*/
+
+freertos_risc_v_application_exception_handler:
+ csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
+ csrr t1, CSR_MEPC /* For viewing in the debugger only */
+ csrr t2, CSR_MSTATUS /* For viewing in the debugger only */
+ j $
+/*-----------------------------------------------------------*/
+
+freertos_risc_v_application_interrupt_handler:
+ csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
+ csrr t1, CSR_MEPC /* For viewing in the debugger only */
+ csrr t2, CSR_MSTATUS /* For viewing in the debugger only */
+ j $
+/*-----------------------------------------------------------*/
+
+ SECTION `.text.freertos_risc_v_exception_handler`:CODE:NOROOT(2)
+ CODE
+
+freertos_risc_v_exception_handler:
+ portcontextSAVE_EXCEPTION_CONTEXT
+ /* a0 now contains mcause. */
+ li t0, 11 /* 11 == environment call. */
+ bne a0, t0, other_exception /* Not an M environment call, so some other exception. */
+ call vTaskSwitchContext
+ portcontextRESTORE_CONTEXT
+
+other_exception:
+ call freertos_risc_v_application_exception_handler
+ portcontextRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+ SECTION `.text.freertos_risc_v_interrupt_handler`:CODE:NOROOT(2)
+ CODE
+
+freertos_risc_v_interrupt_handler:
+ portcontextSAVE_INTERRUPT_CONTEXT
+ call freertos_risc_v_application_interrupt_handler
+ portcontextRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+ SECTION `.text.freertos_risc_v_mtimer_interrupt_handler`:CODE:NOROOT(2)
+ CODE
+
+freertos_risc_v_mtimer_interrupt_handler:
+ portcontextSAVE_INTERRUPT_CONTEXT
+ portUPDATE_MTIMER_COMPARE_REGISTER
+ call xTaskIncrementTick
+ beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */
+ call vTaskSwitchContext
+exit_without_context_switch:
+ portcontextRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+ SECTION `.text.freertos_risc_v_trap_handler`:CODE:NOROOT(8)
+ CODE
+
+freertos_risc_v_trap_handler:
+ portcontextSAVE_CONTEXT_INTERNAL
+
+ csrr a0, CSR_MCAUSE
+ csrr a1, CSR_MEPC
+
+ bge a0, x0, synchronous_exception
+
+asynchronous_interrupt:
+ store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
+ load_x sp, xISRStackTop /* Switch to ISR stack. */
+ j handle_interrupt
+
+synchronous_exception:
+ addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */
+ store_x a1, 0( sp ) /* Save updated exception return address. */
+ load_x sp, xISRStackTop /* Switch to ISR stack. */
+ j handle_exception
+
+handle_interrupt:
+#if( portasmHAS_MTIME != 0 )
+
+ test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
+ addi t0, x0, 1
+ slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
+ addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
+ bne a0, t1, application_interrupt_handler
+
+ portUPDATE_MTIMER_COMPARE_REGISTER
+ call xTaskIncrementTick
+ beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
+ call vTaskSwitchContext
+ j processed_source
+
+#endif /* portasmHAS_MTIME */
+
+application_interrupt_handler:
+ call freertos_risc_v_application_interrupt_handler
+ j processed_source
+
+handle_exception:
+ /* a0 contains mcause. */
+ li t0, 11 /* 11 == environment call. */
+ bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */
+ call vTaskSwitchContext
+ j processed_source
+
+application_exception_handler:
+ call freertos_risc_v_application_exception_handler
+ j processed_source /* No other exceptions handled yet. */
+
+processed_source:
+ portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
diff --git a/portable/IAR/RISC-V/portContext.h b/portable/IAR/RISC-V/portContext.h
new file mode 100644
index 0000000..8b883c8
--- /dev/null
+++ b/portable/IAR/RISC-V/portContext.h
@@ -0,0 +1,177 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTCONTEXT_H
+#define PORTCONTEXT_H
+
+#if __riscv_xlen == 64
+ #define portWORD_SIZE 8
+ #define store_x sd
+ #define load_x ld
+#elif __riscv_xlen == 32
+ #define store_x sw
+ #define load_x lw
+ #define portWORD_SIZE 4
+#else
+ #error Assembler did not define __riscv_xlen
+#endif
+
+#include "freertos_risc_v_chip_specific_extensions.h"
+
+/* Only the standard core registers are stored by default. Any additional
+ * registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
+ * portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
+ * specific version of freertos_risc_v_chip_specific_extensions.h. See the
+ * notes at the top of portASM.S file. */
+#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
+
+ EXTERN pxCurrentTCB
+ EXTERN xISRStackTop
+ EXTERN xCriticalNesting
+ EXTERN pxCriticalNesting
+
+/*-----------------------------------------------------------*/
+
+portcontextSAVE_CONTEXT_INTERNAL MACRO
+ addi sp, sp, -portCONTEXT_SIZE
+ store_x x1, 1 * portWORD_SIZE( sp )
+ store_x x5, 2 * portWORD_SIZE( sp )
+ store_x x6, 3 * portWORD_SIZE( sp )
+ store_x x7, 4 * portWORD_SIZE( sp )
+ store_x x8, 5 * portWORD_SIZE( sp )
+ store_x x9, 6 * portWORD_SIZE( sp )
+ store_x x10, 7 * portWORD_SIZE( sp )
+ store_x x11, 8 * portWORD_SIZE( sp )
+ store_x x12, 9 * portWORD_SIZE( sp )
+ store_x x13, 10 * portWORD_SIZE( sp )
+ store_x x14, 11 * portWORD_SIZE( sp )
+ store_x x15, 12 * portWORD_SIZE( sp )
+ store_x x16, 13 * portWORD_SIZE( sp )
+ store_x x17, 14 * portWORD_SIZE( sp )
+ store_x x18, 15 * portWORD_SIZE( sp )
+ store_x x19, 16 * portWORD_SIZE( sp )
+ store_x x20, 17 * portWORD_SIZE( sp )
+ store_x x21, 18 * portWORD_SIZE( sp )
+ store_x x22, 19 * portWORD_SIZE( sp )
+ store_x x23, 20 * portWORD_SIZE( sp )
+ store_x x24, 21 * portWORD_SIZE( sp )
+ store_x x25, 22 * portWORD_SIZE( sp )
+ store_x x26, 23 * portWORD_SIZE( sp )
+ store_x x27, 24 * portWORD_SIZE( sp )
+ store_x x28, 25 * portWORD_SIZE( sp )
+ store_x x29, 26 * portWORD_SIZE( sp )
+ store_x x30, 27 * portWORD_SIZE( sp )
+ store_x x31, 28 * portWORD_SIZE( sp )
+
+ load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
+ store_x t0, 29 * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
+
+ csrr t0, mstatus /* Required for MPIE bit. */
+ store_x t0, 30 * portWORD_SIZE( sp )
+
+ portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+
+ load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
+ store_x sp, 0( t0 ) /* Write sp to first TCB member. */
+
+ ENDM
+/*-----------------------------------------------------------*/
+
+portcontextSAVE_EXCEPTION_CONTEXT MACRO
+ portcontextSAVE_CONTEXT_INTERNAL
+ csrr a0, mcause
+ csrr a1, mepc
+ addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
+ store_x a1, 0( sp ) /* Save updated exception return address. */
+ load_x sp, xISRStackTop /* Switch to ISR stack. */
+ ENDM
+/*-----------------------------------------------------------*/
+
+portcontextSAVE_INTERRUPT_CONTEXT MACRO
+ portcontextSAVE_CONTEXT_INTERNAL
+ csrr a0, mcause
+ csrr a1, mepc
+ store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
+ load_x sp, xISRStackTop /* Switch to ISR stack. */
+ ENDM
+/*-----------------------------------------------------------*/
+
+portcontextRESTORE_CONTEXT MACRO
+ load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
+ load_x sp, 0( t1 ) /* Read sp from first TCB member. */
+
+ /* Load mepc with the address of the instruction in the task to run next. */
+ load_x t0, 0( sp )
+ csrw mepc, t0
+
+ /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+ portasmRESTORE_ADDITIONAL_REGISTERS
+
+ /* Load mstatus with the interrupt enable bits used by the task. */
+ load_x t0, 30 * portWORD_SIZE( sp )
+ csrw mstatus, t0 /* Required for MPIE bit. */
+
+ load_x t0, 29 * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
+ load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
+ store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */
+
+ load_x x1, 1 * portWORD_SIZE( sp )
+ load_x x5, 2 * portWORD_SIZE( sp )
+ load_x x6, 3 * portWORD_SIZE( sp )
+ load_x x7, 4 * portWORD_SIZE( sp )
+ load_x x8, 5 * portWORD_SIZE( sp )
+ load_x x9, 6 * portWORD_SIZE( sp )
+ load_x x10, 7 * portWORD_SIZE( sp )
+ load_x x11, 8 * portWORD_SIZE( sp )
+ load_x x12, 9 * portWORD_SIZE( sp )
+ load_x x13, 10 * portWORD_SIZE( sp )
+ load_x x14, 11 * portWORD_SIZE( sp )
+ load_x x15, 12 * portWORD_SIZE( sp )
+ load_x x16, 13 * portWORD_SIZE( sp )
+ load_x x17, 14 * portWORD_SIZE( sp )
+ load_x x18, 15 * portWORD_SIZE( sp )
+ load_x x19, 16 * portWORD_SIZE( sp )
+ load_x x20, 17 * portWORD_SIZE( sp )
+ load_x x21, 18 * portWORD_SIZE( sp )
+ load_x x22, 19 * portWORD_SIZE( sp )
+ load_x x23, 20 * portWORD_SIZE( sp )
+ load_x x24, 21 * portWORD_SIZE( sp )
+ load_x x25, 22 * portWORD_SIZE( sp )
+ load_x x26, 23 * portWORD_SIZE( sp )
+ load_x x27, 24 * portWORD_SIZE( sp )
+ load_x x28, 25 * portWORD_SIZE( sp )
+ load_x x29, 26 * portWORD_SIZE( sp )
+ load_x x30, 27 * portWORD_SIZE( sp )
+ load_x x31, 28 * portWORD_SIZE( sp )
+ addi sp, sp, portCONTEXT_SIZE
+
+ mret
+ ENDM
+/*-----------------------------------------------------------*/
+
+#endif /* PORTCONTEXT_H */
diff --git a/portable/IAR/RISC-V/portmacro.h b/portable/IAR/RISC-V/portmacro.h
index aac3090..50e03e2 100644
--- a/portable/IAR/RISC-V/portmacro.h
+++ b/portable/IAR/RISC-V/portmacro.h
@@ -48,50 +48,43 @@
/* Type definitions. */
#if __riscv_xlen == 64
- #define portSTACK_TYPE uint64_t
- #define portBASE_TYPE int64_t
- #define portUBASE_TYPE uint64_t
- #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
- #define portPOINTER_SIZE_TYPE uint64_t
+ #define portSTACK_TYPE uint64_t
+ #define portBASE_TYPE int64_t
+ #define portUBASE_TYPE uint64_t
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
+ #define portPOINTER_SIZE_TYPE uint64_t
#elif __riscv_xlen == 32
- #define portSTACK_TYPE uint32_t
- #define portBASE_TYPE int32_t
- #define portUBASE_TYPE uint32_t
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+ #define portSTACK_TYPE uint32_t
+ #define portBASE_TYPE int32_t
+ #define portUBASE_TYPE uint32_t
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
#else
- #error Assembler did not define __riscv_xlen
+ #error Assembler did not define __riscv_xlen
#endif
-
typedef portSTACK_TYPE StackType_t;
typedef portBASE_TYPE BaseType_t;
typedef portUBASE_TYPE UBaseType_t;
typedef portUBASE_TYPE TickType_t;
/* Legacy type definitions. */
-#define portCHAR char
-#define portFLOAT float
-#define portDOUBLE double
-#define portLONG long
-#define portSHORT short
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
+ * not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/*-----------------------------------------------------------*/
/* Architecture specifics. */
-#define portSTACK_GROWTH ( -1 )
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#ifdef __riscv64
- #error This is the RV32 port that has not yet been adapted for 64.
- #define portBYTE_ALIGNMENT 16
-#else
- #define portBYTE_ALIGNMENT 16
-#endif
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 16
/*-----------------------------------------------------------*/
-
/* Scheduler utilities. */
extern void vTaskSwitchContext( void );
#define portYIELD() __asm volatile( "ecall" );
@@ -99,18 +92,30 @@
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
-
/* Critical section management. */
-#define portCRITICAL_NESTING_IN_TCB 1
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB 0
-#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+
#define portDISABLE_INTERRUPTS() __disable_interrupt()
#define portENABLE_INTERRUPTS() __enable_interrupt()
-#define portENTER_CRITICAL() vTaskEnterCritical()
-#define portEXIT_CRITICAL() vTaskExitCritical()
+
+extern size_t xCriticalNesting;
+#define portENTER_CRITICAL() \
+{ \
+ portDISABLE_INTERRUPTS(); \
+ xCriticalNesting++; \
+}
+
+#define portEXIT_CRITICAL() \
+{ \
+ xCriticalNesting--; \
+ if( xCriticalNesting == 0 ) \
+ { \
+ portENABLE_INTERRUPTS(); \
+ } \
+}
/*-----------------------------------------------------------*/
@@ -124,55 +129,51 @@
/*-----------------------------------------------------------*/
-/* Task function macros as described on the FreeRTOS.org WEB site. These are
-not necessary for to use this port. They are defined so the common demo files
-(which build with all the ports) will build. */
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+ * not necessary for to use this port. They are defined so the common demo
+ * files (which build with all the ports) will build. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/*-----------------------------------------------------------*/
-#define portNOP() __asm volatile ( " nop " )
-
-#define portINLINE __inline
+#define portNOP() __asm volatile( " nop " )
+#define portINLINE __inline
#ifndef portFORCE_INLINE
- #define portFORCE_INLINE inline __attribute__(( always_inline))
+ #define portFORCE_INLINE inline __attribute__(( always_inline))
#endif
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
+/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
-the source code because to do so would cause other compilers to generate
-warnings. */
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
#pragma diag_suppress=Pa082
/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
-configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
-backward compatibility derive the newer definitions from the old if the old
-definition is found. */
+ * configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
+ * backward compatibility derive the newer definitions from the old if the old
+ * definition is found. */
#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
- /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
- there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
- addresses to 0. */
- #define configMTIME_BASE_ADDRESS ( 0 )
- #define configMTIMECMP_BASE_ADDRESS ( 0 )
+ /* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
+ * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
+ * addresses to 0. */
+ #define configMTIME_BASE_ADDRESS ( 0 )
+ #define configMTIMECMP_BASE_ADDRESS ( 0 )
#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
- /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
- the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
- from the CLINT address. */
- #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
- #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
+ /* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
+ * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
+ * from the CLINT address. */
+ #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
+ #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
- #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+ #error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif
-
-
#ifdef __cplusplus
}
#endif
#endif /* PORTMACRO_H */
-
