<?xml version="1.0"?>
<Project Version="1" Minor="1">
	<TOOL_VERSION Version="2015.1"/>
	<MODE Name="Pre-Synthesis"/>
	<SYSTEMINFO BOARD="xilinx.com:vc707:1.2" PART="" ARCH="virtex7" PACKAGE="ffg1761" DEVICE="7vx485t" SPEED="-2"/>
	<HIERARCHY Name="design_1_wrapper"/>
	<File Type="HW_HANDOFF" Name="design_1.hwh" DESIGN_HIERARCHY="design_1_i" BD_TYPE="DEFAULT_BD"/>
	<File Type="BD_TCL" Name="design_1_bd.tcl"/>
	<USEDRESOURCES/>
</Project>