| /* |
| * FreeRTOS Kernel <DEVELOPMENT BRANCH> |
| * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. |
| * |
| * SPDX-License-Identifier: MIT |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a copy of |
| * this software and associated documentation files (the "Software"), to deal in |
| * the Software without restriction, including without limitation the rights to |
| * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of |
| * the Software, and to permit persons to whom the Software is furnished to do so, |
| * subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in all |
| * copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS |
| * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR |
| * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER |
| * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * https://www.FreeRTOS.org |
| * https://github.com/FreeRTOS |
| * |
| */ |
| |
| #ifndef PORTMACRO_H |
| #define PORTMACRO_H |
| |
| /* *INDENT-OFF* */ |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| /* *INDENT-ON* */ |
| |
| /*----------------------------------------------------------- |
| * Port specific definitions. |
| * |
| * The settings in this file configure FreeRTOS correctly for the |
| * given hardware and compiler. |
| * |
| * These settings should not be altered. |
| *----------------------------------------------------------- |
| */ |
| |
| /* Type definitions. */ |
| #define portCHAR char |
| #define portFLOAT float |
| #define portDOUBLE double |
| #define portLONG long |
| #define portSHORT short |
| #define portSTACK_TYPE uint32_t |
| #define portBASE_TYPE portLONG |
| |
| typedef portSTACK_TYPE StackType_t; |
| typedef long BaseType_t; |
| typedef unsigned long UBaseType_t; |
| |
| #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) |
| typedef uint16_t TickType_t; |
| #define portMAX_DELAY ( TickType_t ) 0xffff |
| #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) |
| typedef uint32_t TickType_t; |
| #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) |
| #else |
| #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. |
| #endif |
| /*-----------------------------------------------------------*/ |
| |
| /* Architecture specifics. */ |
| #define portSTACK_GROWTH ( -1 ) |
| #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) |
| #define portBYTE_ALIGNMENT 8 |
| #define portNOP() __asm volatile ( "NOP" ); |
| /*-----------------------------------------------------------*/ |
| |
| |
| /* Scheduler utilities. */ |
| |
| /* |
| * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR |
| * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but |
| * are included here for efficiency. An attempt to call one from |
| * THUMB mode code will result in a compile time error. |
| */ |
| |
| #define portRESTORE_CONTEXT() \ |
| { \ |
| extern volatile void * volatile pxCurrentTCB; \ |
| extern volatile uint32_t ulCriticalNesting; \ |
| \ |
| /* Set the LR to the task stack. */ \ |
| __asm volatile ( \ |
| "LDR R0, =pxCurrentTCB \n\t" \ |
| "LDR R0, [R0] \n\t" \ |
| "LDR LR, [R0] \n\t" \ |
| \ |
| /* The critical nesting depth is the first item on the stack. */ \ |
| /* Load it into the ulCriticalNesting variable. */ \ |
| "LDR R0, =ulCriticalNesting \n\t" \ |
| "LDMFD LR!, {R1} \n\t" \ |
| "STR R1, [R0] \n\t" \ |
| \ |
| /* Get the SPSR from the stack. */ \ |
| "LDMFD LR!, {R0} \n\t" \ |
| "MSR SPSR, R0 \n\t" \ |
| \ |
| /* Restore all system mode registers for the task. */ \ |
| "LDMFD LR, {R0-R14}^ \n\t" \ |
| "NOP \n\t" \ |
| \ |
| /* Restore the return address. */ \ |
| "LDR LR, [LR, #+60] \n\t" \ |
| \ |
| /* And return - correcting the offset in the LR to obtain the */ \ |
| /* correct address. */ \ |
| "SUBS PC, LR, #4 \n\t" \ |
| ); \ |
| ( void ) ulCriticalNesting; \ |
| ( void ) pxCurrentTCB; \ |
| } |
| /*-----------------------------------------------------------*/ |
| |
| #define portSAVE_CONTEXT() \ |
| { \ |
| extern volatile void * volatile pxCurrentTCB; \ |
| extern volatile uint32_t ulCriticalNesting; \ |
| \ |
| /* Push R0 as we are going to use the register. */ \ |
| __asm volatile ( \ |
| "STMDB SP!, {R0} \n\t" \ |
| \ |
| /* Set R0 to point to the task stack pointer. */ \ |
| "STMDB SP,{SP}^ \n\t" \ |
| "NOP \n\t" \ |
| "SUB SP, SP, #4 \n\t" \ |
| "LDMIA SP!,{R0} \n\t" \ |
| \ |
| /* Push the return address onto the stack. */ \ |
| "STMDB R0!, {LR} \n\t" \ |
| \ |
| /* Now we have saved LR we can use it instead of R0. */ \ |
| "MOV LR, R0 \n\t" \ |
| \ |
| /* Pop R0 so we can save it onto the system mode stack. */ \ |
| "LDMIA SP!, {R0} \n\t" \ |
| \ |
| /* Push all the system mode registers onto the task stack. */ \ |
| "STMDB LR,{R0-LR}^ \n\t" \ |
| "NOP \n\t" \ |
| "SUB LR, LR, #60 \n\t" \ |
| \ |
| /* Push the SPSR onto the task stack. */ \ |
| "MRS R0, SPSR \n\t" \ |
| "STMDB LR!, {R0} \n\t" \ |
| \ |
| "LDR R0, =ulCriticalNesting \n\t" \ |
| "LDR R0, [R0] \n\t" \ |
| "STMDB LR!, {R0} \n\t" \ |
| \ |
| /* Store the new top of stack for the task. */ \ |
| "LDR R0, =pxCurrentTCB \n\t" \ |
| "LDR R0, [R0] \n\t" \ |
| "STR LR, [R0] \n\t" \ |
| ); \ |
| ( void ) ulCriticalNesting; \ |
| ( void ) pxCurrentTCB; \ |
| } |
| |
| extern void vTaskSwitchContext( void ); |
| #define portYIELD_FROM_ISR() vTaskSwitchContext() |
| #define portYIELD() __asm volatile ( "SWI 0" ) |
| /*-----------------------------------------------------------*/ |
| |
| |
| /* Critical section management. */ |
| |
| /* |
| * The interrupt management utilities can only be called from ARM mode. When |
| * THUMB_INTERWORK is defined the utilities are defined as functions in |
| * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not |
| * defined then the utilities are defined as macros here - as per other ports. |
| */ |
| |
| #ifdef THUMB_INTERWORK |
| |
| extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); |
| extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); |
| |
| #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() |
| #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() |
| |
| #else |
| |
| #define portDISABLE_INTERRUPTS() \ |
| __asm volatile ( \ |
| "STMDB SP!, {R0} \n\t" /* Push R0. */ \ |
| "MRS R0, CPSR \n\t" /* Get CPSR. */ \ |
| "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ |
| "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ |
| "LDMIA SP!, {R0} " ) /* Pop R0. */ |
| |
| #define portENABLE_INTERRUPTS() \ |
| __asm volatile ( \ |
| "STMDB SP!, {R0} \n\t" /* Push R0. */ \ |
| "MRS R0, CPSR \n\t" /* Get CPSR. */ \ |
| "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ |
| "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ |
| "LDMIA SP!, {R0} " ) /* Pop R0. */ |
| |
| #endif /* THUMB_INTERWORK */ |
| |
| extern void vPortEnterCritical( void ); |
| extern void vPortExitCritical( void ); |
| |
| #define portENTER_CRITICAL() vPortEnterCritical(); |
| #define portEXIT_CRITICAL() vPortExitCritical(); |
| /*-----------------------------------------------------------*/ |
| |
| /* Task function macros as described on the FreeRTOS.org WEB site. */ |
| #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) |
| #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) |
| |
| /* *INDENT-OFF* */ |
| #ifdef __cplusplus |
| } |
| #endif |
| /* *INDENT-ON* */ |
| |
| #endif /* PORTMACRO_H */ |
