ast10x0: add I3C peripheral driver (port of aspeed-rust i3c)

Port the AST1060 I3C controller/target driver from aspeed-rust
(src/i3c @ ce3b567) into the ast10x0_peripherals crate, mirroring the
existing I2C port and following the pac-design-patterns conventions.

Driver (peripherals/i3c/): ccc, config, constants, controller, error,
hardware, ibi, mod, types. hal_impl is folded into controller as
inherent methods (proposed_traits is unavailable in openprot and
embedded-hal has no I3C trait).

Design-pattern conformance:
- Confined-`unsafe` MMIO facade: raw `*const` register pointers, a single
  `unsafe fn new`, private `&'static` derefs, `!Sync`; no unsafe or PAC
  types leak above the facade.
- Cooperative-yield bounded poll: an injected `Y: FnMut(u32)` yield
  closure replaces embedded-hal DelayNs, type-erased at the poll loops.
- Borrow-arbitrated exclusivity for per-call state; the global IBI/IRQ
  plane is kept (documented delta) since an ISR cannot borrow a
  stack-owned device.

Notable deltas: drop the Logger generic and the `#[no_mangle]` ISR
symbol exports (kernel owns the vector and calls dispatch_i3c_irq);
heapless 0.9 SPSC with edition-2024 `addr_of_mut!`; reachable
transfer/clock paths hardened to be panic-free (no_panics_test) without
changing success-path behavior.

Also: add scu pinctrl groups (PINCTRL_I3C0..3 / PINCTRL_HVI3C0..3, the
HV groups clearing the conflicting LV pad bits); wire critical-section
and cortex-m `critical-section-single-core` into the crate universe; add
i3c_init and i3c_irq tests, the latter a faithful controller/target IBI
pair mirroring aspeed-rust tests-hw on I3C2 HV.

See target/ast10x0/peripherals/i3c/plans/goal.md for the behavioral
parity plan, authority pin, and deltas ledger.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>