)]}'
{
  "commit": "3b994d2852b7875987ac69713e2602b565f2d181",
  "tree": "0ce0c0736db70a80e6051ea1381eae7ea442335e",
  "parents": [
    "5e50441e01568600c0a56b0a9f753ba3007b29cc"
  ],
  "author": {
    "name": "Steven Lee",
    "email": "steven_lee@aspeedtech.com",
    "time": "Thu Jun 04 16:17:10 2026 +0800"
  },
  "committer": {
    "name": "Steven Lee",
    "email": "steven_lee@aspeedtech.com",
    "time": "Fri Jul 24 12:41:07 2026 +0800"
  },
  "message": "Decouple the I3C ISR from thread-owned state\n\nThe ISR no longer fabricates a \u0026mut over any thread-owned object. The\nper-bus registry now parks an IsrCtx (an ISR-side register handle plus\nthe role flag) instead of a raw context pointer, and the service routine\nworks exclusively through \u0026self register methods, per-bus ISR_EVENTS\natomics, and the global IBI rings. Master transfer completion follows\nthe SMC flag-and-defer model: the ISR masks the completion sources and\nlatches the status; the polling thread drains the response queue into\nits own transfer and re-enables the sources. Target-mode completions\nand the master-assigned dynamic address move into the per-bus event\nblock; ISR-side halt/resume recovery (which needs the wait policy) is\ndeferred to the thread as a fault flag.\n\nThis dissolves the machinery the old design needed: the curr_xfer\nAtomicPtr handoff and its unsafe reconstruction, I3cXfer\u0027s completion\nflag, and the pinned \u0027static I3cCore (with its singleton! storage and\nPin plumbing) are all gone. The controller is a plain owned value with\nzero unsafe; in-flight transfer overlap is structurally impossible\nbecause the transfer never leaves the thread.\n\nThe controller borrows its I3cConfig (\u0026\u0027c mut) rather than owning it:\nthe config embeds ~0.5 KiB of device tables, and the typestate\ntransition moves the controller by value, so owning the config would\ntransiently stack multiple copies and overflow the 2 KiB kernel\nbootstrap stack (observed as a silent hang during bring-up on the EVB).\nBorrowing keeps exactly one config alive in the caller\u0027s frame, the\nsame footprint as the validated pre-rework layout, and matches the I2C\ndriver\u0027s caller-owned-resource convention.\n\nBehavioral deltas from the reference ISR, all thread-visible only:\nSIR address validation moves from the ISR to the consumer (which\nalready validates), and target error recovery runs at the next\noperation instead of inside the interrupt.\n\nVerified on a two-board AST1060 setup: the dual-device IBI exchange\ntest passes 10/10 exchanges.\n",
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