)]}'
{
  "commit": "3e169cf283ff792d7ca023c5e586a36be825f6b9",
  "tree": "bbaf18f278916c39db56a8a3be665cb3372698a6",
  "parents": [
    "3a784a5ff38defb708826c1f111629d6b9ef28f3"
  ],
  "author": {
    "name": "Anthony Rocha",
    "email": "anthony.rocha@amd.com",
    "time": "Fri Sep 11 17:37:43 2026 -0700"
  },
  "committer": {
    "name": "Anthony Rocha",
    "email": "116300062+rusty1968@users.noreply.github.com",
    "time": "Tue Sep 15 09:38:02 2026 -0700"
  },
  "message": "feat: add fpga exit/pass-fail signaling via the wrapper debug FIFO\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "82bd00f42ae31ae4a2e9d34b11b14b04fef7cd66",
      "old_mode": 33188,
      "old_path": "target/veer/entry.rs",
      "new_id": "cc93fe4c9fbe7fb6837c800b06921f263ed8c61f",
      "new_mode": 33188,
      "new_path": "target/veer/entry.rs"
    }
  ]
}