)]}'
{
  "commit": "84006ecab40d9ae740c8c933c9705730b8c7f4b2",
  "tree": "48d2c596cd4ab53e2245fa385bfcb22fde16c615",
  "parents": [
    "836308fe0c28a6c03f5e2b3fd61df29d50ccf23a"
  ],
  "author": {
    "name": "Will Marone",
    "email": "Will.Marone@amd.com",
    "time": "Tue Mar 03 16:51:26 2026 -0800"
  },
  "committer": {
    "name": "Will Marone",
    "email": "Will.Marone@amd.com",
    "time": "Thu Mar 05 11:02:15 2026 -0800"
  },
  "message": "Enable I2C via IPC port of AST test on AST1060\n\nThis fixes some issues on the openprot side of things to enable\nthe ASpeed I2C test to run on Pigweed, sending requests over IPC\nto the I2C server.\n\nThe test makes a few assumptions about the hardware setup:\n- Using an ASpeed PRoT fixture with two devices\n- The JTAG equipped unit running openprot\n- The other runninng a reference build of Zephyr\n\nConfigure the build of Zephyr to simulate an eeprom on i2c address 0x42, this will satisfy the test. Connect I2C2 between the devices.\n\n* Added a testing doc, should replace README.md with it at some point\n* Significant updates to  uart_test_exec.py to add more features and bugfixes.\n* Replace default() with with_static_clocks()\n* Fixed the target bus to match hardware config across the project.\n* Added memory mappings to the i2c server so that it had permission to touch necessary registers\n* Removed semihosting as it was causing misleading faults at the end of the tests.\n\nA change not included here is in pigweed itself, in pw_kernel/arch/arm_cortex_m/protection_v7.rs:\n\n            MemoryRegionType::Device \u003d\u003e (\n                /* xn */ true,\n                /* tex */ 0b000, // Device memory\n                /* s */ true,\n                /* c */ false,\n                /* b */ true,\n-               RasrAp::RoAny,\n+               RasrAp::RwAny,\n            ),\n\nThis is required to allow writes to the registers.\n",
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