Rework I3C driver to runtime-bus model with register facade

One driver type now manages all four bus instances: the Instance
type-parameter and its per-bus impl macro are removed, and the bus is
selected at runtime in I3cRegisters::new(bus), mirroring the SmcRegisters
shape. All I3C MMIO unsafe (pointer derefs) is confined to the new
registers.rs; hardware.rs accesses the blocks through safe delegates.

IRQ ownership moves to the integration layer: enable_irq/disable_irq are
dropped from the hardware traits and the driver only exposes
dispatch_i3c_irq plus an i3c_bus_interrupt(bus) mapping for the NVIC line
the kernel owns. The per-bus handler registry becomes single-shot
(typed Busy on a second claim) and panic-free (UnsafeCell + critical
section, same rationale as the IBI rings, whose closure-based access is
also replaced by leaf push/pop helpers).

The controller is rebuilt around an ISR-shared I3cCore pinned at a
'static address, so the trampoline pointer's validity is type-guaranteed
rather than a convention, with a light two-state lifecycle
(Uninitialized -> start() -> Ready) matching the SMC precedent. Tests
construct the core via cortex_m::singleton!, which also moves the large
config off the 2 KiB bootstrap stack, and unmask the NVIC line
themselves after start().