)]}'
{
  "commit": "9daec62890f4ef9c82fdde1ce5b79b13e9e40e3c",
  "tree": "0c358d3164cf6befbd11925133a6e3a3b570ca84",
  "parents": [
    "83d57da3a06c2a9c4342ce990de6c3909dd4035b"
  ],
  "author": {
    "name": "Anthony Rocha",
    "email": "anthony.rocha@amd.com",
    "time": "Mon Sep 14 14:31:51 2026 -0700"
  },
  "committer": {
    "name": "Anthony Rocha",
    "email": "116300062+rusty1968@users.noreply.github.com",
    "time": "Tue Sep 15 09:38:02 2026 -0700"
  },
  "message": "ci: build the veer fpga target image on every CI run\n\nAdds a build-only (no lab hardware needed) CI job that builds\n//target/veer/unittest_runner:fpga_test under target_type\u003dfpga, so a\nregression like the console rust_library silently losing its fpga\ncfg feature (caught by the final review of the fpga-target plan) gets\nflagged automatically instead of only being visible under\nbazel aquery. Actually running the test still requires a VCK190 board\nand is left manual/opt-in.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "be73c1917b5cd46e31fe016f20cabe9ef6e0e0f9",
      "old_mode": 33188,
      "old_path": "workflows.json",
      "new_id": "08c439f85aa096efcb56edda22f9860ff4b86e3d",
      "new_mode": 33188,
      "new_path": "workflows.json"
    }
  ]
}