)]}'
{
  "commit": "aec495eaee05844464d5600fe28d2f6a8ad673ee",
  "tree": "cd26159b90ee20ca29085d91ba607b48c84e70ba",
  "parents": [
    "6326315c5c307829803b366fc1890bb44144a3a6"
  ],
  "author": {
    "name": "Steven Lee",
    "email": "steven_lee@aspeedtech.com",
    "time": "Fri Jun 12 16:13:46 2026 +0800"
  },
  "committer": {
    "name": "Anthony Rocha",
    "email": "116300062+rusty1968@users.noreply.github.com",
    "time": "Wed Jun 24 08:23:08 2026 -0700"
  },
  "message": "target/ast10x0/peripherals/sgpiom: fix interrupt configure ordering\n\nconfigure_interrupt enabled before programming sensitivity, creating a\nwindow where stale sensitivity codes could fire, and never cleared\nlatched status. Fix: program sensitivity, clear pending, then enable.\n\nwrite_sens_bits now masks enabled pins during the 3-RMW sensitivity\nupdate to prevent transient spurious latches.\n\nSigned-off-by: Steven Lee \u003csteven_lee@aspeedtech.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "51e7c19bde2e4d30ccc89be98d16b24a6aac4385",
      "old_mode": 33188,
      "old_path": "target/ast10x0/peripherals/sgpiom/hal_impl.rs",
      "new_id": "2667cffbae47aae222cb05d7866d881dee4bea9a",
      "new_mode": 33188,
      "new_path": "target/ast10x0/peripherals/sgpiom/hal_impl.rs"
    },
    {
      "type": "modify",
      "old_id": "a2732d0fd7c7e619a9b178fd58d7a3e2d0a35d5c",
      "old_mode": 33188,
      "old_path": "target/ast10x0/peripherals/sgpiom/register_block.rs",
      "new_id": "79016c3269de9aa8c641e3436d8b68cdf1222490",
      "new_mode": 33188,
      "new_path": "target/ast10x0/peripherals/sgpiom/register_block.rs"
    }
  ]
}