tree: f8511bf5a0546ff0e57231b9562266966be64b81
  1. device/
  2. controller.rs
  3. fmc.rs
  4. helpers.rs
  5. interrupts.rs
  6. mod.rs
  7. README.md
  8. registers.rs
  9. spi.rs
  10. types.rs
target/ast10x0/peripherals/smc/README.md

SMC — Static Memory Controller

Driver for the AST1060 FMC and SPI static memory controllers, supporting memory-mapped flash reads, DMA transfers, and interrupt handling.

Module Structure

smc/
├── mod.rs              — Re-exports all public types; module declarations
├── types.rs            — Core types: SmcError, ChipSelect, FlashConfig, SmcConfig,
│                         SmcController, TransferMode, AddressWidth, SmcRetryable
├── register_traits.rs  — SmcRegisterBackend trait (shared register contract)
├── fmc_backend.rs      — FmcRegisterBackend: wraps ast1060_pac::fmc::RegisterBlock
├── spi_backend.rs      — SpiRegisterBackend: wraps ast1060_pac::spi::RegisterBlock
├── controller.rs       — Generic Smc<B: SmcRegisterBackend, Mode> state machine;
│                         type aliases UninitSmc / ReadySmc / UninitSpiSmc / ReadySpiSmc
├── fmc.rs              — FmcUninit / FmcReady: FMC-specific facade over UninitSmc/ReadySmc
├── spi.rs              — SpiUninit / SpiReady: SPI-specific facade over UninitSpiSmc/ReadySpiSmc
├── interrupts.rs       — SmcInterrupt, SmcInterruptDecoder, SmcIsrContext
├── helpers.rs          — Internal helpers: segment encoding, DMA validation, frequency divisor
└── device/             — SPI NOR flash device facade: SpiNorFlash, SpiNorFlashDevice
    ├── flash.rs            trait, FlashCommandProfile, FlashAddressingPolicy, JedecId
    └── block_device.rs     SpiNorBlockDevice, BlockDeviceInfo

Architecture

The driver uses a two-level abstraction:

Register backend (SmcRegisterBackend trait) Abstracts the PAC-level differences between FMC and SPI register blocks. The same register offset can have different field layouts in the two PACs:

BackendPAC typeNotes
FmcRegisterBackendast1060_pac::fmc::RegisterBlockNamed fields (e.g. dmaintenbl())
SpiRegisterBackendast1060_pac::spi::RegisterBlockRaw bit access; adds spi06c/074()

Controller state machine (Smc<B, Mode>) A type-state generic over backend B and mode (Uninitialized / Ready). Transitions from UninitializedReady happen through init(), which configures timing, segments, and transfer mode.

Facade types (FmcUninit/FmcReady, SpiUninit/SpiReady) Thin wrappers around the concrete Smc<…> aliases, intended as the primary API surface for callers.

Key Types

TypeDescription
SmcRegisterBackendTrait: register read/write/modify operations
FmcRegisterBackendFMC PAC register backend
SpiRegisterBackendSPI PAC register backend
Smc<B, Mode>Generic controller state machine
UninitSmc/ReadySmcFMC controller type aliases
UninitSpiSmc/ReadySpiSmcSPI controller type aliases
FmcUninit/FmcReadyFMC facade
SpiUninit/SpiReadySPI facade
SmcConfigController configuration (timing, segments)
FlashConfigPer-CS flash geometry
ChipSelectCs0 / Cs1
TransferModeSingle / Dual / Quad SPI
SmcInterruptDMA completion / error interrupt variants