)]}'
{
  "commit": "ca284ffbbb3077632e4c93e54ee5ed61af853c36",
  "tree": "64d2095bbf2a310033d6d1fd61eb9d2c26293bd1",
  "parents": [
    "eda977853d14d280b0584619bc23ca7fe916332e"
  ],
  "author": {
    "name": "Anthony Rocha",
    "email": "anthony.rocha@amd.com",
    "time": "Fri Sep 11 17:37:39 2026 -0700"
  },
  "committer": {
    "name": "Anthony Rocha",
    "email": "116300062+rusty1968@users.noreply.github.com",
    "time": "Tue Sep 15 09:38:02 2026 -0700"
  },
  "message": "fix: correct veer fpga target clock to match VCK190 hardware (20 MHz)\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3a2ab0d8a2a0b5c4be2f8eb4feb175d8caf00d4a",
      "old_mode": 33188,
      "old_path": "target/veer/config.rs",
      "new_id": "b002c8a804532315ce31b76d902ad079a45e48a8",
      "new_mode": 33188,
      "new_path": "target/veer/config.rs"
    }
  ]
}