)]}'
{
  "commit": "d396e7a6af8715a8947c66b810d685926eb90f87",
  "tree": "34a72f0687c2dd60a21a3e5786e51ddd01badfbb",
  "parents": [
    "114be915db2c5c58f8c75a0c62094096e2977c2c"
  ],
  "author": {
    "name": "PojuiLiu",
    "email": "pojui_liu@jabil.com",
    "time": "Wed Jul 08 15:45:48 2026 +0800"
  },
  "committer": {
    "name": "PojuiLiu",
    "email": "pojui_liu@jabil.com",
    "time": "Wed Jul 08 17:33:34 2026 +0800"
  },
  "message": "fix(ast10x0-spim): correct control bits and mux polarity\n\nCorrect SPI-monitor driver defects on the AST1060 flash-routing path.\n\n- Fix SPIPF000 control bits: enable [0]-\u003e[2], passthrough [1]-\u003e[0].\n- Fix inverted RoT/host mux polarity in the board monitor (Cypress).\n- Mux the MISO pin on enable/disable; add sw_reset (sweng_rst).\n- Replace the guessed filter encoding with confirmed SPIPFWA\n  (addr_priv) and SPIPFWT (cmd_table) tables.\n- Add set_spim_scu_monitor_enable and spim_disable_cs_internal_pd.\n\nSigned-off-by: PojuiLiu \u003cpojui_liu@jabil.com\u003e\n",
  "tree_diff": [
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