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pigweed / third_party / github / STMicroelectronics / cmsis_core / 7dd288b23bf605a3a2fafa81a29d2c96a2fd83ce / . / Documentation / Core / html / struct_m_p_u___type.html
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<p>Structure type to access the Memory Protection Unit (MPU).
</p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a0433efc1383674bc8e86cc0e830b462d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a0433efc1383674bc8e86cc0e830b462d">TYPE</a></td></tr>
<tr class="memdesc:a0433efc1383674bc8e86cc0e830b462d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) MPU Type Register. <a href="#a0433efc1383674bc8e86cc0e830b462d"></a><br/></td></tr>
<tr class="separator:a0433efc1383674bc8e86cc0e830b462d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4d81d6aa73a9287bafba2bcc5ffc6d18"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a4d81d6aa73a9287bafba2bcc5ffc6d18">CTRL</a></td></tr>
<tr class="memdesc:a4d81d6aa73a9287bafba2bcc5ffc6d18"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) MPU Control Register. <a href="#a4d81d6aa73a9287bafba2bcc5ffc6d18"></a><br/></td></tr>
<tr class="separator:a4d81d6aa73a9287bafba2bcc5ffc6d18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa800d44f4d3520cc891d7b8d711320c1"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#aa800d44f4d3520cc891d7b8d711320c1">RNR</a></td></tr>
<tr class="memdesc:aa800d44f4d3520cc891d7b8d711320c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) MPU Region RNRber Register. <a href="#aa800d44f4d3520cc891d7b8d711320c1"></a><br/></td></tr>
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<tr class="memitem:ac953770d38a7d322b971d93eb8a5b062"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#ac953770d38a7d322b971d93eb8a5b062">RBAR</a></td></tr>
<tr class="memdesc:ac953770d38a7d322b971d93eb8a5b062"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) MPU Region Base Address Register. <a href="#ac953770d38a7d322b971d93eb8a5b062"></a><br/></td></tr>
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<tr class="memitem:a9236c629b7cf86f8bd2459c610fdf715"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a9236c629b7cf86f8bd2459c610fdf715">RASR</a></td></tr>
<tr class="memdesc:a9236c629b7cf86f8bd2459c610fdf715"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) MPU Region Attribute and Size Register. <a href="#a9236c629b7cf86f8bd2459c610fdf715"></a><br/></td></tr>
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<tr class="memitem:a13d69b9bea12861383f3a62764b02f63"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a13d69b9bea12861383f3a62764b02f63">RBAR_A1</a></td></tr>
<tr class="memdesc:a13d69b9bea12861383f3a62764b02f63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register. <a href="#a13d69b9bea12861383f3a62764b02f63"></a><br/></td></tr>
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<tr class="memdesc:ab5a224ccd12ac55ddfe11d9eca42de48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register. <a href="#ab5a224ccd12ac55ddfe11d9eca42de48"></a><br/></td></tr>
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<tr class="memitem:a57dc551614932150e684fcc60590c2c4"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a57dc551614932150e684fcc60590c2c4">RBAR_A2</a></td></tr>
<tr class="memdesc:a57dc551614932150e684fcc60590c2c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register. <a href="#a57dc551614932150e684fcc60590c2c4"></a><br/></td></tr>
<tr class="separator:a57dc551614932150e684fcc60590c2c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memdesc:ac60e0919871b66446a039838bcaaec3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register. <a href="#ac60e0919871b66446a039838bcaaec3b"></a><br/></td></tr>
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<tr class="memitem:a345911aabecd1f7d93a1bff7738b0d86"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a345911aabecd1f7d93a1bff7738b0d86">RBAR_A3</a></td></tr>
<tr class="memdesc:a345911aabecd1f7d93a1bff7738b0d86"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register. <a href="#a345911aabecd1f7d93a1bff7738b0d86"></a><br/></td></tr>
<tr class="separator:a345911aabecd1f7d93a1bff7738b0d86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9c0b2d3e3e16bb4e7dfa069652d5a155"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a9c0b2d3e3e16bb4e7dfa069652d5a155">RASR_A3</a></td></tr>
<tr class="memdesc:a9c0b2d3e3e16bb4e7dfa069652d5a155"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register. <a href="#a9c0b2d3e3e16bb4e7dfa069652d5a155"></a><br/></td></tr>
<tr class="separator:a9c0b2d3e3e16bb4e7dfa069652d5a155"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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