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| <div id="projectname">CMSIS-Core (Cortex-M) |
|  <span id="projectnumber">Version 5.1.2</span> |
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| <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> |
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| <div class="textblock">Here is a list of all modules:</div><div class="directory"> |
| <div class="levels">[detail level <span onclick="javascript:toggleLevel(1);">1</span><span onclick="javascript:toggleLevel(2);">2</span>]</div><table class="directory"> |
| <tr id="row_0_" class="even"><td class="entry"><img id="arr_0_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('0_')"/><a class="el" href="group__version__control__gr.html" target="_self">Version Control</a></td><td class="desc">Version #define symbols for CMSIS release specific C/C++ source code </td></tr> |
| <tr id="row_0_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__version__control__depricated__gr.html" target="_self">Version Control per Core (Depricated)</a></td><td class="desc">Version #define symbols for CMSIS release specific C/C++ source code </td></tr> |
| <tr id="row_1_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__compiler__conntrol__gr.html" target="_self">Compiler Control</a></td><td class="desc">Compiler agnostic #define symbols for generic C/C++ source code </td></tr> |
| <tr id="row_2_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__peripheral__gr.html" target="_self">Peripheral Access</a></td><td class="desc">Naming conventions and optional features for accessing peripherals </td></tr> |
| <tr id="row_3_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__system__init__gr.html" target="_self">System and Clock Configuration</a></td><td class="desc">Functions for system and clock setup available in system_<em>device</em>.c </td></tr> |
| <tr id="row_4_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__NVIC__gr.html" target="_self">Interrupts and Exceptions (NVIC)</a></td><td class="desc">Functions to access the Nested Vector Interrupt Controller (NVIC) </td></tr> |
| <tr id="row_5_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__Core__Register__gr.html" target="_self">Core Register Access</a></td><td class="desc">Functions to access the Cortex-M core registers </td></tr> |
| <tr id="row_6_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic__CPU__gr.html" target="_self">Intrinsic Functions for CPU Instructions</a></td><td class="desc">Functions that generate specific Cortex-M CPU Instructions </td></tr> |
| <tr id="row_7_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic__SIMD__gr.html" target="_self">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a></td><td class="desc">Access to dedicated SIMD instructions </td></tr> |
| <tr id="row_8_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__fpu__functions.html" target="_self">FPU Functions</a></td><td class="desc">Functions that relate to the Floating-Point Arithmetic Unit </td></tr> |
| <tr id="row_9_" class="even"><td class="entry"><img id="arr_9_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('9_')"/><a class="el" href="group__mpu__functions.html" target="_self">MPU Functions for Armv7-M</a></td><td class="desc">Functions that relate to the Memory Protection Unit </td></tr> |
| <tr id="row_9_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__mpu__defines.html" target="_self">Define values</a></td><td class="desc">Define values for MPU region setup </td></tr> |
| <tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__SysTick__gr.html" target="_self">Systick Timer (SYSTICK)</a></td><td class="desc">Initialize and start the SysTick timer </td></tr> |
| <tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__ITM__Debug__gr.html" target="_self">Debug Access</a></td><td class="desc">Debug Access to the Instrumented Trace Macrocell (ITM) </td></tr> |
| <tr id="row_12_" class="even"><td class="entry"><img id="arr_12_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('12_')"/><a class="el" href="group__trustzone__functions.html" target="_self">TrustZone for Armv8-M</a></td><td class="desc">Functions that related to optional Armv8-M security extension </td></tr> |
| <tr id="row_12_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__coreregister__trustzone__functions.html" target="_self">Core Register Access Functions</a></td><td class="desc">Core register Access functions related to TrustZone for Armv8-M </td></tr> |
| <tr id="row_12_1_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__nvic__trustzone__functions.html" target="_self">NVIC Functions</a></td><td class="desc">Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M </td></tr> |
| <tr id="row_12_2_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__systick__trustzone__functions.html" target="_self">SysTick Functions</a></td><td class="desc">SysTick functions related to TrustZone for Armv8-M </td></tr> |
| <tr id="row_12_3_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__sau__trustzone__functions.html" target="_self">SAU Functions</a></td><td class="desc">Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M </td></tr> |
| <tr id="row_12_4_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__context__trustzone__functions.html" target="_self">RTOS Context Management</a></td><td class="desc">RTOS Thread Context Management for Armv8-M TrustZone </td></tr> |
| <tr id="row_13_" class="even"><td class="entry"><img id="arr_13_" src="ftv2mlastnode.png" alt="\" width="16" height="22" onclick="toggleFolder('13_')"/><a class="el" href="group__cache__functions__m7.html" target="_self">Cache Functions (only Cortex-M7)</a></td><td class="desc">Functions for Instruction and Data Cache </td></tr> |
| <tr id="row_13_0_"><td class="entry"><img src="ftv2blank.png" alt=" " width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__Icache__functions__m7.html" target="_self">I-Cache Functions</a></td><td class="desc">Functions for the instruction cache </td></tr> |
| <tr id="row_13_1_" class="even"><td class="entry"><img src="ftv2blank.png" alt=" " width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__Dcache__functions__m7.html" target="_self">D-Cache Functions</a></td><td class="desc">Functions for the data cache </td></tr> |
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