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<div id="projectname">CMSIS-RTOS
&#160;<span id="projectnumber">Version 1.03</span>
<div id="projectbrief">Real-Time Operating System: API and RTX Reference Implementation.</div>
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<div class="title">Generic RTOS Interface </div> </div>
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<div class="textblock"><p>The CMSIS-RTOS API is a generic RTOS interface for Arm&reg; Cortex&reg;-M processor-based devices. CMSIS-RTOS provides a standardized API for software components that require RTOS functionality and gives therefore serious benefits to the users and the software industry.</p>
<li>CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).</li>
<li>The unified feature set of the CMSIS-RTOS API simplifies sharing of software components and reduces learning efforts.</li>
<li>Middleware components that use the CMSIS-RTOS API are RTOS agnostic. CMSIS-RTOS compliant middleware is easier to adapt.</li>
<li>Standard project templates (such as motor control) of the CMSIS-RTOS API may be shipped with freely available CMSIS-RTOS implementations.</li>
<dl class="section note"><dt>Note</dt><dd>The CMSIS-RTOS API defines a minimum feature set. Implementations with extended features may be provided by RTOS vendors.</dd></dl>
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CMSIS-RTOS API Structure</div></div>
<p> A typical CMSIS-RTOS API implementation interfaces to an existing real-time Kernel. The CMSIS-RTOS API provides the following attributes and functionalities:</p>
<li>Function names, identifiers, and parameters are descriptive and easy to understand. The functions are powerful and flexible which reduces the number of functions exposed to the user.</li>
<li><a class="el" href="group__CMSIS__RTOS__ThreadMgmt.html">Thread Management</a> allows you to define, create, and control threads.</li>
<li>Interrupt Service Routines (ISR) can <a class="el" href="functionOverview.html#CMSIS_RTOS_ISR_Calls">call some CMSIS-RTOS functions</a>. When a CMSIS-RTOS function cannot be called from ISR context, it rejects the invocation.</li>
<li>Three different thread event types support communication between multiple threads and/or ISR:<ul>
<li><b>Signal:</b> is a flag that may be used to indicate specific conditions to a thread. Signals can be modified in an ISR or set from other threads.</li>
<li><b>Message:</b> is a 32-bit value that can be sent to a thread or an ISR. Messages are buffered in a queue. The message type and queue size is defined in a descriptor.</li>
<li><b>Mail:</b> is a fixed-size memory block that can be sent to a thread or an ISR. Mails are buffered in a queue and memory allocation is provided. The mail type and queue size is defined in a descriptor.</li>
<li><a class="el" href="group__CMSIS__RTOS__MutexMgmt.html">Mutexes</a> and <a class="el" href="group__CMSIS__RTOS__SemaphoreMgmt.html">Semaphores</a> are incorporated.</li>
<li>CPU time can be schedule with the following functionalities:<ul>
<li>A <em>timeout</em> parameter is incorporated in many CMSIS-RTOS functions to avoid system lockup. When a timeout is specified, the system waits until a resource is available or an event occurs. While waiting, other threads are scheduled.</li>
<li>The <a class="el" href="group__CMSIS__RTOS__Wait.html#ga02e19d5e723bfb06ba9324d625162255">osDelay</a> function puts a thread into the state <b>WAITING</b> for a specified period of time.</li>
<li>The generic <a class="el" href="technicalData.html#osWait">osWait</a> function waits for events that are assigned to a thread.</li>
<li>The <a class="el" href="group__CMSIS__RTOS__ThreadMgmt.html#gaf13a667493c5d629a90c13e113b99233">osThreadYield</a> provides co-operative thread switching and passes execution to another thread of the same priority.</li>
<p>The CMSIS-RTOS API is designed to optionally incorporate multi-processor systems and/or access protection via the Cortex-M Memory Protection Unit (MPU).</p>
<p>In some RTOS implementations threads may execute on different processors and <b>Mail</b> and <b>Message</b> queues can therefore reside in shared memory resources.</p>
<p>The CMSIS-RTOS API encourages the software industry to evolve existing RTOS implementations. Kernel objects are defined and accessed using macros. This allows differentiation. RTOS implementations can be different and optimized in various aspects towards the Cortex-M processors. Optional features may be for example</p>
<li>Generic <b>wait</b> function; i.e. with support of time intervals.</li>
<li>Support of the Cortex-M Memory Protection Unit (MPU).</li>
<li>Zero-copy mail queue.</li>
<li>Support of multi-processor systems.</li>
<li>Support of a DMA controller.</li>
<li>Deterministic context switching.</li>
<li>Round-robin context switching.</li>
<li>Deadlock avoidance, for example with priority inversion.</li>
<li>Zero interrupt latency by using the Cortex-M3/M4 instructions LDREX and STREX. </li>
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