| <?xml version="1.0" encoding="UTF-8"?> |
| |
| <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd"> |
| <name>CMSIS</name> |
| <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description> |
| <vendor>ARM</vendor> |
| <!-- <license>license.txt</license> --> |
| <url>http://www.keil.com/pack/</url> |
| |
| <releases> |
| <release version="5.6.0" date="2019-07-10"> |
| CMSIS-Core(M): 5.3.0 (see revision history for details) |
| - Added provisions for compiler-independent C startup code. |
| CMSIS-Core(A): 1.1.4 (see revision history for details) |
| - Fixed __FPU_Enable. |
| CMSIS-DSP: 1.7.0 (see revision history for details) |
| - New Neon versions of f32 functions |
| - Python wrapper |
| - Preliminary cmake build |
| - Compilation flags for FFTs |
| - Changes to arm_math.h |
| CMSIS-NN: 1.2.0 (see revision history for details) |
| - New function for depthwise convolution with asymmetric quantization. |
| - New support functions for requantization. |
| CMSIS-RTOS: |
| - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+) |
| CMSIS-RTOS2: |
| - RTX 5.5.1 (see revision history for details) |
| CMSIS-Driver: 2.7.1 |
| - WiFi Interface API 1.0.0 |
| Devices: |
| - Generalized C startup code for all Cortex-M familiy devices. |
| - Updated Cortex-A default memory regions and MMU configurations |
| - Moved Cortex-A memory and system config files to avoid include path issues |
| </release> |
| <release version="5.5.1" date="2019-03-20"> |
| The following folders are deprecated |
| - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) |
| |
| CMSIS-Core(M): 5.2.1 (see revision history for details) |
| - Fixed compilation issue in cmsis_armclang_ltm.h |
| </release> |
| <release version="5.5.0" date="2019-03-18"> |
| The following folders have been removed: |
| - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/) |
| - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/) |
| The following folders are deprecated |
| - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) |
| |
| CMSIS-Core(M): 5.2.0 (see revision history for details) |
| - Reworked Stack/Heap configuration for ARM startup files. |
| - Added Cortex-M35P device support. |
| - Added generic Armv8.1-M Mainline device support. |
| CMSIS-Core(A): 1.1.3 (see revision history for details) |
| CMSIS-DSP: 1.6.0 (see revision history for details) |
| - reworked DSP library source files |
| - reworked DSP library documentation |
| - Changed DSP folder structure |
| - moved DSP libraries to folder ./DSP/Lib |
| - ARM DSP Libraries are built with ARMCLANG |
| - Added DSP Libraries Source variant |
| CMSIS-RTOS2: |
| - RTX 5.5.0 (see revision history for details) |
| CMSIS-Driver: 2.7.0 |
| - Added WiFi Interface API 1.0.0-beta |
| - Added components for project specific driver implementations |
| CMSIS-Pack: 1.6.0 (see revision history for details) |
| Devices: |
| - Added Cortex-M35P and ARMv81MML device templates. |
| - Fixed C-Startup Code for GCC (aligned with other compilers) |
| Utilities: |
| - SVDConv 3.3.25 |
| - PackChk 1.3.82 |
| </release> |
| <release version="5.4.0" date="2018-08-01"> |
| Aligned pack structure with repository. |
| The following folders are deprecated: |
| - CMSIS/Include/ |
| - CMSIS/DSP_Lib/ |
| |
| CMSIS-Core(M): 5.1.2 (see revision history for details) |
| - Added Cortex-M1 support (beta). |
| CMSIS-Core(A): 1.1.2 (see revision history for details) |
| CMSIS-NN: 1.1.0 |
| - Added new math functions. |
| CMSIS-RTOS2: |
| - API 2.1.3 (see revision history for details) |
| - RTX 5.4.0 (see revision history for details) |
| * Updated exception handling on Cortex-A |
| CMSIS-Driver: |
| - Flash Driver API V2.2.0 |
| Utilities: |
| - SVDConv 3.3.21 |
| - PackChk 1.3.71 |
| </release> |
| <release version="5.3.0" date="2018-02-22"> |
| Updated Arm company brand. |
| CMSIS-Core(M): 5.1.1 (see revision history for details) |
| CMSIS-Core(A): 1.1.1 (see revision history for details) |
| CMSIS-DAP: 2.0.0 (see revision history for details) |
| CMSIS-NN: 1.0.0 |
| - Initial contribution of the bare metal Neural Network Library. |
| CMSIS-RTOS2: |
| - RTX 5.3.0 (see revision history for details) |
| - OS Tick API 1.0.1 |
| </release> |
| <release version="5.2.0" date="2017-11-16"> |
| CMSIS-Core(M): 5.1.0 (see revision history for details) |
| - Added MPU Functions for ARMv8-M for Cortex-M23/M33. |
| - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler. |
| CMSIS-Core(A): 1.1.0 (see revision history for details) |
| - Added compiler_iccarm.h. |
| - Added additional access functions for physical timer. |
| CMSIS-DAP: 1.2.0 (see revision history for details) |
| CMSIS-DSP: 1.5.2 (see revision history for details) |
| CMSIS-Driver: 2.6.0 (see revision history for details) |
| - CAN Driver API V1.2.0 |
| - NAND Driver API V2.3.0 |
| CMSIS-RTOS: |
| - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata. |
| CMSIS-RTOS2: |
| - API 2.1.2 (see revision history for details) |
| - RTX 5.2.3 (see revision history for details) |
| Devices: |
| - Added GCC startup and linker script for Cortex-A9. |
| - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU. |
| - Added IAR startup code for Cortex-A9 |
| </release> |
| <release version="5.1.1" date="2017-09-19"> |
| CMSIS-RTOS2: |
| - RTX 5.2.1 (see revision history for details) |
| </release> |
| <release version="5.1.0" date="2017-08-04"> |
| CMSIS-Core(M): 5.0.2 (see revision history for details) |
| - Changed Version Control macros to be core agnostic. |
| - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7. |
| CMSIS-Core(A): 1.0.0 (see revision history for details) |
| - Initial release |
| - IRQ Controller API 1.0.0 |
| CMSIS-Driver: 2.05 (see revision history for details) |
| - All typedefs related to status have been made volatile. |
| CMSIS-RTOS2: |
| - API 2.1.1 (see revision history for details) |
| - RTX 5.2.0 (see revision history for details) |
| - OS Tick API 1.0.0 |
| CMSIS-DSP: 1.5.2 (see revision history for details) |
| - Fixed GNU Compiler specific diagnostics. |
| CMSIS-Pack: 1.5.0 (see revision history for details) |
| - added System Description File (*.SDF) Format |
| CMSIS-Zone: 0.0.1 (Preview) |
| - Initial specification draft |
| </release> |
| <release version="5.0.1" date="2017-02-03"> |
| Package Description: |
| - added taxonomy for Cclass RTOS |
| CMSIS-RTOS2: |
| - API 2.1 (see revision history for details) |
| - RTX 5.1.0 (see revision history for details) |
| CMSIS-Core: 5.0.1 (see revision history for details) |
| - Added __PACKED_STRUCT macro |
| - Added uVisior support |
| - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__ |
| - Updated template for secure main function (main_s.c) |
| - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c) |
| CMSIS-DSP: 1.5.1 (see revision history for details) |
| - added ARMv8M DSP libraries. |
| CMSIS-Pack:1.4.9 (see revision history for details) |
| - added Pack Index File specification and schema file |
| </release> |
| <release version="5.0.0" date="2016-11-11"> |
| Changed open source license to Apache 2.0 |
| CMSIS_Core: |
| - Added support for Cortex-M23 and Cortex-M33. |
| - Added ARMv8-M device configurations for mainline and baseline. |
| - Added CMSE support and thread context management for TrustZone for ARMv8-M |
| - Added cmsis_compiler.h to unify compiler behaviour. |
| - Updated function SCB_EnableICache (for Cortex-M7). |
| - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType |
| CMSIS-RTOS: |
| - bug fix in RTX 4.82 (see revision history for details) |
| CMSIS-RTOS2: |
| - new API including compatibility layer to CMSIS-RTOS |
| - reference implementation based on RTX5 |
| - supports all Cortex-M variants including TrustZone for ARMv8-M |
| CMSIS-SVD: |
| - reworked SVD format documentation |
| - removed SVD file database documentation as SVD files are distributed in packs |
| - updated SVDConv for Win32 and Linux |
| CMSIS-DSP: |
| - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. |
| - Added DSP libraries build projects to CMSIS pack. |
| </release> |
| <release version="4.5.0" date="2015-10-28"> |
| - CMSIS-Core 4.30.0 (see revision history for details) |
| - CMSIS-DAP 1.1.0 (unchanged) |
| - CMSIS-Driver 2.04.0 (see revision history for details) |
| - CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details) |
| - CMSIS-Pack 1.4.1 (see revision history for details) |
| - CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details) |
| - CMSIS-SVD 1.3.1 (see revision history for details) |
| </release> |
| <release version="4.4.0" date="2015-09-11"> |
| - CMSIS-Core 4.20 (see revision history for details) |
| - CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details) |
| - CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style) |
| - CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API) |
| - CMSIS-RTOS |
| -- API 1.02 (unchanged) |
| -- RTX 4.79 (see revision history for details) |
| - CMSIS-SVD 1.3.0 (see revision history for details) |
| - CMSIS-DAP 1.1.0 (extended with SWO support) |
| </release> |
| <release version="4.3.0" date="2015-03-20"> |
| - CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions) |
| - CMSIS-DSP 1.4.5 (see revision history for details) |
| - CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API) |
| - CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions) |
| - CMSIS-RTOS |
| -- API 1.02 (unchanged) |
| -- RTX 4.78 (see revision history for details) |
| - CMSIS-SVD 1.2 (unchanged) |
| </release> |
| <release version="4.2.0" date="2014-09-24"> |
| Adding Cortex-M7 support |
| - CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files) |
| - CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues) |
| - CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial) |
| - CMSIS-SVD 1.2 (Cortex-M7 extensions) |
| - CMSIS-RTOS RTX 4.75 (see revision history for details) |
| </release> |
| <release version="4.1.1" date="2014-06-30"> |
| - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices |
| </release> |
| <release version="4.1.0" date="2014-06-12"> |
| - CMSIS-Driver 2.02 (incompatible update) |
| - CMSIS-Pack 1.3 (see revision history for details) |
| - CMSIS-DSP 1.4.2 (unchanged) |
| - CMSIS-Core 3.30 (unchanged) |
| - CMSIS-RTOS RTX 4.74 (unchanged) |
| - CMSIS-RTOS API 1.02 (unchanged) |
| - CMSIS-SVD 1.10 (unchanged) |
| PACK: |
| - removed G++ specific files from PACK |
| - added Component Startup variant "C Startup" |
| - added Pack Checking Utility |
| - updated conditions to reflect tool-chain dependency |
| - added Taxonomy for Graphics |
| - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" |
| </release> |
| <!-- release version="4.0.0"> |
| - CMSIS-Driver 2.00 Preliminary (incompatible update) |
| - CMSIS-Pack 1.1 Preliminary |
| - CMSIS-DSP 1.4.2 (see revision history for details) |
| - CMSIS-Core 3.30 (see revision history for details) |
| - CMSIS-RTOS RTX 4.74 (see revision history for details) |
| - CMSIS-RTOS API 1.02 (unchanged) |
| - CMSIS-SVD 1.10 (unchanged) |
| </release --> |
| <release version="3.20.4" date="2014-02-20"> |
| - CMSIS-RTOS 4.74 (see revision history for details) |
| - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. |
| </release> |
| <!-- release version="3.20.3"> |
| - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change) |
| - CMSIS-RTOS 4.73 (see revision history for details) |
| </release --> |
| <!-- release version="3.20.2"> |
| - CMSIS-Pack documentation has been added |
| - CMSIS-Drivers header and documentation have been added to PACK |
| - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged |
| </release --> |
| <!-- release version="3.20.1"> |
| - CMSIS-RTOS Keil RTX V4.72 has been added to PACK |
| - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged |
| </release --> |
| <!-- release version="3.20.0"> |
| The software portions that are deployed in the application program are now under a BSD license which allows usage |
| of CMSIS components in any commercial or open source projects. The Pack Description file Arm.CMSIS.pdsc describes the use cases |
| The individual components have been update as listed below: |
| - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections. |
| - CMSIS-DSP library is optimized for more performance and contains several bug fixes. |
| - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface. |
| - CMSIS-SVD is unchanged. |
| </release --> |
| </releases> |
| |
| <taxonomy> |
| <description Cclass="Audio">Software components for audio processing</description> |
| <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description> |
| <description Cclass="Board Part">Drivers that support an external component available on an evaluation board</description> |
| <description Cclass="Compiler">Compiler Software Extensions</description> |
| <description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description> |
| <description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description> |
| <description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description> |
| <description Cclass="Data Exchange">Data exchange or data formatter</description> |
| <description Cclass="Extension Board">Drivers that support an extension board or shield</description> |
| <description Cclass="File System">File Drive Support and File System</description> |
| <description Cclass="IoT Client">IoT cloud client connector</description> |
| <description Cclass="IoT Utility">IoT specific software utility</description> |
| <description Cclass="Graphics">Graphical User Interface</description> |
| <description Cclass="Network">Network Stack using Internet Protocols</description> |
| <description Cclass="RTOS">Real-time Operating System</description> |
| <description Cclass="Security">Encryption for secure communication or storage</description> |
| <description Cclass="USB">Universal Serial Bus Stack</description> |
| <description Cclass="Utility">Generic software utility components</description> |
| </taxonomy> |
| |
| <devices> |
| <!-- ****************************** Cortex-M0 ****************************** --> |
| <family Dfamily="ARM Cortex M0" Dvendor="ARM:82"> |
| <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/> |
| <description> |
| The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: |
| - simple, easy-to-use programmers model |
| - highly efficient ultra-low power operation |
| - excellent code density |
| - deterministic, high-performance interrupt handling |
| - upward compatibility with the rest of the Cortex-M processor family. |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM0"> |
| <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-M0P ****************************** --> |
| <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82"> |
| <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/> |
| <description> |
| The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: |
| - simple, easy-to-use programmers model |
| - highly efficient ultra-low power operation |
| - excellent code density |
| - deterministic, high-performance interrupt handling |
| - upward compatibility with the rest of the Cortex-M processor family. |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM0P"> |
| <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/> |
| </device> |
| |
| <device Dname="ARMCM0P_MPU"> |
| <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-M1 ****************************** --> |
| <family Dfamily="ARM Cortex M1" Dvendor="ARM:82"> |
| <!--book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M1 Device Generic Users Guide"/--> |
| <description> |
| The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA. |
| The ARM Cortex-M1 processor implements the ARMv6-M architecture profile. |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM1"> |
| <processor Dcore="Cortex-M1" DcoreVersion="r1p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM1/Include/ARMCM1.h" define="ARMCM1"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-M3 ****************************** --> |
| <family Dfamily="ARM Cortex M3" Dvendor="ARM:82"> |
| <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/> |
| <description> |
| The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: |
| - simple, easy-to-use programmers model |
| - highly efficient ultra-low power operation |
| - excellent code density |
| - deterministic, high-performance interrupt handling |
| - upward compatibility with the rest of the Cortex-M processor family. |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM3"> |
| <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-M4 ****************************** --> |
| <family Dfamily="ARM Cortex M4" Dvendor="ARM:82"> |
| <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/> |
| <description> |
| The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: |
| - simple, easy-to-use programmers model |
| - highly efficient ultra-low power operation |
| - excellent code density |
| - deterministic, high-performance interrupt handling |
| - upward compatibility with the rest of the Cortex-M processor family. |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM4"> |
| <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM4/Include/ARMCM4.h" define="ARMCM4"/> |
| </device> |
| |
| <device Dname="ARMCM4_FP"> |
| <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-M7 ****************************** --> |
| <family Dfamily="ARM Cortex M7" Dvendor="ARM:82"> |
| <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/> |
| <description> |
| The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: |
| - simple, easy-to-use programmers model |
| - highly efficient ultra-low power operation |
| - excellent code density |
| - deterministic, high-performance interrupt handling |
| - upward compatibility with the rest of the Cortex-M processor family. |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM7"> |
| <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/> |
| </device> |
| |
| <device Dname="ARMCM7_SP"> |
| <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/> |
| </device> |
| |
| <device Dname="ARMCM7_DP"> |
| <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-M23 ********************** --> |
| <family Dfamily="ARM Cortex M23" Dvendor="ARM:82"> |
| <!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/--> |
| <description> |
| The Arm Cortex-M23 is based on the Armv8-M baseline architecture. |
| It is the smallest and most energy efficient Arm processor with Arm TrustZone technology. |
| Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security. |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/> |
| <memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM23"> |
| <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/> |
| </device> |
| |
| <device Dname="ARMCM23_TZ"> |
| <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-M33 ****************************** --> |
| <family Dfamily="ARM Cortex M33" Dvendor="ARM:82"> |
| <!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/--> |
| <description> |
| The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller |
| class processor based on the Armv8-M mainline architecture with Arm TrustZone security. |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/> |
| <memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM33"> |
| <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| no DSP Instructions, no Floating Point Unit, no TrustZone |
| </description> |
| <compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/> |
| </device> |
| |
| <device Dname="ARMCM33_TZ"> |
| <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| no DSP Instructions, no Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/> |
| </device> |
| |
| <device Dname="ARMCM33_DSP_FP"> |
| <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| DSP Instructions, Single Precision Floating Point Unit, no TrustZone |
| </description> |
| <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/> |
| </device> |
| |
| <device Dname="ARMCM33_DSP_FP_TZ"> |
| <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| DSP Instructions, Single Precision Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-M35P ****************************** --> |
| <family Dfamily="ARM Cortex M35P" Dvendor="ARM:82"> |
| <!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/--> |
| <description> |
| The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller |
| class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications. |
| </description> |
| |
| <!-- debug svd="Device/ARM/SVD/ARMCM35P.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/> |
| <memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMCM35P"> |
| <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| no DSP Instructions, no Floating Point Unit, no TrustZone |
| </description> |
| <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P.h" define="ARMCM35P"/> |
| </device> |
| |
| <device Dname="ARMCM35P_TZ"> |
| <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| no DSP Instructions, no Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h" define="ARMCM35P_TZ"/> |
| </device> |
| |
| <device Dname="ARMCM35P_DSP_FP"> |
| <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| DSP Instructions, Single Precision Floating Point Unit, no TrustZone |
| </description> |
| <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h" define="ARMCM35P_DSP_FP"/> |
| </device> |
| |
| <device Dname="ARMCM35P_DSP_FP_TZ"> |
| <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| DSP Instructions, Single Precision Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h" define="ARMCM35P_DSP_FP_TZ"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** ARMSC000 ****************************** --> |
| <family Dfamily="ARM SC000" Dvendor="ARM:82"> |
| <description> |
| The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: |
| - simple, easy-to-use programmers model |
| - highly efficient ultra-low power operation |
| - excellent code density |
| - deterministic, high-performance interrupt handling |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMSC000"> |
| <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** ARMSC300 ****************************** --> |
| <family Dfamily="ARM SC300" Dvendor="ARM:82"> |
| <description> |
| The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including: |
| - simple, easy-to-use programmers model |
| - highly efficient ultra-low power operation |
| - excellent code density |
| - deterministic, high-performance interrupt handling |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMSC300"> |
| <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** ARMv8-M Baseline ********************** --> |
| <family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82"> |
| <!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf" title="ARMv8MBL Device Generic Users Guide"/--> |
| <description> |
| Armv8-M Baseline based device with TrustZone |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/> |
| <memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMv8MBL"> |
| <processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** ARMv8-M Mainline ****************************** --> |
| <family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82"> |
| <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf" title="ARMv8MML Device Generic Users Guide"/--> |
| <description> |
| Armv8-M Mainline based device with TrustZone |
| </description> |
| <!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral --> |
| <memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/> |
| <memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/> |
| <memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/> |
| <memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| <device Dname="ARMv8MML"> |
| <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| no DSP Instructions, no Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/> |
| </device> |
| |
| <device Dname="ARMv8MML_DSP"> |
| <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| DSP Instructions, no Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/> |
| </device> |
| |
| <device Dname="ARMv8MML_SP"> |
| <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| no DSP Instructions, Single Precision Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/> |
| </device> |
| |
| <device Dname="ARMv8MML_DSP_SP"> |
| <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| DSP Instructions, Single Precision Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/> |
| </device> |
| |
| <device Dname="ARMv8MML_DP"> |
| <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| no DSP Instructions, Double Precision Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/> |
| </device> |
| |
| <device Dname="ARMv8MML_DSP_DP"> |
| <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| DSP Instructions, Double Precision Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** ARMv8.1-M Mainline ****************************** --> |
| <family Dfamily="ARMv8.1-M Mainline" Dvendor="ARM:82"> |
| <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf" title="ARMv8MML Device Generic Users Guide"/--> |
| <description> |
| Armv8.1-M Mainline based device with TrustZone and MVE |
| </description> |
| <!-- <debug svd="Device/ARM/SVD/ARMv8MML.svd"/> --> |
| <memory id="IROM1" start="0x10000000" size="0x00200000" startup="1" default="1"/> |
| <memory id="IROM2" start="0x00000000" size="0x00200000" startup="0" default="0"/> |
| <memory id="IRAM1" start="0x30000000" size="0x00020000" init ="0" default="1"/> |
| <memory id="IRAM2" start="0x20000000" size="0x00020000" init ="0" default="0"/> |
| <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/--> |
| |
| |
| <device Dname="ARMv81MML_DSP_DP_MVE_FP"> |
| <processor Dcore="ARMV81MML" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dmve="FP_MVE" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/> |
| <description> |
| Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone |
| </description> |
| <compile header="Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h" define="ARMv81MML_DSP_DP_MVE_FP"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-A5 ****************************** --> |
| <family Dfamily="ARM Cortex A5" Dvendor="ARM:82"> |
| <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/> |
| <description> |
| The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full |
| virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit |
| Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. |
| </description> |
| |
| <memory id="IROM1" start="0x00000000" size="0x04000000" startup="1" default="1"/> <!-- 64MB NOR --> |
| <memory id="IROM2" start="0x0C000000" size="0x04000000" startup="0" default="0"/> <!-- 64MB NOR --> |
| <memory id="IRAM1" start="0x14000000" size="0x02000000" init ="0" default="1"/> <!-- 32MB SRAM --> |
| <memory id="IRAM2" start="0x80000000" size="0x40000000" init ="0" default="0"/> <!-- 1GB DRAM --> |
| |
| <device Dname="ARMCA5"> |
| <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/> |
| <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-A7 ****************************** --> |
| <family Dfamily="ARM Cortex A7" Dvendor="ARM:82"> |
| <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/> |
| <description> |
| The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture. |
| The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem, |
| an optional integrated GIC, and an optional L2 cache controller. |
| </description> |
| |
| <memory id="IROM1" start="0x00000000" size="0x04000000" startup="1" default="1"/> <!-- 64MB NOR --> |
| <memory id="IROM2" start="0x0C000000" size="0x04000000" startup="0" default="0"/> <!-- 64MB NOR --> |
| <memory id="IRAM1" start="0x14000000" size="0x02000000" init ="0" default="1"/> <!-- 32MB SRAM --> |
| <memory id="IRAM2" start="0x80000000" size="0x40000000" init ="0" default="0"/> <!-- 1GB DRAM --> |
| |
| <device Dname="ARMCA7"> |
| <processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/> |
| <compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/> |
| </device> |
| </family> |
| |
| <!-- ****************************** Cortex-A9 ****************************** --> |
| <family Dfamily="ARM Cortex A9" Dvendor="ARM:82"> |
| <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/> |
| <description> |
| The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. |
| The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, |
| and 8-bit Java bytecodes in Jazelle state. |
| </description> |
| |
| <memory id="IROM1" start="0x00000000" size="0x04000000" startup="1" default="1"/> <!-- 64MB NOR --> |
| <memory id="IROM2" start="0x0C000000" size="0x04000000" startup="0" default="0"/> <!-- 64MB NOR --> |
| <memory id="IRAM1" start="0x14000000" size="0x02000000" init ="0" default="1"/> <!-- 32MB SRAM --> |
| <memory id="IRAM2" start="0x80000000" size="0x40000000" init ="0" default="0"/> <!-- 1GB DRAM --> |
| |
| <device Dname="ARMCA9"> |
| <processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/> |
| <compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/> |
| </device> |
| </family> |
| </devices> |
| |
| |
| <apis> |
| <!-- CMSIS Device API --> |
| <api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1"> |
| <description>Device interrupt controller interface</description> |
| <files> |
| <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/> |
| </files> |
| </api> |
| <api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1"> |
| <description>RTOS Kernel system tick timer interface</description> |
| <files> |
| <file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/> |
| </files> |
| </api> |
| <!-- CMSIS-RTOS API --> |
| <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1"> |
| <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/> |
| </files> |
| </api> |
| <api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.3" exclusive="1"> |
| <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/> |
| <file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/> |
| </files> |
| </api> |
| <!-- CMSIS Driver API --> |
| <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0"> |
| <description>USART Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_USART.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0"> |
| <description>SPI Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0"> |
| <description>SAI Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/> |
| <file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0"> |
| <description>I2C Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/> |
| <file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0"> |
| <description>CAN Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/> |
| <file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.2.0" exclusive="0"> |
| <description>Flash Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0"> |
| <description>MCI Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0"> |
| <description>NAND Flash Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0"> |
| <description>Ethernet MAC and PHY Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0"> |
| <description>Ethernet MAC Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0"> |
| <description>Ethernet PHY Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0"> |
| <description>USB Device Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0"> |
| <description>USB Host Driver API for Cortex-M</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" /> |
| </files> |
| </api> |
| <api Cclass="CMSIS Driver" Cgroup="WiFi" Capiversion="1.0.0" exclusive="0"> |
| <description>WiFi driver</description> |
| <files> |
| <file category="doc" name="CMSIS/Documentation/Driver/html/group__wifi__interface__gr.html" /> |
| <file category="header" name="CMSIS/Driver/Include/Driver_WiFi.h" /> |
| </files> |
| </api> |
| </apis> |
| |
| <!-- conditions are dependency rules that can apply to a component or an individual file --> |
| <conditions> |
| <!-- compiler --> |
| <condition id="ARMCC6"> |
| <accept Tcompiler="ARMCC" Toptions="AC6"/> |
| <accept Tcompiler="ARMCC" Toptions="AC6LTO"/> |
| </condition> |
| <condition id="ARMCC5"> |
| <require Tcompiler="ARMCC" Toptions="AC5"/> |
| </condition> |
| <condition id="ARMCC"> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="GCC"> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="IAR"> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="ARMCC GCC"> |
| <accept Tcompiler="ARMCC"/> |
| <accept Tcompiler="GCC"/> |
| </condition> |
| <condition id="ARMCC GCC IAR"> |
| <accept Tcompiler="ARMCC"/> |
| <accept Tcompiler="GCC"/> |
| <accept Tcompiler="IAR"/> |
| </condition> |
| |
| <!-- Arm architecture --> |
| <condition id="ARMv6-M Device"> |
| <description>Armv6-M architecture based device</description> |
| <accept Dcore="Cortex-M0"/> |
| <accept Dcore="Cortex-M1"/> |
| <accept Dcore="Cortex-M0+"/> |
| <accept Dcore="SC000"/> |
| </condition> |
| <condition id="ARMv7-M Device"> |
| <description>Armv7-M architecture based device</description> |
| <accept Dcore="Cortex-M3"/> |
| <accept Dcore="Cortex-M4"/> |
| <accept Dcore="Cortex-M7"/> |
| <accept Dcore="SC300"/> |
| </condition> |
| <condition id="ARMv8-M Device"> |
| <description>Armv8-M architecture based device</description> |
| <accept Dcore="ARMV8MBL"/> |
| <accept Dcore="ARMV8MML"/> |
| <accept Dcore="ARMV81MML"/> |
| <accept Dcore="Cortex-M23"/> |
| <accept Dcore="Cortex-M33"/> |
| <accept Dcore="Cortex-M35P"/> |
| </condition> |
| <condition id="ARMv8-M TZ Device"> |
| <description>Armv8-M architecture based device with TrustZone</description> |
| <require condition="ARMv8-M Device"/> |
| <require Dtz="TZ"/> |
| </condition> |
| <condition id="ARMv6_7-M Device"> |
| <description>Armv6_7-M architecture based device</description> |
| <accept condition="ARMv6-M Device"/> |
| <accept condition="ARMv7-M Device"/> |
| </condition> |
| <condition id="ARMv6_7_8-M Device"> |
| <description>Armv6_7_8-M architecture based device</description> |
| <accept condition="ARMv6-M Device"/> |
| <accept condition="ARMv7-M Device"/> |
| <accept condition="ARMv8-M Device"/> |
| </condition> |
| <condition id="ARMv7-A Device"> |
| <description>Armv7-A architecture based device</description> |
| <accept Dcore="Cortex-A5"/> |
| <accept Dcore="Cortex-A7"/> |
| <accept Dcore="Cortex-A9"/> |
| </condition> |
| |
| <!-- ARM core --> |
| <condition id="CM0"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description> |
| <accept Dcore="Cortex-M0"/> |
| <accept Dcore="Cortex-M0+"/> |
| <accept Dcore="SC000"/> |
| </condition> |
| <condition id="CM1"> |
| <description>Cortex-M1</description> |
| <require Dcore="Cortex-M1"/> |
| </condition> |
| <condition id="CM3"> |
| <description>Cortex-M3 or SC300 processor based device</description> |
| <accept Dcore="Cortex-M3"/> |
| <accept Dcore="SC300"/> |
| </condition> |
| <condition id="CM4"> |
| <description>Cortex-M4 processor based device</description> |
| <require Dcore="Cortex-M4" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="CM4_FP"> |
| <description>Cortex-M4 processor based device using Floating Point Unit</description> |
| <accept Dcore="Cortex-M4" Dfpu="FPU"/> |
| <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/> |
| <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/> |
| </condition> |
| <condition id="CM7"> |
| <description>Cortex-M7 processor based device</description> |
| <require Dcore="Cortex-M7" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="CM7_FP"> |
| <description>Cortex-M7 processor based device using Floating Point Unit</description> |
| <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/> |
| <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/> |
| </condition> |
| <condition id="CM7_SP"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description> |
| <require Dcore="Cortex-M7" Dfpu="SP_FPU"/> |
| </condition> |
| <condition id="CM7_DP"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description> |
| <require Dcore="Cortex-M7" Dfpu="DP_FPU"/> |
| </condition> |
| <condition id="CM23"> |
| <description>Cortex-M23 processor based device</description> |
| <require Dcore="Cortex-M23"/> |
| </condition> |
| <condition id="CM33"> |
| <description>Cortex-M33 processor based device</description> |
| <require Dcore="Cortex-M33" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="CM33_FP"> |
| <description>Cortex-M33 processor based device using Floating Point Unit</description> |
| <require Dcore="Cortex-M33" Dfpu="SP_FPU"/> |
| </condition> |
| <condition id="CM35P"> |
| <description>Cortex-M35P processor based device</description> |
| <require Dcore="Cortex-M35P" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="CM35P_FP"> |
| <description>Cortex-M35P processor based device using Floating Point Unit</description> |
| <require Dcore="Cortex-M35P" Dfpu="SP_FPU"/> |
| </condition> |
| <condition id="ARMv8MBL"> |
| <description>Armv8-M Baseline processor based device</description> |
| <require Dcore="ARMV8MBL"/> |
| </condition> |
| <condition id="ARMv8MML"> |
| <description>Armv8-M Mainline processor based device</description> |
| <require Dcore="ARMV8MML" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="ARMv8MML_FP"> |
| <description>Armv8-M Mainline processor based device using Floating Point Unit</description> |
| <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/> |
| <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/> |
| </condition> |
| |
| <condition id="CM33_NODSP_NOFPU"> |
| <description>CM33, no DSP, no FPU</description> |
| <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="CM33_DSP_NOFPU"> |
| <description>CM33, DSP, no FPU</description> |
| <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="CM33_NODSP_SP"> |
| <description>CM33, no DSP, SP FPU</description> |
| <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/> |
| </condition> |
| <condition id="CM33_DSP_SP"> |
| <description>CM33, DSP, SP FPU</description> |
| <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/> |
| </condition> |
| |
| <condition id="CM35P_NODSP_NOFPU"> |
| <description>CM35P, no DSP, no FPU</description> |
| <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="CM35P_DSP_NOFPU"> |
| <description>CM35P, DSP, no FPU</description> |
| <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="CM35P_NODSP_SP"> |
| <description>CM35P, no DSP, SP FPU</description> |
| <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="SP_FPU"/> |
| </condition> |
| <condition id="CM35P_DSP_SP"> |
| <description>CM35P, DSP, SP FPU</description> |
| <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="SP_FPU"/> |
| </condition> |
| |
| <condition id="ARMv8MML_NODSP_NOFPU"> |
| <description>Armv8-M Mainline, no DSP, no FPU</description> |
| <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_NOFPU"> |
| <description>Armv8-M Mainline, DSP, no FPU</description> |
| <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_SP"> |
| <description>Armv8-M Mainline, no DSP, SP FPU</description> |
| <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_SP"> |
| <description>Armv8-M Mainline, DSP, SP FPU</description> |
| <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/> |
| </condition> |
| |
| <condition id="CA5_CA9"> |
| <description>Cortex-A5 or Cortex-A9 processor based device</description> |
| <accept Dcore="Cortex-A5"/> |
| <accept Dcore="Cortex-A9"/> |
| </condition> |
| |
| <condition id="CA7"> |
| <description>Cortex-A7 processor based device</description> |
| <accept Dcore="Cortex-A7"/> |
| </condition> |
| |
| <!-- ARMCC compiler --> |
| <condition id="CA_ARMCC5"> |
| <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description> |
| <require condition="ARMv7-A Device"/> |
| <require condition="ARMCC5"/> |
| </condition> |
| <condition id="CA_ARMCC6"> |
| <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description> |
| <require condition="ARMv7-A Device"/> |
| <require condition="ARMCC6"/> |
| </condition> |
| |
| <condition id="CM0_ARMCC"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description> |
| <require condition="CM0"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM0_LE_ARMCC"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="CM0_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM0_BE_ARMCC"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description> |
| <require condition="CM0_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM1_ARMCC"> |
| <description>Cortex-M1 based device for the Arm Compiler</description> |
| <require condition="CM1"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM1_LE_ARMCC"> |
| <description>Cortex-M1 based device in little endian mode for the Arm Compiler</description> |
| <require condition="CM1_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM1_BE_ARMCC"> |
| <description>Cortex-M1 based device in big endian mode for the Arm Compiler</description> |
| <require condition="CM1_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM3_ARMCC"> |
| <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description> |
| <require condition="CM3"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM3_LE_ARMCC"> |
| <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="CM3_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM3_BE_ARMCC"> |
| <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description> |
| <require condition="CM3_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM4_ARMCC"> |
| <description>Cortex-M4 processor based device for the Arm Compiler</description> |
| <require condition="CM4"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM4_LE_ARMCC"> |
| <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="CM4_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM4_BE_ARMCC"> |
| <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description> |
| <require condition="CM4_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM4_FP_ARMCC"> |
| <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description> |
| <require condition="CM4_FP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM4_FP_LE_ARMCC"> |
| <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description> |
| <require condition="CM4_FP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM4_FP_BE_ARMCC"> |
| <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description> |
| <require condition="CM4_FP_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_ARMCC"> |
| <description>Cortex-M7 processor based device for the Arm Compiler</description> |
| <require condition="CM7"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM7_LE_ARMCC"> |
| <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="CM7_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_BE_ARMCC"> |
| <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description> |
| <require condition="CM7_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_FP_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description> |
| <require condition="CM7_FP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM7_FP_LE_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description> |
| <require condition="CM7_FP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_FP_BE_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description> |
| <require condition="CM7_FP_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_SP_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description> |
| <require condition="CM7_SP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM7_SP_LE_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description> |
| <require condition="CM7_SP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_SP_BE_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description> |
| <require condition="CM7_SP_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_DP_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description> |
| <require condition="CM7_DP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM7_DP_LE_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description> |
| <require condition="CM7_DP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_DP_BE_ARMCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description> |
| <require condition="CM7_DP_ARMCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM23_ARMCC"> |
| <description>Cortex-M23 processor based device for the Arm Compiler</description> |
| <require condition="CM23"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM23_LE_ARMCC"> |
| <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="CM23_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_ARMCC"> |
| <description>Cortex-M33 processor based device for the Arm Compiler</description> |
| <require condition="CM33"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM33_LE_ARMCC"> |
| <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="CM33_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_FP_ARMCC"> |
| <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description> |
| <require condition="CM33_FP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM33_FP_LE_ARMCC"> |
| <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description> |
| <require condition="CM33_FP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_NODSP_NOFPU_ARMCC"> |
| <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description> |
| <require condition="CM33_NODSP_NOFPU"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM33_DSP_NOFPU_ARMCC"> |
| <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description> |
| <require condition="CM33_DSP_NOFPU"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM33_NODSP_SP_ARMCC"> |
| <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description> |
| <require condition="CM33_NODSP_SP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM33_DSP_SP_ARMCC"> |
| <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description> |
| <require condition="CM33_DSP_SP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM33_NODSP_NOFPU_LE_ARMCC"> |
| <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description> |
| <require condition="CM33_NODSP_NOFPU_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_DSP_NOFPU_LE_ARMCC"> |
| <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description> |
| <require condition="CM33_DSP_NOFPU_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_NODSP_SP_LE_ARMCC"> |
| <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description> |
| <require condition="CM33_NODSP_SP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_DSP_SP_LE_ARMCC"> |
| <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description> |
| <require condition="CM33_DSP_SP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_ARMCC"> |
| <description>Cortex-M35P processor based device for the Arm Compiler</description> |
| <require condition="CM35P"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM35P_LE_ARMCC"> |
| <description>Cortex-M35P processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="CM35P_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_FP_ARMCC"> |
| <description>Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler</description> |
| <require condition="CM35P_FP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM35P_FP_LE_ARMCC"> |
| <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description> |
| <require condition="CM35P_FP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_NODSP_NOFPU_ARMCC"> |
| <description>Cortex-M35P processor, no DSP, no FPU, Arm Compiler</description> |
| <require condition="CM35P_NODSP_NOFPU"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM35P_DSP_NOFPU_ARMCC"> |
| <description>Cortex-M35P processor, DSP, no FPU, Arm Compiler</description> |
| <require condition="CM35P_DSP_NOFPU"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM35P_NODSP_SP_ARMCC"> |
| <description>Cortex-M35P processor, no DSP, SP FPU, Arm Compiler</description> |
| <require condition="CM35P_NODSP_SP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM35P_DSP_SP_ARMCC"> |
| <description>Cortex-M35P processor, DSP, SP FPU, Arm Compiler</description> |
| <require condition="CM35P_DSP_SP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="CM35P_NODSP_NOFPU_LE_ARMCC"> |
| <description>Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler</description> |
| <require condition="CM35P_NODSP_NOFPU_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_DSP_NOFPU_LE_ARMCC"> |
| <description>Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler</description> |
| <require condition="CM35P_DSP_NOFPU_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_NODSP_SP_LE_ARMCC"> |
| <description>Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler</description> |
| <require condition="CM35P_NODSP_SP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_DSP_SP_LE_ARMCC"> |
| <description>Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler</description> |
| <require condition="CM35P_DSP_SP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MBL_ARMCC"> |
| <description>Armv8-M Baseline processor based device for the Arm Compiler</description> |
| <require condition="ARMv8MBL"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="ARMv8MBL_LE_ARMCC"> |
| <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="ARMv8MBL_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_ARMCC"> |
| <description>Armv8-M Mainline processor based device for the Arm Compiler</description> |
| <require condition="ARMv8MML"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="ARMv8MML_LE_ARMCC"> |
| <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description> |
| <require condition="ARMv8MML_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_FP_ARMCC"> |
| <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description> |
| <require condition="ARMv8MML_FP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="ARMv8MML_FP_LE_ARMCC"> |
| <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description> |
| <require condition="ARMv8MML_FP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_NODSP_NOFPU_ARMCC"> |
| <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description> |
| <require condition="ARMv8MML_NODSP_NOFPU"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_NOFPU_ARMCC"> |
| <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description> |
| <require condition="ARMv8MML_DSP_NOFPU"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_SP_ARMCC"> |
| <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description> |
| <require condition="ARMv8MML_NODSP_SP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_SP_ARMCC"> |
| <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description> |
| <require condition="ARMv8MML_DSP_SP"/> |
| <require Tcompiler="ARMCC"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC"> |
| <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description> |
| <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC"> |
| <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description> |
| <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_SP_LE_ARMCC"> |
| <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description> |
| <require condition="ARMv8MML_NODSP_SP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_SP_LE_ARMCC"> |
| <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description> |
| <require condition="ARMv8MML_DSP_SP_ARMCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <!-- GCC compiler --> |
| <condition id="CA_GCC"> |
| <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description> |
| <require condition="ARMv7-A Device"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| |
| <condition id="CM0_GCC"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description> |
| <require condition="CM0"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM0_LE_GCC"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="CM0_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM0_BE_GCC"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description> |
| <require condition="CM0_GCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM1_GCC"> |
| <description>Cortex-M1 based device for the GCC Compiler</description> |
| <require condition="CM1"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM1_LE_GCC"> |
| <description>Cortex-M1 based device in little endian mode for the GCC Compiler</description> |
| <require condition="CM1_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM1_BE_GCC"> |
| <description>Cortex-M1 based device in big endian mode for the GCC Compiler</description> |
| <require condition="CM1_GCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM3_GCC"> |
| <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description> |
| <require condition="CM3"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM3_LE_GCC"> |
| <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="CM3_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM3_BE_GCC"> |
| <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description> |
| <require condition="CM3_GCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM4_GCC"> |
| <description>Cortex-M4 processor based device for the GCC Compiler</description> |
| <require condition="CM4"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM4_LE_GCC"> |
| <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="CM4_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM4_BE_GCC"> |
| <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description> |
| <require condition="CM4_GCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM4_FP_GCC"> |
| <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description> |
| <require condition="CM4_FP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM4_FP_LE_GCC"> |
| <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description> |
| <require condition="CM4_FP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM4_FP_BE_GCC"> |
| <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description> |
| <require condition="CM4_FP_GCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_GCC"> |
| <description>Cortex-M7 processor based device for the GCC Compiler</description> |
| <require condition="CM7"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM7_LE_GCC"> |
| <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="CM7_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_BE_GCC"> |
| <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description> |
| <require condition="CM7_GCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_FP_GCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description> |
| <require condition="CM7_FP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM7_FP_LE_GCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description> |
| <require condition="CM7_FP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_FP_BE_GCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description> |
| <require condition="CM7_FP_GCC"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_SP_GCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description> |
| <require condition="CM7_SP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM7_SP_LE_GCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description> |
| <require condition="CM7_SP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM7_DP_GCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description> |
| <require condition="CM7_DP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM7_DP_LE_GCC"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description> |
| <require condition="CM7_DP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM23_GCC"> |
| <description>Cortex-M23 processor based device for the GCC Compiler</description> |
| <require condition="CM23"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM23_LE_GCC"> |
| <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="CM23_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_GCC"> |
| <description>Cortex-M33 processor based device for the GCC Compiler</description> |
| <require condition="CM33"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM33_LE_GCC"> |
| <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="CM33_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_FP_GCC"> |
| <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description> |
| <require condition="CM33_FP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM33_FP_LE_GCC"> |
| <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description> |
| <require condition="CM33_FP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_NODSP_NOFPU_GCC"> |
| <description>CM33, no DSP, no FPU, GCC Compiler</description> |
| <require condition="CM33_NODSP_NOFPU"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM33_DSP_NOFPU_GCC"> |
| <description>CM33, DSP, no FPU, GCC Compiler</description> |
| <require condition="CM33_DSP_NOFPU"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM33_NODSP_SP_GCC"> |
| <description>CM33, no DSP, SP FPU, GCC Compiler</description> |
| <require condition="CM33_NODSP_SP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM33_DSP_SP_GCC"> |
| <description>CM33, DSP, SP FPU, GCC Compiler</description> |
| <require condition="CM33_DSP_SP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM33_NODSP_NOFPU_LE_GCC"> |
| <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description> |
| <require condition="CM33_NODSP_NOFPU_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_DSP_NOFPU_LE_GCC"> |
| <description>CM33, little endian, DSP, no FPU, GCC Compiler</description> |
| <require condition="CM33_DSP_NOFPU_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_NODSP_SP_LE_GCC"> |
| <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description> |
| <require condition="CM33_NODSP_SP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_DSP_SP_LE_GCC"> |
| <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description> |
| <require condition="CM33_DSP_SP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_GCC"> |
| <description>Cortex-M35P processor based device for the GCC Compiler</description> |
| <require condition="CM35P"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM35P_LE_GCC"> |
| <description>Cortex-M35P processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="CM35P_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_FP_GCC"> |
| <description>Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler</description> |
| <require condition="CM35P_FP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM35P_FP_LE_GCC"> |
| <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description> |
| <require condition="CM35P_FP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_NODSP_NOFPU_GCC"> |
| <description>CM35P, no DSP, no FPU, GCC Compiler</description> |
| <require condition="CM35P_NODSP_NOFPU"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM35P_DSP_NOFPU_GCC"> |
| <description>CM35P, DSP, no FPU, GCC Compiler</description> |
| <require condition="CM35P_DSP_NOFPU"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM35P_NODSP_SP_GCC"> |
| <description>CM35P, no DSP, SP FPU, GCC Compiler</description> |
| <require condition="CM35P_NODSP_SP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM35P_DSP_SP_GCC"> |
| <description>CM35P, DSP, SP FPU, GCC Compiler</description> |
| <require condition="CM35P_DSP_SP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="CM35P_NODSP_NOFPU_LE_GCC"> |
| <description>CM35P, little endian, no DSP, no FPU, GCC Compiler</description> |
| <require condition="CM35P_NODSP_NOFPU_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_DSP_NOFPU_LE_GCC"> |
| <description>CM35P, little endian, DSP, no FPU, GCC Compiler</description> |
| <require condition="CM35P_DSP_NOFPU_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_NODSP_SP_LE_GCC"> |
| <description>CM35P, little endian, no DSP, SP FPU, GCC Compiler</description> |
| <require condition="CM35P_NODSP_SP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_DSP_SP_LE_GCC"> |
| <description>CM35P, little endian, DSP, SP FPU, GCC Compiler</description> |
| <require condition="CM35P_DSP_SP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MBL_GCC"> |
| <description>Armv8-M Baseline processor based device for the GCC Compiler</description> |
| <require condition="ARMv8MBL"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="ARMv8MBL_LE_GCC"> |
| <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="ARMv8MBL_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_GCC"> |
| <description>Armv8-M Mainline processor based device for the GCC Compiler</description> |
| <require condition="ARMv8MML"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="ARMv8MML_LE_GCC"> |
| <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description> |
| <require condition="ARMv8MML_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_FP_GCC"> |
| <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description> |
| <require condition="ARMv8MML_FP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="ARMv8MML_FP_LE_GCC"> |
| <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description> |
| <require condition="ARMv8MML_FP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_NODSP_NOFPU_GCC"> |
| <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description> |
| <require condition="ARMv8MML_NODSP_NOFPU"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_NOFPU_GCC"> |
| <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description> |
| <require condition="ARMv8MML_DSP_NOFPU"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_SP_GCC"> |
| <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description> |
| <require condition="ARMv8MML_NODSP_SP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_SP_GCC"> |
| <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description> |
| <require condition="ARMv8MML_DSP_SP"/> |
| <require Tcompiler="GCC"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC"> |
| <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description> |
| <require condition="ARMv8MML_NODSP_NOFPU_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_NOFPU_LE_GCC"> |
| <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description> |
| <require condition="ARMv8MML_DSP_NOFPU_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_SP_LE_GCC"> |
| <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description> |
| <require condition="ARMv8MML_NODSP_SP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_SP_LE_GCC"> |
| <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description> |
| <require condition="ARMv8MML_DSP_SP_GCC"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <!-- IAR compiler --> |
| <condition id="CA_IAR"> |
| <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description> |
| <require condition="ARMv7-A Device"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| |
| <condition id="CM0_IAR"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description> |
| <require condition="CM0"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM0_LE_IAR"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="CM0_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM0_BE_IAR"> |
| <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description> |
| <require condition="CM0_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM1_IAR"> |
| <description>Cortex-M1 based device for the IAR Compiler</description> |
| <require condition="CM1"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM1_LE_IAR"> |
| <description>Cortex-M1 based device in little endian mode for the IAR Compiler</description> |
| <require condition="CM1_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM1_BE_IAR"> |
| <description>Cortex-M1 based device in big endian mode for the IAR Compiler</description> |
| <require condition="CM1_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM3_IAR"> |
| <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description> |
| <require condition="CM3"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM3_LE_IAR"> |
| <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="CM3_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM3_BE_IAR"> |
| <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description> |
| <require condition="CM3_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM4_IAR"> |
| <description>Cortex-M4 processor based device for the IAR Compiler</description> |
| <require condition="CM4"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM4_LE_IAR"> |
| <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="CM4_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM4_BE_IAR"> |
| <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description> |
| <require condition="CM4_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM4_FP_IAR"> |
| <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description> |
| <require condition="CM4_FP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM4_FP_LE_IAR"> |
| <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description> |
| <require condition="CM4_FP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM4_FP_BE_IAR"> |
| <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description> |
| <require condition="CM4_FP_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_IAR"> |
| <description>Cortex-M7 processor based device for the IAR Compiler</description> |
| <require condition="CM7"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM7_LE_IAR"> |
| <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="CM7_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_BE_IAR"> |
| <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description> |
| <require condition="CM7_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_FP_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description> |
| <require condition="CM7_FP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM7_FP_LE_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description> |
| <require condition="CM7_FP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_FP_BE_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description> |
| <require condition="CM7_FP_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_SP_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description> |
| <require condition="CM7_SP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM7_SP_LE_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description> |
| <require condition="CM7_SP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_SP_BE_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description> |
| <require condition="CM7_SP_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM7_DP_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description> |
| <require condition="CM7_DP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM7_DP_LE_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description> |
| <require condition="CM7_DP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM7_DP_BE_IAR"> |
| <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description> |
| <require condition="CM7_DP_IAR"/> |
| <require Dendian="Big-endian"/> |
| </condition> |
| |
| <condition id="CM23_IAR"> |
| <description>Cortex-M23 processor based device for the IAR Compiler</description> |
| <require condition="CM23"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM23_LE_IAR"> |
| <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="CM23_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_IAR"> |
| <description>Cortex-M33 processor based device for the IAR Compiler</description> |
| <require condition="CM33"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM33_LE_IAR"> |
| <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="CM33_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_FP_IAR"> |
| <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description> |
| <require condition="CM33_FP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM33_FP_LE_IAR"> |
| <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description> |
| <require condition="CM33_FP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM33_NODSP_NOFPU_IAR"> |
| <description>CM33, no DSP, no FPU, IAR Compiler</description> |
| <require condition="CM33_NODSP_NOFPU"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM33_DSP_NOFPU_IAR"> |
| <description>CM33, DSP, no FPU, IAR Compiler</description> |
| <require condition="CM33_DSP_NOFPU"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM33_NODSP_SP_IAR"> |
| <description>CM33, no DSP, SP FPU, IAR Compiler</description> |
| <require condition="CM33_NODSP_SP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM33_DSP_SP_IAR"> |
| <description>CM33, DSP, SP FPU, IAR Compiler</description> |
| <require condition="CM33_DSP_SP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM33_NODSP_NOFPU_LE_IAR"> |
| <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description> |
| <require condition="CM33_NODSP_NOFPU_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_DSP_NOFPU_LE_IAR"> |
| <description>CM33, little endian, DSP, no FPU, IAR Compiler</description> |
| <require condition="CM33_DSP_NOFPU_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_NODSP_SP_LE_IAR"> |
| <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description> |
| <require condition="CM33_NODSP_SP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM33_DSP_SP_LE_IAR"> |
| <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description> |
| <require condition="CM33_DSP_SP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_IAR"> |
| <description>Cortex-M35P processor based device for the IAR Compiler</description> |
| <require condition="CM35P"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM35P_LE_IAR"> |
| <description>Cortex-M35P processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="CM35P_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_FP_IAR"> |
| <description>Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler</description> |
| <require condition="CM35P_FP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM35P_FP_LE_IAR"> |
| <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description> |
| <require condition="CM35P_FP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="CM35P_NODSP_NOFPU_IAR"> |
| <description>CM35P, no DSP, no FPU, IAR Compiler</description> |
| <require condition="CM35P_NODSP_NOFPU"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM35P_DSP_NOFPU_IAR"> |
| <description>CM35P, DSP, no FPU, IAR Compiler</description> |
| <require condition="CM35P_DSP_NOFPU"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM35P_NODSP_SP_IAR"> |
| <description>CM35P, no DSP, SP FPU, IAR Compiler</description> |
| <require condition="CM35P_NODSP_SP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM35P_DSP_SP_IAR"> |
| <description>CM35P, DSP, SP FPU, IAR Compiler</description> |
| <require condition="CM35P_DSP_SP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="CM35P_NODSP_NOFPU_LE_IAR"> |
| <description>CM35P, little endian, no DSP, no FPU, IAR Compiler</description> |
| <require condition="CM35P_NODSP_NOFPU_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_DSP_NOFPU_LE_IAR"> |
| <description>CM35P, little endian, DSP, no FPU, IAR Compiler</description> |
| <require condition="CM35P_DSP_NOFPU_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_NODSP_SP_LE_IAR"> |
| <description>CM35P, little endian, no DSP, SP FPU, IAR Compiler</description> |
| <require condition="CM35P_NODSP_SP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="CM35P_DSP_SP_LE_IAR"> |
| <description>CM35P, little endian, DSP, SP FPU, IAR Compiler</description> |
| <require condition="CM35P_DSP_SP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MBL_IAR"> |
| <description>Armv8-M Baseline processor based device for the IAR Compiler</description> |
| <require condition="ARMv8MBL"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="ARMv8MBL_LE_IAR"> |
| <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="ARMv8MBL_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_IAR"> |
| <description>Armv8-M Mainline processor based device for the IAR Compiler</description> |
| <require condition="ARMv8MML"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="ARMv8MML_LE_IAR"> |
| <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description> |
| <require condition="ARMv8MML_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_FP_IAR"> |
| <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description> |
| <require condition="ARMv8MML_FP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="ARMv8MML_FP_LE_IAR"> |
| <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description> |
| <require condition="ARMv8MML_FP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <condition id="ARMv8MML_NODSP_NOFPU_IAR"> |
| <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description> |
| <require condition="ARMv8MML_NODSP_NOFPU"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_NOFPU_IAR"> |
| <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description> |
| <require condition="ARMv8MML_DSP_NOFPU"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_SP_IAR"> |
| <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description> |
| <require condition="ARMv8MML_NODSP_SP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_SP_IAR"> |
| <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description> |
| <require condition="ARMv8MML_DSP_SP"/> |
| <require Tcompiler="IAR"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR"> |
| <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description> |
| <require condition="ARMv8MML_NODSP_NOFPU_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_NOFPU_LE_IAR"> |
| <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description> |
| <require condition="ARMv8MML_DSP_NOFPU_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_NODSP_SP_LE_IAR"> |
| <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description> |
| <require condition="ARMv8MML_NODSP_SP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| <condition id="ARMv8MML_DSP_SP_LE_IAR"> |
| <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description> |
| <require condition="ARMv8MML_DSP_SP_IAR"/> |
| <require Dendian="Little-endian"/> |
| </condition> |
| |
| <!-- conditions selecting single devices and CMSIS Core --> |
| <condition id="ARMCM0 CMSIS"> |
| <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM0"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCM0+ CMSIS"> |
| <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM0P*"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCM1 CMSIS"> |
| <description>Generic Arm Cortex-M1 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM1"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCM3 CMSIS"> |
| <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM3"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCM4 CMSIS"> |
| <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM4*"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCM7 CMSIS"> |
| <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM7*"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCM23 CMSIS"> |
| <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM23*"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCM33 CMSIS"> |
| <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM33*"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCM35P CMSIS"> |
| <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCM35P*"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMSC000 CMSIS"> |
| <description>Generic Arm SC000 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMSC000"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMSC300 CMSIS"> |
| <description>Generic Arm SC300 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMSC300"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMv8MBL CMSIS"> |
| <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMv8MBL"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMv8MML CMSIS"> |
| <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMv8MML*"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMv81MML CMSIS"> |
| <description>Generic Armv8.1-M Mainline device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMv81MML*"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCA5 CMSIS"> |
| <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCA5"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCA7 CMSIS"> |
| <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCA7"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <condition id="ARMCA9 CMSIS"> |
| <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description> |
| <require Dvendor="ARM:82" Dname="ARMCA9"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <!-- CMSIS DSP --> |
| <condition id="CMSIS DSP"> |
| <description>Components required for DSP</description> |
| <require condition="ARMv6_7_8-M Device"/> |
| <require condition="ARMCC GCC IAR"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| </condition> |
| |
| <!-- CMSIS NN --> |
| <condition id="CMSIS NN"> |
| <description>Components required for NN</description> |
| <require condition="CMSIS DSP"/> |
| </condition> |
| |
| <!-- RTOS RTX --> |
| <condition id="RTOS RTX"> |
| <description>Components required for RTOS RTX</description> |
| <require condition="ARMv6_7-M Device"/> |
| <require condition="ARMCC GCC IAR"/> |
| <require Cclass="Device" Cgroup="Startup"/> |
| <deny Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5"/> |
| </condition> |
| <condition id="RTOS RTX IFX"> |
| <description>Components required for RTOS RTX IFX</description> |
| <require condition="ARMv6_7-M Device"/> |
| <require condition="ARMCC GCC IAR"/> |
| <require Dvendor="Infineon:7" Dname="XMC4*"/> |
| <require Cclass="Device" Cgroup="Startup"/> |
| <deny Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5"/> |
| </condition> |
| <condition id="RTOS RTX5"> |
| <description>Components required for RTOS RTX5</description> |
| <require condition="ARMv6_7_8-M Device"/> |
| <require condition="ARMCC GCC IAR"/> |
| <require Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5"/> |
| </condition> |
| <condition id="RTOS2 RTX5"> |
| <description>Components required for RTOS2 RTX5</description> |
| <require condition="ARMv6_7_8-M Device"/> |
| <require condition="ARMCC GCC IAR"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| <require Cclass="Device" Cgroup="Startup"/> |
| </condition> |
| <condition id="RTOS2 RTX5 v7-A"> |
| <description>Components required for RTOS2 RTX5 on Armv7-A</description> |
| <require condition="ARMv7-A Device"/> |
| <require condition="ARMCC GCC IAR"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| <require Cclass="Device" Cgroup="Startup"/> |
| <require Cclass="Device" Cgroup="OS Tick"/> |
| <require Cclass="Device" Cgroup="IRQ Controller"/> |
| </condition> |
| <condition id="RTOS2 RTX5 Lib"> |
| <description>Components required for RTOS2 RTX5 Library</description> |
| <require condition="ARMv6_7_8-M Device"/> |
| <require condition="ARMCC GCC IAR"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| <require Cclass="Device" Cgroup="Startup"/> |
| </condition> |
| <condition id="RTOS2 RTX5 NS"> |
| <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description> |
| <require condition="ARMv8-M TZ Device"/> |
| <require condition="ARMCC GCC IAR"/> |
| <require Cclass="CMSIS" Cgroup="CORE"/> |
| <require Cclass="Device" Cgroup="Startup"/> |
| </condition> |
| |
| <!-- OS Tick --> |
| <condition id="OS Tick PTIM"> |
| <description>Components required for OS Tick Private Timer</description> |
| <require condition="CA5_CA9"/> |
| <require Cclass="Device" Cgroup="IRQ Controller"/> |
| </condition> |
| |
| <condition id="OS Tick GTIM"> |
| <description>Components required for OS Tick Generic Physical Timer</description> |
| <require condition="CA7"/> |
| <require Cclass="Device" Cgroup="IRQ Controller"/> |
| </condition> |
| |
| </conditions> |
| |
| <components> |
| <!-- CMSIS-Core component --> |
| <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.3.0" condition="ARMv6_7_8-M Device" > |
| <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M</description> |
| <files> |
| <!-- CPU independent --> |
| <file category="doc" name="CMSIS/Documentation/Core/html/index.html"/> |
| <file category="include" name="CMSIS/Core/Include/"/> |
| <file category="header" name="CMSIS/Core/Include/tz_context.h" condition="ARMv8-M TZ Device"/> |
| <!-- Code template --> |
| <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c" version="1.1.1" select="Secure mode 'main' module for ARMv8-M"/> |
| <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.1" select="RTOS Context Management (TrustZone for ARMv8-M)" /> |
| </files> |
| </component> |
| |
| <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.4" condition="ARMv7-A Device" > |
| <description>CMSIS-CORE for Cortex-A</description> |
| <files> |
| <!-- CPU independent --> |
| <file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/> |
| <file category="include" name="CMSIS/Core_A/Include/"/> |
| </files> |
| </component> |
| |
| <!-- CMSIS-Startup components --> |
| <!-- Cortex-M0 --> |
| <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.0" condition="ARMCM0 CMSIS"> |
| <description>System and Startup for Generic Arm Cortex-M0 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="header" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/> |
| <!-- startup / system file --> |
| <file category="sourceC" name="Device/ARM/ARMCM0/Source/startup_ARMCM0.c" version="2.0.0" attr="config"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceC" name="Device/ARM/ARMCM0/Source/system_ARMCM0.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| <component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMCM0 CMSIS"> |
| <description>DEPRECATED: System and Startup for Generic Arm Cortex-M0 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="header" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/> |
| <!-- startup / system file --> |
| <file category="sourceAsm" name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/> |
| <file category="sourceC" name="Device/ARM/ARMCM0/Source/system_ARMCM0.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| |
| <!-- Cortex-M0+ --> |
| <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.0" condition="ARMCM0+ CMSIS"> |
| <description>System and Startup for Generic Arm Cortex-M0+ device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="header" name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/> |
| <!-- startup / system file --> |
| <file category="sourceC" name="Device/ARM/ARMCM0plus/Source/startup_ARMCM0plus.c" version="2.0.0" attr="config"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceC" name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| <component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMCM0+ CMSIS"> |
| <description>DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="header" name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/> |
| <!-- startup / system file --> |
| <file category="sourceAsm" name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/> |
| <file category="sourceC" name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| |
| <!-- Cortex-M1 --> |
| <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.0" condition="ARMCM1 CMSIS"> |
| <description>System and Startup for Generic Arm Cortex-M1 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="header" name="Device/ARM/ARMCM1/Include/ARMCM1.h"/> |
| <!-- startup / system file --> |
| <file category="sourceC" name="Device/ARM/ARMCM1/Source/startup_ARMCM1.c" version="2.0.0" attr="config"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceC" name="Device/ARM/ARMCM1/Source/system_ARMCM1.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| <component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMCM1 CMSIS"> |
| <description>DEPRECATED: System and Startup for Generic Arm Cortex-M1 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="header" name="Device/ARM/ARMCM1/Include/ARMCM1.h"/> |
| <!-- startup / system file --> |
| <file category="sourceAsm" name="Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s" version="1.0.0" attr="config" condition="ARMCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s" version="1.0.0" attr="config" condition="IAR"/> |
| <file category="sourceC" name="Device/ARM/ARMCM1/Source/system_ARMCM1.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| |
| <!-- Cortex-M3 --> |
| <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.0" condition="ARMCM3 CMSIS"> |
| <description>System and Startup for Generic Arm Cortex-M3 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="header" name="Device/ARM/ARMCM3/Include/ARMCM3.h"/> |
| <!-- startup / system file --> |
| <file category="sourceC" name="Device/ARM/ARMCM3/Source/startup_ARMCM3.c" version="2.0.0" attr="config"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceC" name="Device/ARM/ARMCM3/Source/system_ARMCM3.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| <component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMCM3 CMSIS"> |
| <description>DEPRECATED: System and Startup for Generic Arm Cortex-M3 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="header" name="Device/ARM/ARMCM3/Include/ARMCM3.h"/> |
| <!-- startup / system file --> |
| <file category="sourceAsm" name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/> |
| <file category="sourceC" name="Device/ARM/ARMCM3/Source/system_ARMCM3.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| |
| <!-- Cortex-M4 --> |
| <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.0" condition="ARMCM4 CMSIS"> |
| <description>System and Startup for Generic Arm Cortex-M4 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="include" name="Device/ARM/ARMCM4/Include/"/> |
| <!-- startup / system file --> |
| <file category="sourceC" name="Device/ARM/ARMCM4/Source/startup_ARMCM4.c" version="2.0.0" attr="config"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceC" name="Device/ARM/ARMCM4/Source/system_ARMCM4.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| <component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMCM4 CMSIS"> |
| <description>DEPRECATED: System and Startup for Generic Arm Cortex-M4 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="include" name="Device/ARM/ARMCM4/Include/"/> |
| <!-- startup / system file --> |
| <file category="sourceAsm" name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/> |
| <file category="sourceC" name="Device/ARM/ARMCM4/Source/system_ARMCM4.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| |
| <!-- Cortex-M7 --> |
| <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.0" condition="ARMCM7 CMSIS"> |
| <description>System and Startup for Generic Arm Cortex-M7 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="include" name="Device/ARM/ARMCM7/Include/"/> |
| <!-- startup / system file --> |
| <file category="sourceC" name="Device/ARM/ARMCM7/Source/startup_ARMCM7.c" version="2.0.0" attr="config"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceC" name="Device/ARM/ARMCM7/Source/system_ARMCM7.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| <component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMCM7 CMSIS"> |
| <description>DEPRECATED: System and Startup for Generic Arm Cortex-M7 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="include" name="Device/ARM/ARMCM7/Include/"/> |
| <!-- startup / system file --> |
| <file category="sourceAsm" name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/> |
| <file category="sourceC" name="Device/ARM/ARMCM7/Source/system_ARMCM7.c" version="1.0.0" attr="config"/> |
| </files> |
| </component> |
| |
| <!-- Cortex-M23 --> |
| <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.0" condition="ARMCM23 CMSIS"> |
| <description>System and Startup for Generic Arm Cortex-M23 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="include" name="Device/ARM/ARMCM23/Include/"/> |
| <!-- startup / system file --> |
| <file category="sourceC" name="Device/ARM/ARMCM23/Source/startup_ARMCM23.c" version="2.0.0" attr="config"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceC" name="Device/ARM/ARMCM23/Source/system_ARMCM23.c" version="1.0.0" attr="config"/> |
| <!-- SAU configuration --> |
| <file category="header" name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/> |
| </files> |
| </component> |
| <component Cclass="Device" Cgroup="Startup" Cversion="1.1.0" condition="ARMCM23 CMSIS"> |
| <description>DEPRECATED: System and Startup for Generic Arm Cortex-M23 device</description> |
| <files> |
| <!-- include folder / device header file --> |
| <file category="include" name="Device/ARM/ARMCM23/Include/"/> |
| <!-- startup / system file --> |
| <file category="sourceAsm" name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s" version="1.0.0" attr="config" condition="ARMCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld" version="2.0.0" attr="config" condition="GCC"/> |
| <file category="sourceAsm" name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.0.0" attr="config" condition="IAR"/> |
| <file category="sourceC" name="Device/ARM/ARMCM23/Source/system_ARMCM23.c" version="1.0.0" attr="config"/> |
| <!-- SAU configuration --> |
| <file category="header" name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr<
|
