Google Git
Sign in
pigweed / third_party / github / STMicroelectronics / cmsis_core / refs/heads/cm4 / . / docs / Core / html / device_h_pg.html
blob: 6f3dc2ec9ae03fec5962a54746dfb11830a2396f [file] [log] [blame] [edit]
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<title>Device Header File &lt;device.h&gt;</title>
<title>CMSIS-Core (Cortex-M): Device Header File &lt;device.h&gt;</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<link href="cmsis.css" rel="stylesheet" type="text/css" />
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<script type="text/javascript" src="printComponentTabs.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
$(document).ready(initResizable);
$(window).load(resizeHeight);
</script>
<link href="search/search.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="search/search.js"></script>
<script type="text/javascript">
$(document).ready(function() { searchBox.OnSelectItem(0); });
</script>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
<tbody>
<tr style="height: 46px;">
<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
<td style="padding-left: 0.5em;">
<div id="projectname">CMSIS-Core (Cortex-M)
&#160;<span id="projectnumber">Version 5.3.0</span>
</div>
<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
</td>
</tr>
</tbody>
</table>
</div>
<!-- end header part -->
<div id="CMSISnav" class="tabs1">
<ul class="tablist">
<script type="text/javascript">
<!--
writeComponentTabs.call(this);
//-->
</script>
</ul>
</div>
<!-- Generated by Doxygen 1.8.6 -->
<script type="text/javascript">
var searchBox = new SearchBox("searchBox", "search",false,'Search');
</script>
<div id="navrow1" class="tabs">
<ul class="tablist">
<li><a href="index.html"><span>Main&#160;Page</span></a></li>
<li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
<li><a href="modules.html"><span>Reference</span></a></li>
<li>
<div id="MSearchBox" class="MSearchBoxInactive">
<span class="left">
<img id="MSearchSelect" src="search/mag_sel.png"
onmouseover="return searchBox.OnSearchSelectShow()"
onmouseout="return searchBox.OnSearchSelectHide()"
alt=""/>
<input type="text" id="MSearchField" value="Search" accesskey="S"
onfocus="searchBox.OnSearchFieldFocus(true)"
onblur="searchBox.OnSearchFieldFocus(false)"
onkeyup="searchBox.OnSearchFieldChange(event)"/>
</span><span class="right">
<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
</span>
</div>
</li>
</ul>
</div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
<div id="nav-tree">
<div id="nav-tree-contents">
<div id="nav-sync" class="sync"></div>
</div>
</div>
<div id="splitbar" style="-moz-user-select:none;"
class="ui-resizable-handle">
</div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('device_h_pg.html','');});
</script>
<div id="doc-content">
<!-- window showing the filter options -->
<div id="MSearchSelectWindow"
onmouseover="return searchBox.OnSearchSelectShow()"
onmouseout="return searchBox.OnSearchSelectHide()"
onkeydown="return searchBox.OnSearchSelectKey(event)">
<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
<!-- iframe showing the search results (closed by default) -->
<div id="MSearchResultsWindow">
<iframe src="javascript:void(0)" frameborder="0"
name="MSearchResults" id="MSearchResults">
</iframe>
</div>
<div class="header">
<div class="headertitle">
<div class="title">Device Header File &lt;device.h&gt; </div> </div>
</div><!--header-->
<div class="contents">
<div class="textblock"><p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains the following sections that are device specific:</p>
<ul>
<li><a class="el" href="device_h_pg.html#interrupt_number_sec">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li>
<li><a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li>
<li><a class="el" href="device_h_pg.html#device_access">Device Peripheral Access Layer</a> provides definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li>
<li><b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li>
</ul>
<p><a href="Modules.html"><b>Reference</b> </a> describes the standard features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</p>
<h1><a class="anchor" id="interrupt_number_sec"></a>
Interrupt Number Definition</h1>
<p><a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains the enumeration <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all exceptions and interrupts of the device.</p>
<ul>
<li>Negative IRQn values represent processor core exceptions (internal interrupts).</li>
<li>Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the <a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s (deprecated)</a>.</li>
</ul>
<p><b>Example:</b> </p>
<p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p>
<div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">enum</span> IRQn</div>
<div class="line">{</div>
<div class="line"><span class="comment">/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/</span></div>
<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a> = -14, </div>
<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">HardFault_IRQn</a> = -13, </div>
<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a> = -5, </div>
<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a> = -2, </div>
<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> = -1, </div>
<div class="line"><span class="comment">/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/</span></div>
<div class="line"> WAKEUP0_IRQn = 0, </div>
<div class="line"> WAKEUP1_IRQn = 1, </div>
<div class="line"> WAKEUP2_IRQn = 2,</div>
<div class="line"> : :</div>
<div class="line"> : :</div>
<div class="line"> EINT1_IRQn = 30, </div>
<div class="line"> EINT0_IRQn = 31, </div>
<div class="line">} <a class="code" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>;</div>
</div><!-- fragment --><h1><a class="anchor" id="core_config_sect"></a>
Configuration of the Processor and Core Peripherals</h1>
<p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> configures the Cortex-M or SecurCore processor and the core peripherals with <em>#defines</em> that are set prior to including the file <b>core_&lt;cpu&gt;.h</b>.</p>
<p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p>
<p><b>core_cm0.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__CM0_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
</table>
<p><b>core_cm0plus.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__CM0PLUS_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
</table>
<p><b>core_cm3.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__CM3_REV </td><td>0x0101 | 0x0200 </td><td>0x0200 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
</table>
<p><b>core_cm4.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__CM4_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
<tr>
<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
</table>
<p><b>core_cm7.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__CM7_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
<tr>
<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not. See <b>__FPU_DP</b> description below. </td></tr>
<tr>
<td>__FPU_DP </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <b>__FPU_PRESENT</b> and <b>__FPU_DP</b> determine the whether the FPU is with single or double precision as shown in the table below. <br/>
<br/>
<table class="cmtable">
<tr bgcolor="cyan">
<td><b>__FPU_PRESENT</b> </td><td><b>__FPU_DP</b> </td><td><b>Description</b> </td></tr>
<tr>
<td align="center">0 </td><td align="center"><em>ignored</em> </td><td>Processor has no FPU. The value set for <b>__FPU_DP</b> has no influence. </td></tr>
<tr>
<td align="center">1 </td><td align="center">0 </td><td>Processor with FPU with single precision. The file <b>ARMCM7_SP.h</b> has preconfigured settings for this combination. </td></tr>
<tr>
<td align="center">1 </td><td align="center">1 </td><td>Processor with FPU with double precision. The file <b>ARMCM7_DP.h</b> has preconfigured settings for this combination. </td></tr>
</table>
</td></tr>
<tr>
<td>__ICACHE_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not </td></tr>
<tr>
<td>__DCACHE_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not </td></tr>
<tr>
<td>__DTCM_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Data Tightly Coupled Memory is present or not </td></tr>
</table>
<p><b>core_sc000.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__SC000_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
</table>
<p><b>core_sc300.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__SC300_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
</table>
<p><b>core_CM23.h</b> or <b>core_ARMv8MBL.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__ARMv8MBL_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
<tr>
<td>__SAUREGION_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not </td></tr>
<tr>
<td>__VTOR_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
</table>
<p><b>core_CM33.h</b> or <b>core_cm35p.h</b> or <b>core_ARMv8MML.h</b> </p>
<table class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
<tr>
<td>__ARMv8MML_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
<tr>
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
<tr>
<td>__SAUREGION_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not </td></tr>
<tr>
<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not </td></tr>
<tr>
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>3 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
<tr>
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
</table>
<p><b>Example</b> </p>
<p>The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_REV 0x0001 </span><span class="comment">/* Core revision r0p1 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __MPU_PRESENT 1 </span><span class="comment">/* MPU present or not */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __NVIC_PRIO_BITS 3 </span><span class="comment">/* Number of Bits used for Priority Levels */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __Vendor_SysTickConfig 0 </span><span class="comment">/* Set to 1 if different SysTick Config is used */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __FPU_PRESENT 1 </span><span class="comment">/* FPU present or not */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span>.</div>
<div class="line">.</div>
<div class="line"><span class="preprocessor">#include &lt;core_cm4.h&gt;</span> <span class="comment">/* Cortex-M4 processor and core peripherals */</span></div>
</div><!-- fragment --><h1><a class="anchor" id="core_version_sect"></a>
CMSIS Version and Processor Information</h1>
<p>Defines in the core_<em>cpu</em>.h file identify the version of the CMSIS-Core (Cortex-M) and the processor used. The following shows the defines in the various core_<em>cpu</em>.h files that may be used in the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> to verify a minimum version or ensure that the right processor core is used.</p>
<p><b>core_cm0.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __CM0_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define __CORTEX_M (0U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><p><b>core_cm0plus.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __CM0P_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define __CORTEX_M (0U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><p><b>core_cm1.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) </span></div>
<div class="line"><span class="preprocessor">#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) </span></div>
<div class="line"><span class="preprocessor">#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __CM1_CMSIS_VERSION_SUB ) </span></div>
<div class="line"><span class="preprocessor">#define __CORTEX_M (1U) </span></div>
</div><!-- fragment --><p><b>core_cm3.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM3_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __CM3_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define __CORTEX_M (3U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><p><b>core_cm4.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __CM4_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define __CORTEX_M (4U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><p><b>core_cm7.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM7_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM7_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __CM7_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define __CORTEX_M (7U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><p><b>core_sc000.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __SC000_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __SC000_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define __CORTEX_SC (0U) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><p><b>core_sc300.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __SC300_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __SC300_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define __CORTEX_SC (300U) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><p><b>core_ARMv8MBL.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __ARMv8MBL_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define __CORTEX_M (tbd) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><p><b>core_ARMv8MML.h</b> </p>
<div class="fragment"><div class="line"><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
<div class="line"><span class="preprocessor"> __ARMv8MML_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span> </div>
<div class="line"><span class="preprocessor">#define __CORTEX_M (tbd) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
</div><!-- fragment --><h1><a class="anchor" id="device_access"></a>
Device Peripheral Access Layer</h1>
<p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains for each peripheral:</p>
<ul>
<li>Register Layout Typedef</li>
<li>Base Address</li>
<li>Access Definitions</li>
</ul>
<p>The section <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> shows examples for peripheral definitions.</p>
<h1><a class="anchor" id="device_h_sec"></a>
Device.h Template File</h1>
<p>The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> may contain functions to access device-specific peripherals. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> which is provided as part of the CMSIS specification is shown below.</p>
<pre class="fragment">/**************************************************************************//**
* @file &lt;Device&gt;.h
* @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File for
* Device &lt;Device&gt;
* @version V5.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef &lt;Device&gt;_H /* ToDo: replace '&lt;Device&gt;' with your device name */
#define &lt;Device&gt;_H
#ifdef __cplusplus
extern "C" {
#endif
/* ToDo: replace '&lt;Vendor&gt;' with vendor name; add your doxyGen comment */
/** @addtogroup &lt;Vendor&gt;
* @{
*/
/* ToDo: replace '&lt;Device&gt;' with device name; add your doxyGen comment */
/** @addtogroup &lt;Device&gt;
* @{
*/
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum IRQn
{
/* ======================================= ARM Cortex-M# Specific Interrupt Numbers ======================================== */
/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M0 / Cortex-M0+ device */
Reset_IRQn = -15, /*!&lt; -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!&lt; -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!&lt; -13 Hard Fault, all classes of Fault */
SVCall_IRQn = -5, /*!&lt; -5 System Service Call via SVC instruction */
PendSV_IRQn = -2, /*!&lt; -2 Pendable request for system service */
SysTick_IRQn = -1, /*!&lt; -1 System Tick Timer */
/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M3 / Cortex-M4 / Cortex-M7 device */
Reset_IRQn = -15, /*!&lt; -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!&lt; -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!&lt; -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!&lt; -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!&lt; -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!&lt; -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!&lt; -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!&lt; -4 Debug Monitor */
PendSV_IRQn = -2, /*!&lt; -2 Pendable request for system service */
SysTick_IRQn = -1, /*!&lt; -1 System Tick Timer */
/* =========================================== &lt;Device&gt; Specific Interrupt Numbers ========================================= */
/* ToDo: add here your device specific external interrupt numbers
according the interrupt handlers defined in startup_Device.s
eg.: Interrupt for Timer#1 TIM1_IRQHandler -&gt; TIM1_IRQn */
&lt;DeviceInterrupt&gt;_IRQn = 0, /*!&lt; Device Interrupt */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the Arm Cortex-M4 Processor and Core Peripherals =========================== */
/* ToDo: set the defines according your Device */
/* ToDo: define the correct core revision
__CM0_REV if your device is a Cortex-M0 device
__CM3_REV if your device is a Cortex-M3 device
__CM4_REV if your device is a Cortex-M4 device
__CM7_REV if your device is a Cortex-M7 device */
#define __CM#_REV 0x0201 /*!&lt; Core Revision r2p1 */
/* ToDo: define the correct core features for the &lt;Device&gt; */
#define __MPU_PRESENT 1 /*!&lt; Set to 1 if MPU is present */
#define __VTOR_PRESENT 1 /*!&lt; Set to 1 if VTOR is present */
#define __NVIC_PRIO_BITS 3 /*!&lt; Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!&lt; Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0 /*!&lt; Set to 1 if FPU is present */
#define __FPU_DP 0 /*!&lt; Set to 1 if FPU is double precision FPU (default is single precision FPU) */
#define __ICACHE_PRESENT 0 /*!&lt; Set to 1 if I-Cache is present */
#define __DCACHE_PRESENT 0 /*!&lt; Set to 1 if D-Cache is present */
#define __DTCM_PRESENT 0 /*!&lt; Set to 1 if DTCM is present */
/** @} */ /* End of group Configuration_of_CMSIS */
/* ToDo: include the correct core_cm#.h file
core_cm0.h if your device is a CORTEX-M0 device
core_cm3.h if your device is a CORTEX-M3 device
core_cm4.h if your device is a CORTEX-M4 device
core_cm7.h if your device is a CORTEX-M4 device */
#include &lt;core_cm#.h&gt; /*!&lt; Arm Cortex-M# processor and core peripherals */
/* ToDo: include your system_&lt;Device&gt;.h file
replace '&lt;Device&gt;' with your device name */
#include "system_&lt;Device&gt;.h" /*!&lt; &lt;Device&gt; System */
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) &amp;&amp; (__ARMCC_VERSION &gt;= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/* ToDo: add here your device specific peripheral access structure typedefs
following is an example for a timer */
/* =========================================================================================================================== */
/* ================ TMR ================ */
/* =========================================================================================================================== */
/**
* @brief Timer (TMR)
*/
typedef struct
{ /*!&lt; (@ 0x40000000) TIM Structure */
__IOM uint32_t TimerLoad; /*!&lt; (@ 0x00000004) Timer Load */
__IM uint32_t TimerValue; /*!&lt; (@ 0x00000008) Timer Counter Current Value */
__IOM uint32_t TimerControl; /*!&lt; (@ 0x0000000C) Timer Control */
__OM uint32_t TimerIntClr; /*!&lt; (@ 0x00000010) Timer Interrupt Clear */
__IM uint32_t TimerRIS; /*!&lt; (@ 0x00000014) Timer Raw Interrupt Status */
__IM uint32_t TimerMIS; /*!&lt; (@ 0x00000018) Timer Masked Interrupt Status */
__IM uint32_t RESERVED[1];
__IOM uint32_t TimerBGLoad; /*!&lt; (@ 0x00000020) Background Load Register */
} &lt;DeviceAbbreviation&gt;_TMR_TypeDef;
/*@}*/ /* end of group &lt;Device&gt;_Peripherals */
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION &gt;= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/* ToDo: add here your device peripherals base addresses
following is an example for timer */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
/* Peripheral and SRAM base address */
#define &lt;DeviceAbbreviation&gt;_FLASH_BASE (0x00000000UL) /*!&lt; (FLASH ) Base Address */
#define &lt;DeviceAbbreviation&gt;_SRAM_BASE (0x20000000UL) /*!&lt; (SRAM ) Base Address */
#define &lt;DeviceAbbreviation&gt;_PERIPH_BASE (0x40000000UL) /*!&lt; (Peripheral) Base Address */
/* Peripheral memory map */
#define &lt;DeviceAbbreviation&gt;TIM0_BASE (&lt;DeviceAbbreviation&gt;_PERIPH_BASE) /*!&lt; (Timer0 ) Base Address */
#define &lt;DeviceAbbreviation&gt;TIM1_BASE (&lt;DeviceAbbreviation&gt;_PERIPH_BASE + 0x0800) /*!&lt; (Timer1 ) Base Address */
#define &lt;DeviceAbbreviation&gt;TIM2_BASE (&lt;DeviceAbbreviation&gt;_PERIPH_BASE + 0x1000) /*!&lt; (Timer2 ) Base Address */
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/* ToDo: add here your device peripherals pointer definitions
following is an example for timer */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#define &lt;DeviceAbbreviation&gt;_TIM0 ((&lt;DeviceAbbreviation&gt;_TMR_TypeDef *) &lt;DeviceAbbreviation&gt;TIM0_BASE)
#define &lt;DeviceAbbreviation&gt;_TIM1 ((&lt;DeviceAbbreviation&gt;_TMR_TypeDef *) &lt;DeviceAbbreviation&gt;TIM0_BASE)
#define &lt;DeviceAbbreviation&gt;_TIM2 ((&lt;DeviceAbbreviation&gt;_TMR_TypeDef *) &lt;DeviceAbbreviation&gt;TIM0_BASE)
/** @} */ /* End of group &lt;Device&gt; */
/** @} */ /* End of group &lt;Vendor&gt; */
#ifdef __cplusplus
}
#endif
#endif /* &lt;Device&gt;_H */
</pre> </div></div><!-- contents -->
</div><!-- doc-content -->
<!-- start footer part -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
<ul>
<li class="navelem"><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a></li>
<li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
<!--
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6
-->
</li>
</ul>
</div>
</body>
</html>