docs/Core/html/group__cache__functions__m7.html - third_party/github/STMicroelectronics/cmsis_core - Git at Google

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 <p>Functions for Instruction and Data Cache.
 <a href="#details">More...</a></p>
 <table class="memberdecls">
 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
 Content</h2></td></tr>
 <tr class="memitem:group__Icache__functions__m7"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html">I-Cache Functions</a></td></tr>
 <tr class="memdesc:group__Icache__functions__m7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Functions for the instruction cache. <br/></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:group__Dcache__functions__m7"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html">D-Cache Functions</a></td></tr>
 <tr class="memdesc:group__Dcache__functions__m7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Functions for the data cache. <br/></td></tr>
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 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 <p>Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of <span class="XML-Token">[0;4;8;16;32;64]KB</span>. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.</p>
 <p>All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.</p>
 <dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling it.</dd></dl>
 <p>The functions are grouped for:</p>
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 <li><a class="el" href="group__Icache__functions__m7.html">I-Cache Functions</a></li>
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	<div class="contents">

	<p>Functions for Instruction and Data Cache.
	<a href="#details">More...</a></p>
	<table class="memberdecls">
	<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
	Content</h2></td></tr>
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	<tr class="memdesc:group__Icache__functions__m7"><td class="mdescLeft"> </td><td class="mdescRight">Functions for the instruction cache. <br/></td></tr>
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	<tr class="memdesc:group__Dcache__functions__m7"><td class="mdescLeft"> </td><td class="mdescRight">Functions for the data cache. <br/></td></tr>
	<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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	<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
	<p>Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of <span class="XML-Token">[0;4;8;16;32;64]KB</span>. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.</p>
	<p>All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.</p>
	<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling it.</dd></dl>
	<p>The functions are grouped for:</p>
	<ul>
	<li><a class="el" href="group__Icache__functions__m7.html">I-Cache Functions</a></li>
	<li><a class="el" href="group__Dcache__functions__m7.html">D-Cache Functions</a> </li>
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