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<div id="projectname">CMSIS-Core (Cortex-M)
&#160;<span id="projectnumber">Version 5.3.0</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<a href="#define-members">Macros</a> </div>
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<div class="title">Define values<div class="ingroups"><a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a></div></div> </div>
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<p>Define values for MPU region setup.
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gadb0a92c0928c113120567e85ff1ba05c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a></td></tr>
<tr class="memdesc:gadb0a92c0928c113120567e85ff1ba05c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size values of a MPU region (in RASR field) <a href="#gadb0a92c0928c113120567e85ff1ba05c">More...</a><br/></td></tr>
<tr class="separator:gadb0a92c0928c113120567e85ff1ba05c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc4788126d7798469cb862a08d3050cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a></td></tr>
<tr class="memdesc:gabc4788126d7798469cb862a08d3050cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values for MPU region access permissions (in RASR field) <a href="#gabc4788126d7798469cb862a08d3050cc">More...</a><br/></td></tr>
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<tr class="memitem:ga71d41084e984be70a23cb640fd89d1e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a></td></tr>
<tr class="memdesc:ga71d41084e984be70a23cb640fd89d1e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values for MPU region access attributes (in RASR field) <a href="#ga71d41084e984be70a23cb640fd89d1e2">More...</a><br/></td></tr>
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<tr class="memitem:gab23596306119e7831847bd9683de3934"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a></td></tr>
<tr class="memdesc:gab23596306119e7831847bd9683de3934"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cache policy values for MPU region access attributes (in RASR field) <a href="#gab23596306119e7831847bd9683de3934">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The following define values are used with <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> to setup the <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value field in the MPU region.</p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structARM__MPU__Region__t.html" title="Setup information of a single MPU Region. ">ARM_MPU_Region_t</a>, <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>, <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>. </dd></dl>
<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define ARM_MPU_ACCESS_xxx</td>
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<p>The following define values are used to compose the access attributes for an MPU region: </p>
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<th align="left">#define </th><th align="left">TEX </th><th align="left">Shareable </th><th align="left">Cacheable </th><th align="left">Bufferable </th><th align="left">Description </th></tr>
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<td align="left">ARM_MPU_ACCESS_ORDERED </td><td align="left">000b </td><td align="left">1 </td><td align="left">0 </td><td align="left">0 </td><td align="left">Strongly ordered memory </td></tr>
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<td align="left">ARM_MPU_ACCESS_DEVICE(S) </td><td align="left">0s0b </td><td align="left">S </td><td align="left">0 </td><td align="left">S </td><td align="left">Memory mapped peripheral device, shared (S=1) or non-shared (S=0) </td></tr>
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<td align="left">ARM_MPU_ACCESS_NORMAL(O,I,S) </td><td align="left">1BBb </td><td align="left">S </td><td align="left">A </td><td align="left">A </td><td align="left">Normal memory, with outer/inner cache policy (O/I=<a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a>, shared (S=1) or non-share (S=0) </td></tr>
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<td class="memname">#define ARM_MPU_AP_xxx</td>
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<p>The following define values are used to compose the access permission for an MPU region: </p>
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<th align="left">#define </th><th align="left">Value </th><th align="left">Access permissions </th></tr>
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<td align="left">ARM_MPU_AP_NONE </td><td align="left">0x0U </td><td align="left">None: any access generates a permission fault. </td></tr>
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<td align="left">ARM_MPU_AP_PRIV </td><td align="left">0x1U </td><td align="left">Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault. </td></tr>
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<td align="left">ARM_MPU_AP_URO </td><td align="left">0x2U </td><td align="left">Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault. </td></tr>
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<td align="left">ARM_MPU_AP_FULL </td><td align="left">0x3U </td><td align="left">Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated. </td></tr>
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<td align="left">ARM_MPU_AP_PRO </td><td align="left">0x5U </td><td align="left">Privileged Read-only: any unprivileged access or privileged write generates a permission fault. </td></tr>
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<td align="left">ARM_MPU_AP_RO </td><td align="left">0x6U </td><td align="left">Privileged and Unprivileged Read-only: any write generates a permission fault. </td></tr>
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<td class="memname">#define ARM_MPU_CACHEP_xxx</td>
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<p>The following define values are used to compose the cacheability flags within the access attributes for an MPU region: </p>
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<th align="left">#define </th><th align="left">Value </th><th align="left">Cacheability policy </th></tr>
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<td align="left">ARM_MPU_CACHEP_NOCACHE </td><td align="left">00b </td><td align="left">Non-cacheable </td></tr>
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<td align="left">ARM_MPU_CACHEP_WB_WRA </td><td align="left">01b </td><td align="left">Write-back, write and read allocate </td></tr>
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<td align="left">ARM_MPU_CACHEP_WT_NWA </td><td align="left">10b </td><td align="left">Write-through, no write allocate </td></tr>
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<td align="left">ARM_MPU_CACHEP_WB_NWA </td><td align="left">11b </td><td align="left">Write-back, no write allocate </td></tr>
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<td class="memname">#define ARM_MPU_REGION_SIZE_xxx</td>
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<p>The following define values are used to compose the size information for an MPU region:</p>
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<th align="left">#define </th><th align="left">Value </th><th align="left">Description </th></tr>
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<td align="left">ARM_MPU_REGION_SIZE_32B </td><td align="left">0x04U </td><td align="left">Region size 32 Bytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_64B </td><td align="left">0x05U </td><td align="left">Region size 64 Bytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_128B </td><td align="left">0x06U </td><td align="left">Region size 128 Bytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_256B </td><td align="left">0x07U </td><td align="left">Region size 256 Bytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_512B </td><td align="left">0x08U </td><td align="left">Region size 512 Bytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_1KB </td><td align="left">0x09U </td><td align="left">Region size 1 KByte </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_2KB </td><td align="left">0x0AU </td><td align="left">Region size 2 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_4KB </td><td align="left">0x0BU </td><td align="left">Region size 4 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_8KB </td><td align="left">0x0CU </td><td align="left">Region size 8 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_16KB </td><td align="left">0x0DU </td><td align="left">Region size 16 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_32KB </td><td align="left">0x0EU </td><td align="left">Region size 32 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_64KB </td><td align="left">0x0FU </td><td align="left">Region size 64 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_128KB </td><td align="left">0x10U </td><td align="left">Region size 128 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_256KB </td><td align="left">0x11U </td><td align="left">Region size 256 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_512KB </td><td align="left">0x12U </td><td align="left">Region size 512 KBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_1MB </td><td align="left">0x13U </td><td align="left">Region size 1 MByte </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_2MB </td><td align="left">0x14U </td><td align="left">Region size 2 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_4MB </td><td align="left">0x15U </td><td align="left">Region size 4 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_8MB </td><td align="left">0x16U </td><td align="left">Region size 8 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_16MB </td><td align="left">0x17U </td><td align="left">Region size 16 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_32MB </td><td align="left">0x18U </td><td align="left">Region size 32 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_64MB </td><td align="left">0x19U </td><td align="left">Region size 64 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_128MB </td><td align="left">0x1AU </td><td align="left">Region size 128 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_256MB </td><td align="left">0x1BU </td><td align="left">Region size 256 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_512MB </td><td align="left">0x1CU </td><td align="left">Region size 512 MBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_1GB </td><td align="left">0x1DU </td><td align="left">Region size 1 GByte </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_2GB </td><td align="left">0x1EU </td><td align="left">Region size 2 GBytes </td></tr>
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<td align="left">ARM_MPU_REGION_SIZE_4GB </td><td align="left">0x1FU </td><td align="left">Region size 4 GBytes </td></tr>
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